KR20040059409A - Method for fabricating contact hole of semiconductor device - Google Patents
Method for fabricating contact hole of semiconductor device Download PDFInfo
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- KR20040059409A KR20040059409A KR1020020086143A KR20020086143A KR20040059409A KR 20040059409 A KR20040059409 A KR 20040059409A KR 1020020086143 A KR1020020086143 A KR 1020020086143A KR 20020086143 A KR20020086143 A KR 20020086143A KR 20040059409 A KR20040059409 A KR 20040059409A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 230000008569 process Effects 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- 239000008239 natural water Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000001965 increasing effect Effects 0.000 abstract description 8
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
본 발명은 반도체 소자에 관한 것으로, 구체적으로 소오스/드레인 영역의 실리콘의 마이크로 모폴로지(Micro-Morphology)를 증가시킨 후에 살리사이드 공정을 진행하여 콘택 저항을 감소시킬 수 있도록 한 반도체 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. Specifically, a method of forming a contact hole in a semiconductor device in which a contact resistance is reduced by performing a salicide process after increasing the micro-morphology of silicon in a source / drain region. It is about.
반도체 제조 기술은 고집적화와 고성능화를 위해 부단한 연구를 필요로 한다.Semiconductor manufacturing technology requires constant research for high integration and high performance.
이에 부응키 위해 게이트 선폭의 축소 및 구리 배선 공정의 채용등 많은 발전이 있어 왔으며, 소오스/드레인/게이트와 금속 배선의 연결 부위인 콘택홀의 경우는 보더리스(borderless) 콘택 기술을 이용하여 고집적화 및 고성능화를 이루고 있다.To cope with this, there have been many developments such as reduction of gate line width and adoption of copper wiring process.In the case of contact hole, which is a connection point between source / drain / gate and metal wiring, borderless contact technology is used for high integration and high performance. To achieve.
반도체 소자가 고집적화되어 감에 따라 각 단위 소자가 차지하는 면적은 줄어들고 있으며, 콘택이 형성되는 영역 또한 줄어들고 있다. 이로 인하여, 콘택 저항이 증가될 뿐만 아니라 콘택 공정 마진의 확보가 어려워지고 있다.As semiconductor devices are highly integrated, the area occupied by each unit device is decreasing, and the area where contacts are formed is also decreasing. As a result, not only the contact resistance is increased but it is also difficult to secure the contact process margin.
콘택 저항의 증가를 보상하기 위하여, 콘택 부분에 금속-실리사이드층을 적용하고 있다. 또한, 콘택 공정 마진의 확보를 위하여, 소위 보더리스 콘택(Borderless Contace; BLC)이라는 방법을 적용하고 있다.In order to compensate for the increase in contact resistance, a metal-silicide layer is applied to the contact portion. In addition, in order to secure a contact process margin, a so-called borderless contact (BLC) method is applied.
즉, 트랜지스터의 소오스나 드레인 영역에 반도체 소자의 선폭이 미세화 되면서 단위 트랜지스터 소자의 배선 연결을 위한 콘택 형성은 BLC 방법을 적용하여 콘택이 형성되는 영역을 따로 구분하지 않고 직접 트랜지스터의 소오스나 드레인영역에 콘택을 형성시키므로 칩 크기를 더욱 줄이는 효과를 얻을 수 있다.That is, as the line width of the semiconductor device becomes finer in the source or drain region of the transistor, the contact formation for wiring connection of the unit transistor element is applied directly to the source or drain region of the transistor without applying the BLC method. By forming contacts, the chip size can be further reduced.
그러나 이와 같은 종래 기술의 반도체 소자의 콘택 형성 공정은 다음과 같은 문제점이 있다.However, the contact forming process of the semiconductor device of the prior art has the following problems.
소자가 고집적화 될수록 보더리스 콘택 기술은 소오스/드fp인 영역과 소자 분리 영역의 적층 한계를 넘어서게 되고, 현재의 일반적인 0.13㎛ 정도에서의 콘택홀의 임계 치수(critical demension)는 0.16㎛ 정도에 불과하다. 콘택 - 폴리 오버랩과 콘택 - 액티브 오버랩, 즉 리소그래피(lithography) 측면에서의 OPC(Optical Proxymity Correction)등의 작업을 적용하더라도 0.1㎛ 이하가 되는 부분이 발생한다.As devices become more integrated, borderless contact technology goes beyond the stacking limit of source / defp and device isolation regions, and the critical dimension of contact holes in the current 0.13µm range is only 0.16µm. Even when applying operations such as contact-poly overlap and contact-active overlap, that is, optical proxymity correction (OPC) in terms of lithography, a portion of 0.1 μm or less occurs.
액티브 - 콘택 오버레이 등의 정확도에 따라 그 접촉 면적의 변화는 예측하기 어렵다. 이는 동일 셀 내에서의 콘택 저항이 부분적 위치별로 차이를 보일 수 있고, 따라서 소자의 동작에 치명적인 결함이 될 수 있다.Depending on the accuracy of the active-contact overlay, the change in its contact area is difficult to predict. This may cause the contact resistance in the same cell to be different for each partial position, which may result in a fatal defect in the operation of the device.
본 발명은 이와 같은 종래 기술의 반도체 소자의 콘택 형성 공정의 문제를 해결하기 위하여 안출한 것으로, 소오스/드레인 영역의 실리콘의 마이크로 모폴로지(Micro-Morphology)를 증가시킨 후에 살리사이드 공정을 진행하여 콘택 저항을 감소시킬 수 있도록 한 반도체 소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problem of the contact forming process of the semiconductor device of the prior art, and after increasing the micro-Morphology of silicon in the source / drain region, proceed with the salicide process to contact resistance SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of reducing the number of layers.
도 1a내지 도 1f는 본 발명에 따른 반도체 소자의 콘택홀 형성을 위한 공정 단면도1A to 1F are cross-sectional views of a process for forming a contact hole in a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11. 반도체 기판 12. 소자 격리층11. Semiconductor substrate 12. Device isolation layer
13. 게이트 폴리층 14. 소오스/드레인13. Gate poly layer 14. Source / drain
15. 스페이서 16. 버퍼 산화막15. Spacer 16. Buffer Oxide
17. HSG 실리콘층 18. 살리사이드층17. HSG silicon layer 18. Salicide layer
19. BLC 절연층 20. 층간 절연층19. BLC insulation layer 20. Interlayer insulation layer
21. 플러그21. Plug
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택홀 형성 방법은 반도체 기판에 게이트 및 소오스/드레인을 포함하는 트랜지스터를 형성하는 단계; 전면에 버퍼 산화막을 형성하고 살리사이드 블록킹 식각을 진행하는 단계; 상기 버퍼 산화막위에 HSG 실리콘층을 형성하고 이를 이용하여 반도체 기판 및 게이트를 선택적으로 식각하고 HSG 실리콘층을 제거하는 단계; 살리사이드 공정을 진행하고 BLC 절연층, 층간 절연층을 형성하는 단계; BLC 콘택 감광막 패터닝 공정을 이용하여 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method including: forming a transistor including a gate and a source / drain in a semiconductor substrate; Forming a buffer oxide layer on the entire surface and performing salicide blocking etching; Forming an HSG silicon layer on the buffer oxide layer and selectively etching the semiconductor substrate and the gate using the HSG silicon layer and removing the HSG silicon layer; Performing a salicide process to form a BLC insulating layer and an interlayer insulating layer; And forming a plug using a BLC contact photoresist patterning process.
본 발명에 따른 반도체 소자의 콘택홀 형성 방법의 바람직한 실시예에 관하여 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method for forming a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a내지 도 1f는 본 발명에 따른 반도체 소자의 콘택홀 형성을 위한 공정 단면도이다.1A to 1F are cross-sectional views illustrating a process for forming contact holes in a semiconductor device according to the present invention.
본 발명은 보더리스 콘택 형성시에 HSG 기술을 이용하여 폴리실리콘 게이트 지역과 소오스/드레인 지역의 실리콘의 마이크로 모폴로지를 증착시킨 후에 살리사이드 공정을 진행하는 것이다.The present invention proceeds with the salicide process after depositing micromorphology of silicon in the polysilicon gate region and source / drain region using HSG technology in forming the borderless contact.
얕은 접합 형성 기술은 저전력 고성능 반도체 소자의 기본적인 접합 형성 기술이다.The shallow junction formation technique is a basic junction formation technique for low power, high performance semiconductor devices.
또 그에 따른 매우 작은 설계 법칙으로 인해 콘택 홀 형성기술은 보덜스(borderless) 콘택을 채택하지 않을 수 없다.In addition, due to the very small design rule, the contact hole forming technique is forced to adopt borderless contacts.
BLC의 형성기술은 DRAM의 자기 정렬 콘택홀 형성기술과 거의 흡사하며, 산화막 건식식각시 C/F 비를 높이는 방법을 사용하여 하지막인 질화막과의 선택비를 높이는 방법을 사용해 오고 있다.BLC formation technology is almost similar to DRAM self-aligned contact hole formation technology, and has been using a method of increasing the selectivity with the nitride film as the underlying film by increasing the C / F ratio during oxide dry etching.
먼저, 도 1a에서와 같이, 반도체 기판(11)의 소자 격리 영역에 STI 공정으로 소자 격리층(12)을 형성하고 게이트 폴리층(13), 소오스/드레인(14), 나이트라이드 스페이서(15) 그리고 버퍼 산화막(16)을 20 ~ 500Å 두께로 형성한다.First, as shown in FIG. 1A, the device isolation layer 12 is formed in the device isolation region of the semiconductor substrate 11 by the STI process, and the gate poly layer 13, the source / drain 14, and the nitride spacer 15 are formed. Then, the buffer oxide film 16 is formed to a thickness of 20 to 500 Å.
이는 살리사이드 등이 형성되지 않을 부분을 위하여 살리사이드 블록킹 식각을 진행한 후, 살리사이드가 형성될 지역을 보여준다.This shows the region where the salicide will be formed after the salicide blocking etching is performed for the portion where the salicide is not formed.
그리고 도 2b에서와 같이, 버퍼 산화막(16)위에 HSG(Hemi Spherical Grain) 방법을 이용하여 HSG 실리콘층(17)을 형성한다.As shown in FIG. 2B, the HSG silicon layer 17 is formed on the buffer oxide layer 16 using a Hemi Spherical Grain (HSG) method.
이어, 도 2c에서와 같이, HSG 실리콘층(17)을 식각 베리어층을 이용하여 버퍼 산화막(16)을 건식 또는 습식 식각한 후, Cl2, HBr등을 주 식각 가스로 이용하여 반도체 기판(11) 및 게이트 폴리층(13)를 30 ~ 400Å 정도를 식각한 후, HF 또는 BOE등을 이용하여 HSG 실리콘층(17)을 제거한다.Subsequently, as shown in FIG. 2C, after the buffer oxide layer 16 is dry or wet etched using the HSG silicon layer 17 using the etch barrier layer, the semiconductor substrate 11 may be formed using Cl 2 , HBr, or the like as a main etching gas. ) And the gate poly layer 13 is etched at about 30 to 400 kPa, and then the HSG silicon layer 17 is removed using HF or BOE.
여기서, 반도체 기판(11) 및 게이트 폴리층(13)을 CxHyFz(x,y,z 는 0 또는 자연수)를 주 식각 가스로 하여 HSG 산화막 및 실리콘 기판을 동시에 식각하거나, Cl2/HBr 또는 CxHyFz(x,y,z 는 0 또는 자연수) 가스를 이용하여 실리콘 기판 건식 식각시 Ar, He, N2, O2등의 불활성기체 원자 또는 분자를 첨가하여 식각한다.Here, the HSG oxide film and the silicon substrate are simultaneously etched using the semiconductor substrate 11 and the gate poly layer 13 as CxHyFz (x, y, z is 0 or a natural number), or Cl 2 / HBr or CxHyFz ( x, y, z is 0 or natural water) and when the silicon substrate dry etching using an inert gas atoms or molecules such as Ar, He, N 2 , O 2 and the like.
여기서, HSG 실리콘층(17)을 HF 또는 BOE 등의 습식 식각 용액으로 HSG를 제거하지 않고, NH4OH등의 암모늄 베이스 케미컬(ammonium base chemical) 또는 HCl등을 이용하여 제거하거나, HF, BOE, NH4OH, HCL 등의 케미컬을 2가지 이상 복합적으로 사용하여 제거하는 것도 가능하다.Here, the HSG silicon layer 17 is removed using an ammonium base chemical such as NH 4 OH or HCl without removing HSG with a wet etching solution such as HF or BOE, or HF, BOE, It is also possible to use a combination of two or more chemicals such as NH 4 OH and HCL to remove them.
그리고 도 2d에서와 같이, 코발트 살리사이드 공정으로 표면에 살리사이드층(18)을 형성한다.As shown in FIG. 2D, a salicide layer 18 is formed on the surface by a cobalt salicide process.
이어, 도 2e에서와 같이, borderless contact(BLC)을 형성하기 위하여 BLC 절연층(19)를 100 ~ 500Å 두께 증착한 후, BPSG, PE-TEOS 등의 산화막을 증착 및 평탄화하여 층간 절연층(20)을 형성한다.Subsequently, as shown in FIG. 2E, to form a borderless contact (BLC), the BLC insulating layer 19 is deposited to a thickness of 100 to 500 μm, and then an oxide film such as BPSG and PE-TEOS is deposited and planarized to form an interlayer insulating layer 20. ).
여기서, BLC 절연층(19)을 SiN(Si3N4), SiC, SiON 의 어느 하나로 형성한다.Here, the BLC insulating layer 19 is formed of any one of SiN (Si 3 N 4 ), SiC, and SiON.
그리고 도 2f에서와 같이, BLC 콘택 감광막 패터닝 공정을 진행하고 패터닝된 감광막을 이용하여 Ti/TiN, 텅스텐 플러그(21)를 형성한다.As shown in FIG. 2F, the BLC contact photoresist patterning process is performed, and Ti / TiN and tungsten plugs 21 are formed using the patterned photoresist.
이와 같은 본 발명은 HSG(Hemi Spherical Grain) 공정을 이용하여 폴리 실리콘 게이트 및 소오스/드레인 지역을 블랭킷(blanket) 건식 식각 함으로써, 폴리실리콘 게이트 및 소오스/드레인 지역의 표면적을 확장시킴으로써 최종적으로 콘택홀의 접촉 면적(도 1f의 (가) 부분) 증가를 유도하는 방법이다.The present invention uses a blanket dry etching of polysilicon gate and source / drain regions using a Hemi Spherical Grain (HSG) process, thereby expanding the surface area of the polysilicon gate and source / drain regions, thereby finally contacting the contact holes. It is a method of inducing an increase in area ((a) part of FIG.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
이상에서 설명한 본 발명에 따른 반도체 소자의 콘택홀 형성 방법은 다음과 같은 효과가 있다.The above-described method for forming a contact hole in a semiconductor device according to the present invention has the following effects.
본 발명은 HSG(Hemi Spherical Grain) 공정을 이용하여 폴리실리콘 게이트 및 소오스/드레인 지역의 표면적을 확장시킴으로써 최종적으로 콘택홀의 접촉 면적을 증가시켜 공정의 안정성을 확보하는 효과가 있다.The present invention has the effect of securing the stability of the process by finally increasing the contact area of the contact hole by expanding the surface area of the polysilicon gate and the source / drain region using a Hemi Spherical Grain (HSG) process.
본 발명에 의한 콘택홀 형성 방법을 이용할 경우, 0.13㎛이하의 기술에서 극히 미세한 콘트롤이 필요한 트랜치 패터닝 공정, OPC 공정, 콘택-게이트 폴리, 콘택-액티브 오버랩시에 평면적 접촉 면적이 부족하더라도 확장된 콘택 접촉면적을 넓히게 됨으로써 낮은 콘택 저항등을 확보할 수 있는 효과가 있다.When the contact hole forming method according to the present invention is used, even in the case of a trench patterning process, an OPC process, a contact-gate poly, and a contact-active overlap that require extremely fine control in a technology of 0.13 μm or less, even if the contact area is insufficient, the expanded contact is expanded. By increasing the contact area, it is possible to secure a low contact resistance.
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