KR20040058993A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20040058993A KR20040058993A KR1020020085515A KR20020085515A KR20040058993A KR 20040058993 A KR20040058993 A KR 20040058993A KR 1020020085515 A KR1020020085515 A KR 1020020085515A KR 20020085515 A KR20020085515 A KR 20020085515A KR 20040058993 A KR20040058993 A KR 20040058993A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 구리 배선을 형성한 후 구리의 외부 확산을 방지하기 위한 캐핑층을 SiC막과 실리콘 리치 산화막 또는 실리콘 리치 SiC막의 이중 구조로 형성함으로써 구리의 저유전 절연막으로의 외부 확산을 효과적으로 차단하여 반도체 소자의 신뢰성을 향상시킬 수 있는 동시에 유효 유전 상수를 최소화시켜 소자의 동작 속도를 향상시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a low dielectric of copper is formed by forming a capping layer for preventing external diffusion of copper after forming a copper wiring in a double structure of a SiC film and a silicon rich oxide film or a silicon rich SiC film. The present invention relates to a method for manufacturing a semiconductor device that can effectively block external diffusion into an insulating film to improve the reliability of the semiconductor device and at the same time minimize the effective dielectric constant to improve the operation speed of the device.
반도체 소자의 동작 속도를 향상시키기 위해 사용되는 구리는 식각의 어려움 때문에 다마신(damascene) 공정을 이용하여 형성한다. 다마신 공정은 식각 정지막과 층간 절연막을 다층으로 적층하고 이들을 식각하여 비아홀과 트렌치를 확정한 후 구리를 채우고 CMP 공정에 의해 구리를 연마함으로써 플러그와 금속 배선을 한번에 형성할 수 있는 공정이다. 이러한 다마신 공정을 적용하는 반도체 소자의 제조 공정에서 소자의 동작 속도를 더욱 향상시키기 위해 층간 절연막을 저유전 물질로 형성하고, 매립된 구리의 외부 확산을 방지하기 위해 구리 배선 상부에 캐핑층을 형성하고 있다. 이러한 캐핑층으로는 SiC막을 주로 이용하고 있는데, SiC막은 유전 상수 4.5 정도의 막으로 구리의 외부 확산을 효과적으로 차단하지 못하는 문제가 있다. 따라서, 구리의 외부 확산을 효과적으로 방지하기 위해서는 SiN막 또는 SiCN막을 사용해야 한다. 그러나, SiN막 및 SiCN막의 유전 상수는 5.0 이상으로 크기 때문에 유효 유전 상수를 증가시켜 소자의 동작 속도를 저하시킨다.Copper, which is used to improve the operating speed of semiconductor devices, is formed using a damascene process due to the difficulty of etching. In the damascene process, the etch stop film and the interlayer insulating film are stacked in multiple layers, the vias and trenches are etched, the copper is filled, and the copper is polished by the CMP process to form the plug and the metal wiring at once. In the process of manufacturing a semiconductor device applying the damascene process, an interlayer insulating film is formed of a low dielectric material to further improve the operation speed of the device, and a capping layer is formed on the copper wiring to prevent external diffusion of embedded copper. Doing. As the capping layer, a SiC film is mainly used, but the SiC film has a dielectric constant of about 4.5, which does not effectively block external diffusion of copper. Therefore, in order to effectively prevent the external diffusion of copper, a SiN film or a SiCN film should be used. However, since the dielectric constants of the SiN film and the SiCN film are larger than 5.0, the effective dielectric constant is increased to lower the operation speed of the device.
본 발명은 유효 유전 상수를 증가시키지 않으면서 구리의 외부 확산을 효과적으로 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.The present invention provides a method for manufacturing a semiconductor device that can effectively prevent the external diffusion of copper without increasing the effective dielectric constant.
본 발명의 다른 목적은 구리의 외부 확산을 방지하기 위한 캐핑층을 이중 구조로 형성함으로써 유효 유전 상수를 증가시키지 않으면서 구리의 외부 확산을 효과적으로 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device that can effectively prevent the external diffusion of copper without increasing the effective dielectric constant by forming a capping layer for preventing the external diffusion of copper in a double structure.
상기의 목적을 달성하기 위해 본 발명에서는 구리를 이용하여 금속 배선을 형성한 후 구리의 외부 확산을 방지하기 위한 캐핑층을 SiC막과 실리콘 리치 산화막 또는 실리콘 리치 SiC막의 이중 구조로 형성한다. 이 경우 구리가 SiC막을 통과하더라도 실리콘 리치 산화막 또는 실리콘 리치 SiC막에 개터링(gattering)되어 저유전 절연막까지 침투하지 못하게 함으로써 유효 유전 상수를 증가시키지 않아 소자의 신뢰성을 향상시킨다.In order to achieve the above object, in the present invention, after forming a metal wiring using copper, a capping layer for preventing external diffusion of copper is formed in a double structure of a SiC film and a silicon rich oxide film or a silicon rich SiC film. In this case, even if the copper passes through the SiC film, the silicon-rich oxide film or the silicon-rich SiC film is gated and prevented from penetrating into the low-k dielectric layer, thereby increasing the effective dielectric constant, thereby improving reliability of the device.
도 1은 본 발명에 따른 구리 다마신 공정을 적용하는 반도체 소자의 제조 방법을 설명하기 위해 도시한 소자의 단면도.1 is a cross-sectional view of a device shown for explaining a method of manufacturing a semiconductor device applying the copper damascene process according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 반도체 기판 102 : 제 1 식각 정지막101 semiconductor substrate 102 first etch stop film
103 : 제 1 층간 절연막 104 : 제 2 식각 정지막103: first interlayer insulating film 104: second etching stop film
105 : 제 2 층간 절연막 106 : 확산 방지막105: second interlayer insulating film 106: diffusion barrier film
107 : 시드층 108 : 구리층107: seed layer 108: copper layer
109 : SiC막 110 : 실리콘 리치 산화막109: SiC film 110: silicon rich oxide film
111 : 제 3 층간 절연막111: third interlayer insulating film
본 발명에 따른 반도체 소자의 제조 방법은 소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하는 단계와, 상기 층간 절연막을 패터닝하여 다마신 패턴을 형성한 후 상기 다마신 패턴이 매립되도록 구리층을 형성하는 단계와, 상기 구리층을 연마하여 구리 배선을 형성하는 단계와, 전체 구조 상부에 이중 구조의 캐핑층을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film on a semiconductor substrate having a predetermined structure, patterning the interlayer insulating film to form a damascene pattern, and then forming a copper layer to fill the damascene pattern. And forming a copper wiring by polishing the copper layer, and forming a capping layer having a double structure on the entire structure.
상기 캐핑층은 SiC막 및 실리콘 리치 산화막을 적층하여 형성하거나, SiC막 및 실리콘 리치 SiC막을 적층하여 형성하는 것을 특징으로 한다.The capping layer is formed by stacking a SiC film and a silicon rich oxide film, or by stacking a SiC film and a silicon rich SiC film.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.
도 1은 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 소자의 단면도이다.1 is a cross-sectional view of a device illustrated to explain a method of manufacturing a semiconductor device according to the present invention.
소정의 구조가 형성된 반도체 기판(101) 상부에 제 1 식각 정지막(102), ㅈ 1 층간 절연막(103), 제 2 식각 정지막(104) 및 제 2 층간 절연막(105)을 순차적으로 형성한다. 여기서, 제 1 및 제 2 식각 정지막(102 및 104)은 비아홀 및 트렌치를 형성하기 위한 식각 공정에서 과도 식각에 의한 마이크로트렌치 등이 형성되는 것을 방지하기 위해 제 1 및 제 2 층간 절연막(103 및 105)과 비교하여 식각 선택비가 우수한 막으로 형성한다. 그리고, 제 1 및 제 2 층간 절연막(103 및 105)는 저유전 절연막을 이용하여 형성한다. 다마신 공정으로 제 2 층간 절연막(105) 및 제 2 식각 정지막(104)을 식각하여 트렌치를 형성한 후 제 1 층간 절연막(103) 및 제 1 식각 정지막(102)을 식각하여 하부 배선을 노출시키는 비아홀을 형성함으로써듀얼 다마신 패턴을 형성한다. 전체 구조 상부에 확산 방지막(106) 및 시드층(107)을 형성한 후 비아홀 및 트렌치가 매립되도록 전체 구조 상부에 구리층(108)을 형성한다. CMP 공정을 실시하여 구리층(108), 시드층(107) 및 확산 방지막(106)을 연마하여 구리 배선을 형성한다. 구리 배선의 외부 확산을 방지하기 위해 SiC막(109) 및 실리콘 리치 산화막(110)이 적층된 이중 구조의 캐핑층을 형성한다. 이때, 실리콘 리치 산화막(110) 대신에 실리콘 리치 SiC막을 형성하기도 한다. 그리고, 전체 구조 상부에 저유전 절연막을 이용하여 제 3 층간 절연막(111)을 형성한다.The first etch stop layer 102, the first interlayer insulating layer 103, the second etch stop layer 104, and the second interlayer insulating layer 105 are sequentially formed on the semiconductor substrate 101 on which the predetermined structure is formed. . The first and second etch stop layers 102 and 104 may be formed of the first and second interlayer insulating layers 103 and 103 to prevent the formation of micro trenches or the like due to excessive etching in an etching process for forming via holes and trenches. Compared with 105), the film has an excellent etching selectivity. The first and second interlayer insulating films 103 and 105 are formed using a low dielectric insulating film. After the trench is formed by etching the second interlayer insulating layer 105 and the second etch stop layer 104 by a damascene process, the first interlayer insulating layer 103 and the first etch stop layer 102 are etched to form a lower wiring. A dual damascene pattern is formed by forming exposed via holes. After the diffusion barrier layer 106 and the seed layer 107 are formed on the entire structure, the copper layer 108 is formed on the entire structure so that the via holes and the trench are filled. The CMP process is performed to polish the copper layer 108, the seed layer 107, and the diffusion barrier film 106 to form a copper wiring. In order to prevent external diffusion of the copper wiring, a double capping layer in which the SiC film 109 and the silicon rich oxide film 110 are stacked is formed. In this case, a silicon rich SiC film may be formed instead of the silicon rich oxide film 110. Then, the third interlayer insulating film 111 is formed on the entire structure by using the low dielectric insulating film.
상기에서 캐핑층을 이중 구조로 형성하는데, 먼저 유전 상수가 4.5 이하인 일반적인 SiC막(109)을 형성하고, 그 상부에 실리콘 리치 산화막(110) 또는 실리콘 리치 SiC막등 실리콘 리치 형태의 막을 형성한다. 이 경우 구리가 후속 열처리 공정에 의해 SiC막(109)을 통과할지라도 실리콘 리치 형태의 막에 개터링되기 때문에 구리가 저유전 절연막까지 침투되는 것을 방지할 수 있다. 즉, 실리콘 리치 형태의 막에 의한 넌브리징(non bridging)으로 인해 구리의 개터링이 가능하게 되는 것이다. 이때, 실리콘 리치 형태의 막은 유전 상수가 약 4.5 정도이므로 유효 유전 상수를 최소화할 수 있어 반도체 소자의 동작 속도 특성 및 신뢰성 특성을 향상시킬 수 있다.The capping layer is formed in a double structure. First, a general SiC film 109 having a dielectric constant of 4.5 or less is formed, and a silicon rich film such as a silicon rich oxide film 110 or a silicon rich SiC film is formed thereon. In this case, even though the copper passes through the SiC film 109 by a subsequent heat treatment process, the copper can be prevented from penetrating into the low-k dielectric layer because it is formed in the silicon-rich film. In other words, non-bridging by the silicon rich film enables the guttering of copper. In this case, since the silicon-rich film has a dielectric constant of about 4.5, the effective dielectric constant may be minimized, thereby improving operating speed characteristics and reliability characteristics of the semiconductor device.
상술한 바와 같이 본 발명에 의하면 구리 배선을 형성한 후 구리의 외부 확산을 방지하기 위한 캐핑층을 SiC막과 실리콘 리치 형태의 막으로 형성함으로써 구리의 저유전 절연막으로의 외부 확산을 효과적으로 차단하여 반도체 소자의 신뢰성을 향상시킬 수 있는 동시에 유효 유전 상수를 최소화시켜 소자의 동작 속도를 향상시킬 수 있다.As described above, according to the present invention, after the copper wiring is formed, a capping layer for preventing the external diffusion of copper is formed of the SiC film and the silicon rich type film to effectively block the external diffusion of copper into the low dielectric insulating film, thereby The reliability of the device can be improved while the effective dielectric constant can be minimized to speed up the device's operation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100771370B1 (en) * | 2005-12-29 | 2007-10-30 | 동부일렉트로닉스 주식회사 | Metal line in semiconductor device and fabricating method thereof |
| KR20190058154A (en) * | 2017-11-21 | 2019-05-29 | 삼성전자주식회사 | Semiconductor device |
-
2002
- 2002-12-27 KR KR10-2002-0085515A patent/KR100475536B1/en active IP Right Grant
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100771370B1 (en) * | 2005-12-29 | 2007-10-30 | 동부일렉트로닉스 주식회사 | Metal line in semiconductor device and fabricating method thereof |
| KR20190058154A (en) * | 2017-11-21 | 2019-05-29 | 삼성전자주식회사 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100475536B1 (en) | 2005-03-10 |
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