KR20040057656A - Method for manufacturing bit line - Google Patents

Method for manufacturing bit line Download PDF

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KR20040057656A
KR20040057656A KR1020020084423A KR20020084423A KR20040057656A KR 20040057656 A KR20040057656 A KR 20040057656A KR 1020020084423 A KR1020020084423 A KR 1020020084423A KR 20020084423 A KR20020084423 A KR 20020084423A KR 20040057656 A KR20040057656 A KR 20040057656A
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film
etching
gas
bit line
hard mask
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KR1020020084423A
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Korean (ko)
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KR100587060B1 (en
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조성윤
김승범
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for forming a bit line is provided to obtain fine pattern and to reduce loss of a hard mask by using a Ta film as an anti-reflective coating layer. CONSTITUTION: A Ti/TiN layer as a glue layer, a tungsten film, a silicon nitride layer as a hard mask, and a Ta film as an anti-reflective coating layer are sequentially formed on a substrate(10). An anti-reflective coating film made of Ta is formed by first dry-etching the Ta film using Cl-based gas. A hard mask film(13a) of silicon nitride is formed by second dry-etching the silicon nitride layer using Cl-based gas. A tungsten film(12a) is formed by third dry-etching the tungsten film using F-based gas. A glue film(11a) is formed by fourth dry-etching the Ti/TiN layer using Cl-based gas, thereby forming a bit line.

Description

비트라인 형성 방법{METHOD FOR MANUFACTURING BIT LINE}Bit line formation method {METHOD FOR MANUFACTURING BIT LINE}

본 발명은 반도체소자의 제조 방법에 관한 것으로, 보다 상세하게는 비트라인용 하드 마스크의 실리콘 질화막 손실을 줄일 수 있는 비트라인 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a bit line forming method that can reduce the silicon nitride film loss of the hard mask for bit lines.

비트라인의 하드 마스크 식각 공정 시, 이 후의 셀프어라인 콘택 공정 마진을 확보하기 위해 하드 마스크의 두께를 3000Å이상으로 형성하는데, 이로 인해 식각 타겟 과도로 패턴에 줄무늬 형상이 나타나거나 탑 부분의 손실이 발생된다.또한, 패턴의 높이로 CD(Critical Dimension) 제어가 어려울 뿐만 아니라,구형 결함도 발생된다.In the hard mask etching process of the bit line, the thickness of the hard mask is formed to be 3000 Å or more in order to secure the margin of the subsequent self-aligned contact process. In addition, CD (Critical Dimension) control is difficult not only with the height of the pattern, but also spherical defects are generated.

한편, 반사방지막으로 SiON막을을 사용하며, 텅스텐막 식각 공정 시, F계열의 식각가스로 식각할 경우, F계열의 식각가스에 SiON막이 식각이 잘되어 하부의 하드마스크용 실리콘 질화막의 손실이 많이 발생된다.On the other hand, a SiON film is used as an anti-reflection film, and during the tungsten film etching process, when the F-type etching gas is etched, the SiON film is well etched in the F-type etching gas, which causes a large loss of the silicon nitride film for the hard mask at the bottom. Is generated.

또한, 상기 SiON막의 반사방지막을 이용하여 마스크 공정 시, 얇은 패턴을 미세하게 제어하기 어려운 문제점이 있었다.In addition, in the mask process using the anti-reflection film of the SiON film, there was a problem that it is difficult to finely control the thin pattern.

따라서, 본 발명은 비트라인용 하드 마스크의 실리콘 질화막 손실을 줄일 수 있는 비트라인 형성 방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a bit line which can reduce the silicon nitride film loss of the hard mask for the bit line.

도 1a 내지 도 1f는 본 발명에 따른 비트라인 형성 방법을 설명하기 위한 공정단면도.1A to 1F are cross-sectional views illustrating a method of forming a bit line according to the present invention.

상기 목적을 달성하기 위해 본 발명에 따른 비트라인 형성 방법은 반도체기판 상에 접착 역할을 하는 Ti/TiN막, 비트라인용 텅스텐막, 하드마스크용 실리콘 질화막 및 반사방지막용 Ta막을 차례로 형성하는 단계와, Ta막 위에 비트라인영역이 정의된 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하고 Cl계열의 식각가스를 이용하여 상기 Ta막을 1차 건식 식각하는 단계와, 감광막 패턴을 마스크로 하고 Cl계열의 식각가스를 이용하여 하드마스크용 실리콘 질화막을 2차 건식 식각하는 단계와, 감광막 패턴을 제거하는 단계와, 잔류된 Ta막, 하드마스크용 실리콘 질화막을 마스크로 하고 F계열의 식각가스를 이용하여 텅스텐막을 3차 건식 식각하는 단계와, 잔류된 막들을 마스크로 하고 Cl계열의 식각가스를 이용하여 Ti/TiN막을 4차 건식 식각하여 비트라인을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, the method of forming a bit line according to the present invention includes the steps of sequentially forming a Ti / TiN film, a tungsten film for a bit line, a silicon nitride film for a hard mask, and a Ta film for an antireflection film on a semiconductor substrate; And forming a photoresist pattern having a bit line region defined on the Ta film, performing a first dry etching of the Ta film using a photoresist pattern as a mask and using an etching gas of Cl series, and using a photoresist pattern as a mask Secondary dry etching of the hard mask silicon nitride film using the etching gas of the series, removing the photoresist pattern, using the remaining Ta film and the silicon nitride film for the hard mask as a mask, and using the F-type etching gas Tertiary dry etching the tungsten film, and using the remaining films as a mask and performing fourth dry etching of the Ti / TiN film using Cl-based etching gas. Characterized by including the step of forming a line.

상기 1차 건식 식각 공정은 MERIE 및 ECR 중 어느 하나의 방식을 이용한다.The first dry etching process uses one of MERIE and ECR.

상기 1차 건식 식각 공정에서, 식각가스로 CCl4 또는 Cl2/O2의 혼합 가스를 이용한다.In the first dry etching process, a mixed gas of CCl 4 or Cl 2 / O 2 is used as an etching gas.

상기 2차 식각 공정에서, 식각 가스로 CHF3, CF4,O2 및 Ar의 혼합 가스를 이용한다.In the secondary etching process, a mixed gas of CHF 3, CF 4, O 2 and Ar is used as an etching gas.

상기 3차 식각 공정에서, 식각 가스로 SF6/N2 혼합가스를 이용한다.In the tertiary etching process, SF6 / N2 mixed gas is used as an etching gas.

상기 4차 식각 공정에서, 식각 가스로 Cl2/BCl3 혼합 가스를 이용한다.In the fourth etching process, Cl2 / BCl3 mixed gas is used as an etching gas.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 f는 본 발명에 따른 비트라인 형성 방법을 설명하기 위한 공정단면도이다.1A to F are cross-sectional views illustrating a method of forming a bit line according to the present invention.

본 발명에 따른 비트라인 형성 방법은, 도 1a에 도시된 바와 같이, 먼저 반도체기판(10) 위에 접착막(11), 비트라인용 텅스텐막(12), 하드마스크용 실리콘 질화막(13) 및 반사방지막(14)을 차례로 형성한다. 이때, 상기 접착막(11)은 기판(10)과 텅스텐막(12) 간의 부착력을 향상시키기 위한 것이다. 또한, 상기 반사방지막(14)의 재질로는 Ta막을 사용하며, 상기 Ta막은 원자수가 많아 미세 패턴 형성에 용이하다.In the method of forming a bit line according to the present invention, as shown in FIG. 1A, an adhesive film 11, a tungsten film 12 for a bit line 12, a silicon nitride film 13 for a hard mask and a reflection are first formed on a semiconductor substrate 10. The prevention film 14 is formed in order. In this case, the adhesive film 11 is to improve the adhesion between the substrate 10 and the tungsten film 12. In addition, as the material of the anti-reflection film 14, a Ta film is used, and the Ta film has a large number of atoms to facilitate formation of a fine pattern.

이어, 상기 반사방지막(14) 위에 비트라인영역이 정의된 감광막 패턴(20)을 형성한다.Subsequently, a photoresist pattern 20 having a bit line region defined on the antireflection layer 14 is formed.

그런 다음, 도 1b에 도시된 바와 같이, 감광막 패턴(20)을 마스크로 하고 상기 반사방지막을 1차로 건식 식각한다. 이때, 상기 1차 건식 식각 공정은 MERIE, ECR 등의 방식을 이용한다. 상기 MERIE 방식은 식각 시 표면의 자연산화막 제거를 위해 CCl4 또는 Cl2/O2가스를 혼합한 식각 가스를 이용한다. 상기 Cl계열의 식각가스를 사용할 시, TaCl5의 반응부산물이 발생되는데, 높은 끓는점으로 인해 낮은 휘발성 특성으로 폴리머 형성도 용이하다. 미설명된 도면 부호 14a는 상기 건식 식각 공정 후 잔류된 반사방지막을 나타낸 것이다.Then, as illustrated in FIG. 1B, the photoresist pattern 20 is used as a mask and the antireflection film is first dry-etched. In this case, the first dry etching process uses a method such as MERIE, ECR. The MERIE method uses an etching gas mixed with CCl4 or Cl2 / O2 gas to remove the natural oxide layer on the surface during etching. When the Cl-based etching gas is used, a reaction by-product of TaCl 5 is generated. Due to the high boiling point, it is easy to form a polymer due to low volatility. Unexplained reference numeral 14a represents an antireflection film remaining after the dry etching process.

이 후, 도 1c에 도시된 바와 같이, 상기 감광막 패턴(20)을 마스크로 하고 상기 실리콘 질화막을 2차로 건식 식각한다. 이때, 상기 건식 식각 공정 시 사용되는 식각가스로는 반사방지막의 건식 식각 공정과 동일한 F계열의 식각가스를 이용하는데, CHF3, CF4,O2 및 Ar의 혼합 가스를 이용한다.Thereafter, as illustrated in FIG. 1C, the photoresist layer pattern 20 is used as a mask and the silicon nitride layer is secondly dry etched. In this case, the etching gas used in the dry etching process uses an F-type etching gas, which is the same as the dry etching process of the anti-reflection film, and uses a mixed gas of CHF 3, CF 4, O 2, and Ar.

이어, 도 1d에 도시된 바와 같이, 상기 하드 마스크용 실리콘 질화막의 식각 공정이 완료되면, 감광막 패턴을 제거한다.Subsequently, as shown in FIG. 1D, when the etching process of the silicon nitride film for hard mask is completed, the photoresist pattern is removed.

그런 다음, 도 1e에 도시된 바와 같이, 잔류된 반사방지막 및 하드마스크용 실리콘 질화막을 마스크로 상기 텅스텐막을 3차로 건식 식각한다. 이때, 상기 텅스텐막의 3차 건식 식각 공정에서, 식각가스로 SF6/N2가스를 이용한다.Then, as shown in FIG. 1E, the tungsten film is dry-etched in the third order using the remaining antireflection film and the silicon nitride film for the hard mask as a mask. In this case, in the third dry etching process of the tungsten film, SF6 / N2 gas is used as an etching gas.

한편, 상기 텅스텐막을 식각하는데 있어서, F계열의 식각가스를 사용하기 때문에 패턴 상부에 있는 반사방지막의 Ta 성분은 F계열에 식각이 잘되질 않는다. 즉, 텅스텐막 식각 시 선택비가 높아 텅스텐 식각 후에도 Ta일부가 잔류되어 (도면부호 14a 참조) 하드 마스크용 실리콘 질화막의 손실에는 영향을 미치지 않는다.On the other hand, in etching the tungsten film, since the F series etching gas is used, the Ta component of the antireflection film on the upper part of the pattern is not etched well in the F series. That is, since the selectivity is high during tungsten film etching, a part of Ta remains even after tungsten etching (see reference numeral 14a), so that the loss of the silicon nitride film for the hard mask is not affected.

이 후, 도 1f에 도시된 바와 같이, 상기 잔류된 반사방지막, 하드마스크용 실리콘 질화막 및 텅스텐막을 마스크로 하고 상기 Ti/TiN막을 4차로 건식 식각하여 비트라인(B)을 형성한다. 이때, 상기 Ti/TiN막의 4차 건식 식각 공정에서, 식각가스로 Cl2/BCl3 혼합 가스를 이용한다. 또한, 상기 Cl계열의 식각 가스에 의해 잔류되어 있던 반사방지막의 Ta 성분이 완전히 제거된다. 한편, 상기 잔류된 하드 마스크용 실리콘 질화막은 F계열의 식각가스에 의해 식각되기 때문에 Cl계열의 식각 가스를 이용한 Ti/TiN막의 식각 공정에서는 제거되지 않고 계속 잔류된다.Thereafter, as shown in FIG. 1F, the bit-line B is formed by dry etching the Ti / TiN film in the fourth order using the remaining antireflection film, the hard mask silicon nitride film, and the tungsten film as a mask. At this time, in the fourth dry etching process of the Ti / TiN film, Cl2 / BCl3 mixed gas is used as the etching gas. In addition, the Ta component of the anti-reflection film remaining by the Cl-based etching gas is completely removed. On the other hand, since the remaining silicon nitride film for hard mask is etched by the F-based etching gas, it remains without being removed in the etching process of the Ti / TiN film using Cl-based etching gas.

따라서, 하드마스크용 실리콘 질화막은 식각 공정이 모두 완료된 후에도 최초 증착 두께에 대비하여 손실이 미소하게 때문에 원하는 잔류 두께를 확보할 수 있을 뿐만 아니라 균일도(uniformity)도 양호하여 이 후의 셀프 어라인 콘택 또는 화학적 기계적 연마(chemical mechnical polishing) 공정 마진을 확보할 수 있다.Therefore, even after the etching process is completed, the silicon nitride film for the hard mask has a small loss compared to the initial deposition thickness, so that the desired residual thickness can be secured and the uniformity is good. Mechanical mechnical polishing process margins can be secured.

또한, 하드마스크용 실리콘 질화막 손실이 최소화되기 때문에 하드마스크용 실리콘막의 증착 두께도 줄일 수 있고, 미세 패턴에 의해 CD 제어도 용이하다.In addition, since the silicon nitride film loss for the hard mask is minimized, the deposition thickness of the hard mask silicon film can be reduced, and the CD pattern can be easily controlled by the fine pattern.

이상에서와 같이, 본 발명에서는 반사방지막으로 Ta막을 사용함으로써, 마스크 공정 시 미세 패턴을 형성할 수 있고, Ta막이 F계열의 식각가스보다는 Cl계열의 식각가스에 의해 식각이 잘되므로 이 후의 텅스텐막 식각 공정 시 하드마스크의 손실을 줄일 수 있다. 또한, 하드마스크의 두께, 높이와 식각 타겟 과도로 발생되는 탑부분의 손실, CD제어의 어려움 및 구형 결함 발생 등을 방지할 수 있다.As described above, in the present invention, by using the Ta film as the anti-reflection film, a fine pattern can be formed during the mask process, and since the Ta film is etched by the Cl-based etching gas rather than the F-based etching gas, the subsequent tungsten film The hard mask loss can be reduced during the etching process. In addition, it is possible to prevent the loss of the top portion caused by the thickness, height and etching target of the hard mask, difficulty in CD control, and spherical defects.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

반도체기판 상에 접착 역할을 하는 Ti/TiN막, 비트라인용 텅스텐막, 하드마스크용 실리콘 질화막 및 반사방지막용 Ta막을 차례로 형성하는 단계와,Forming a Ti / TiN film, a tungsten film for bit lines, a silicon nitride film for hard mask, and a Ta film for anti-reflective film, in turn, on the semiconductor substrate; 상기 Ta막 위에 비트라인영역이 정의된 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern having a bit line region defined on the Ta film; 상기 감광막 패턴을 마스크로 하고 Cl계열의 식각가스를 이용하여 상기 Ta막을 1차 건식 식각하는 단계와,First dry etching the Ta film by using the photosensitive film pattern as a mask and using an etching gas of Cl series; 상기 감광막 패턴을 마스크로 하고 Cl계열의 식각가스를 이용하여 상기 하드마스크용 실리콘 질화막을 2차 건식 식각하는 단계와,Second dry etching the silicon nitride film for the hard mask by using the photosensitive film pattern as a mask and using an etching gas of Cl series; 상기 감광막 패턴을 제거하는 단계와,Removing the photoresist pattern; 상기 잔류된 Ta막, 하드마스크용 실리콘 질화막을 마스크로 하고 F계열의 식각가스를 이용하여 상기 텅스텐막을 3차 건식 식각하는 단계와,Tertiary dry etching the tungsten film using the remaining Ta film and the silicon nitride film for the hard mask as a mask and an etching gas of an F series; 상기 잔류된 막들을 마스크로 하고 Cl계열의 식각가스를 이용하여 상기 Ti/TiN막을 4차 건식 식각하여 비트라인을 형성하는 단계를 포함한 것을 특징으로 하는 비트라인 형성 방법.And forming a bit line by performing fourth dry etching of the Ti / TiN film using the Cl-based etching gas as a mask. 제 1항에 있어서, 상기 1차 건식 식각 공정은 MERIE 및 ECR 중 어느 하나의 방식을 이용하는 것을 특징으로 하는 비트라인 형성 방법.The method of claim 1, wherein the first dry etching process uses any one of MERIE and ECR. 제 1항에 있어서, 상기 1차 건식 식각 공정에서, 식각가스로 CCl4 또는Cl2/O2의 혼합 가스를 이용하는 것을 특징으로 하는 비트라인 형성 방법.The method of claim 1, wherein in the first dry etching process, a mixed gas of CCl 4 or Cl 2 / O 2 is used as an etching gas. 제 1항에 있어서, 상기 2차 식각 공정에서, 식각 가스로 CHF3, CF4,O2 및 Ar의 혼합 가스를 이용하는 것을 특징으로 하는 비트라인 형성 방법.The method of claim 1, wherein in the secondary etching process, a mixed gas of CHF 3, CF 4, O 2, and Ar is used as an etching gas. 제 1항에 있어서, 상기 3차 식각 공정에서, 식각 가스로 SF6/N2 혼합가스를The method of claim 1, wherein in the tertiary etching process, the SF6 / N2 mixed gas as an etching gas 이용하는 것을 특징으로 하는 비트라인 형성 방법.And using the bit line forming method. 제 1항에 있어서, 상기 4차 식각 공정에서, 식각 가스로 Cl2/BCl3 혼합 가스를 이용하는 것을 특징으로 하는 비트라인 형성 방법.The method of claim 1, wherein in the fourth etching process, a Cl 2 / BCl 3 mixed gas is used as an etching gas.
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KR101033985B1 (en) * 2004-11-19 2011-05-11 주식회사 하이닉스반도체 Method for forming bit lines of semiconductor devices
WO2022142266A1 (en) * 2021-01-04 2022-07-07 长鑫存储技术有限公司 Method for manufacturing semiconductor structure, and semiconductor structure
US11871560B2 (en) 2021-01-04 2024-01-09 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

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KR20220106498A (en) 2021-01-22 2022-07-29 삼성전기주식회사 Multilayered capacitor and manufacturing method for the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101033985B1 (en) * 2004-11-19 2011-05-11 주식회사 하이닉스반도체 Method for forming bit lines of semiconductor devices
WO2022142266A1 (en) * 2021-01-04 2022-07-07 长鑫存储技术有限公司 Method for manufacturing semiconductor structure, and semiconductor structure
US11871560B2 (en) 2021-01-04 2024-01-09 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

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