KR20040050410A - Class D power amp having protection circuit - Google Patents

Abstract

PURPOSE: A class D power amplifier having a protection circuit is provided to protect an operation of MOS transistors driven by a driver by blocking an operation of the driver according to short-circuit of a speaker output signal. CONSTITUTION: The first and the second drivers(202,204) input a PWM(Pulse Width Modulation) signal. An external circuit part(210) generates a speaker output signal by including MOS transistors and an LC filter comprising an inductor and a capacitor. An inverter(220) is driven by an output of the second driver. An output signal mapper(250) maps an operation range of the speaker output signal to an internal operation range of the class D amplifier. A low pass filter(230) demodulates an output of the inverter to an analog signal. The first and the second threshold area generation parts(240,260) set each of the output signal mapper output and the low pass filter output to be output within a threshold. And a protection circuit(270) judges whether to block an operation of the first driver.

Description

Class D power amp having protection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a class D power amplifier having a protection circuit that senses a short circuit and shuts down the operation.

Class D power amplifiers among audio amplifiers can be classified into an analog-digital method for generating a digital output signal from an analog input signal and a digital-digital method for generating a digital output signal from a digital input signal. Because power amplifiers are typically systems that drive large currents, they can be destroyed by excessive current flow in the event of a short circuit or overload caused by the external environment.

1 is a diagram illustrating a general class D power amplifier. Referring to this, the class D amplifier 100 includes a first amplifier 102, a triangle wave generator 104, a PWM generator 106, a PMOS transistor 108, an NMOS transistor 110, and inductors 112. , 116, a capacitor 114, a feedback unit 120, and a speaker 118. The first amplifier 102 generates an amplifier output AMP_OUT by amplifying the audio signal inputted from the feedback unit 120 output. The PWM generator 106 inputs a triangular wave having a fixed frequency generated by the triangular wave generator 104 and the amplifier output AMP_OUT to generate a modulated PWM signal PWM_OUT. The PWM signal PWM_OUT is driven by the PMOS transistor 108 and the NMOS transistor 110 to demodulate the audio signal through an LC filter composed of the inductors 112 and 116 and the capacitor 114 to output the speaker output SP_OUT. Is generated. The speaker output SP_OUT is fed back to the first amplifier 102 through the feedback unit 120 to prevent degradation of analog amplifier performance.

However, in the class D power amplifier, excessive current flows to the PMOS transistor 108 and the NMOS transistor 110 when the speaker output signal SP_OUT is shorted with the power voltage PVCC or the ground voltage PVSS. The problem is that the transistors 108 and 110 are destroyed.

Thus, there is a great need for a protection circuit to protect the MOS transistors 108 and 110 of a class D power amplifier.

It is an object of the present invention to provide a class D power amplifier comprising a protection circuit.

1 is a view showing a general class D power amplifier,

2 is a diagram illustrating a class D power amplifier according to an embodiment of the present invention.

3 is a diagram illustrating a signal flow of the class D power amplifier of FIG. 2.

In order to achieve the above object, the present invention provides a class D amplifier for generating a speaker output signal from a pulse width modulated signal (PWM signal), the first and second drivers for inputting a PWM signal, and the first driver output; An internal circuit of a class D amplifier includes an external circuit that generates a speaker output signal including an LC filter including an MOS transistor and an inductor and a capacitor to be driven, an inverter driven to a second driver output, and an operating range of the speaker output signal. An output signal mapper for mapping to a range, a low pass filter for demodulating the output of the inverter into an analog signal, and an output signal mapper output and a low pass filter output, respectively, to be output within a threshold of an area separated by a predetermined operating range The operating range is compared by comparing the outputs of the first and second limit region generators and the first and second limit range generators. And a protection circuit that determines whether to shut off the operation of the first driver depending on whether they deviate from each other. The limit region generators are preferably set such that the widths of the ranges divided by the first limit range generator are smaller than the widths of the ranges divided by the second limit range operation part.

Therefore, according to the class D power amplifier of the present invention, a protection circuit is provided therein to cut off the operation of the driver depending on whether the speaker output signal is short-circuited to thereby protect the MOS transistors driven by the driver.

The invention is now described with reference to FIGS. 2 and 3.

2 is a diagram illustrating a class D power amplifier according to an embodiment of the present invention. Referring to this, the class D power amplifier 200 includes drivers 202 and 204, an external circuit 210, an inverter 220, a low pass filter (LPF, 230), limit range generators 240 and 260, and an output. A signal mapper 150 and a protection circuit 270. The drivers 202 and 204 are some blocks included in the pulse width modulation (PWM) generator 106 of FIG. 1 to input a PWM signal to generate a PWM output signal PWM_OUT. . The external circuit 210 inputs the PWM output signal PWM_OUT, and as shown in FIG. 1, the PMOS transistor 108, the NMOS transistor 110, the inductor 112, and the LC filter 114 and 116. And a speaker 118.

The inverter 220 inputs the PWM output signal PWM_OUT and transmits the output to the low pass filter 230. The low pass filter 230 converts the inverter 220 output into an analog signal. The output signal mapper 250 maps the operating range of the external circuit 210, that is, the speaker output signal SP_OUT into the dynamic operating range of the chip internal circuit. Each of the limit range generators 240 and 260 sets an output signal mapper 250 output and a low pass filter 230 output within a threshold of an area divided into a predetermined operating range. The protection circuit 270 compares the outputs of the first limit range generator 240 and the second limit range generator 260 and drives the external circuit unit 210 according to whether the operating ranges are different from each other. It is determined whether the operation of the 202 is blocked.

Operation of the class D power amplifier 200 is described with reference to FIG. Referring to FIG. 3, the waveform of the speaker output signal SP_OUT, which is an analog signal, may be converted into a first voltage PVCCO through a mapping operation of the output signal mapper 250 (FIG. 2) and an operation of the first limit range generator 240. It is generated within a range divided into regions A, B, and C between the level and the second voltage PVSSO level. Zone B is a range between the high threshold voltage (VTHO) and the low threshold voltage (VTLO) based on the reference voltage (Vbias), and zone A has a range between the high threshold voltage (VTHO) and the first voltage (PVCCO). The area C is in the range between the low limit voltage VTLO and the second power supply PVSSO.

Meanwhile, the output of the inverter 220 (FIG. 2), which is a digital signal, is generated within the range divided by the regions ai, bi, and ci between the power supply voltage VDD and the ground voltage GND through the low pass filter 230. The area bi is in the range between the high limit voltage (VTHI) and the low limit voltage (VTLI) with respect to ½ supply voltage (VDD / 2), and the area ai is between the high limit voltage (VTHI) and the supply voltage (VDD). Area ci is the range between the low threshold voltage VTLI and the ground voltage GND.

Here, the regions A and C ranges are set to be smaller than the regions ai and ci ranges. This is because the phase delay and gain mismatch between the output of the inverter 220 (FIG. 2), which is an internal circuit, and the speaker output SP_OUT of the external circuit 210, FIG. In addition, the range of the areas A and C is narrowed because if the speaker output signal SP_OUT is shorted, the range is near the first voltage PVCCO and the second voltage PVSSO.

In the signal flow of FIG. 3, when the mapped output signal is in the region A, when the signal demodulated through the low pass filter 230 (FIG. 2) is in the region bi or ci, the speaker output signal is divided into the first power source PVCCO and the first power source. 2 It is determined that the power supply is shorted to PVSSO. If you express it as a relational expression,

Short circuit detection = {area A <and> (area bi <or> area ci)} <or> {area C <and> (area bi <or> area ai)}

It is expressed as

Therefore, when it is determined that the speaker output signal SP_OUT is shorted, the protection circuit 270 (FIG. 2) turns off the operation of the driver 202 so that the PMOS transistor 108 and the NMOS of the external circuit 210 are turned off. The transistor 110 is not driven. Thus, the transistors of the external circuit unit 210 are protected.

In the above, the present invention has been described with reference to the embodiments, which are merely exemplary and do not limit or limit the technical spirit and scope of the present invention. Therefore, various changes and modifications are possible without departing from the spirit and scope of the present invention.

According to the class D power amplifier of the present invention described above, a protection circuit is provided therein to cut off the operation of the driver depending on whether the speaker output signal is short-circuited to thereby protect the MOS transistors driven by the driver.

Claims (2)

In a class D amplifier that generates a speaker output signal from a pulse width modulated signal (PWM signal), First and second drivers for inputting the PWM signal; An external circuit unit configured to generate a speaker output signal including an LC filter including MOS transistors and an inductor and a capacitor driven at the first driver output; An inverter driven to the second driver output; An output signal mapper for mapping an operating range of the speaker output signal to an internal operating range of the class D amplifier; A low pass filter demodulating the output of the inverter into an analog signal; First and second limit region generators configured to output each of the output signal mapper output and the low pass filter output within a threshold of an area separated by a predetermined operating range; And And a protection circuit comparing the outputs of the first and second limit range generators and determining whether the first driver is blocked according to whether the operating ranges are out of each other. The method of claim 1, wherein the limit region generating unit The ranges divided by the first limit range generator are set to be narrower than the ranges divided by the second limit range operation unit.