JP2002111446A - Mute circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mute circuit capable of eliminating the need for an external DC power supply by generating a bias voltage inside of a semiconductor integrated circuit, thereby decreasing an external terminal. SOLUTION: The mute circuit supplies a predetermined negative voltage to the base of a muting MOS transistor M5 to turn off in response to switching of a switch 38 and outputs an input signal without damping by turning off the MOS transistor M5. Since the mute circuit has an oscillation circuit 44 for generating an oscillation signal and a clamping and smoothing circuit (C11, M2, R1 and C12) for obtaining the predetermined negative voltage by clamping and filtering the oscillation signal, the bias voltage of the predetermined negative voltage can be generated inside of the semiconductor integrated circuit, thereby eliminating the need of the external DC power supply and decreasing the external terminal of the semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a mute circuit, and more particularly, to a semiconductor integrated mute circuit for attenuating an audio signal.

[0002]

2. Description of the Related Art Conventionally, CDs (Compact Discs)
The device for reproducing the audio data is provided with a mute circuit for attenuating the audio signal reproduced from the CD and stopping the signal output.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor integrated mute circuit. In FIG. 1, a DC power supply 12 supplies, for example, +5 V to an external terminal 11 of a semiconductor integrated circuit 10.
Is supplied. The external terminal 13 is supplied with a bias voltage Vb of approximately −2 V from the DC power supply 14. The external terminal 15 is grounded, and the external terminal 17 is grounded via a switch 18. The external terminal 19 is connected to an external output terminal 22. Here, the output terminal 22 is connected to the input terminal 20 via the resistor R10, and an audio signal is supplied to the input terminal 20 and output from the output terminal 22.

In the semiconductor integrated circuit 10, an N-channel MOS transistor M1 as a protection element has a drain connected to a power supply Vdd through an external terminal 11, and a source, a gate and a back gate grounded through an external terminal 15. ing. The N-channel MOS transistor M3 as a protection element has a drain connected to the external terminal 17, and a source, a gate, and a back gate grounded via the external terminal 15.

The external terminal 11 is connected to one end of a resistor R3 and the source and back gate of a P-channel MOS transistor M4. The other end of the resistor R3 is connected to the gate of the MOS transistor M4 and to the external terminal 17 via the resistor R4. The drain of the MOS transistor M4 is connected to a connection point between the resistors R1 and R2.

Further, one end of a resistor R1 is connected to the external terminal 11, the other end of the resistor R1 is connected to one end of a resistor R2, and the other end of the resistor R2 is connected to an N-channel MOS transistor M.
5 gates. MOS transistor M5
Is connected to the external terminal 19, the source is grounded via the external terminal 15, and a resistor R5 is connected between the gate and the back gate.

Here, when the switch 18 is open (off), the MOS transistor M4 is off, so the bias voltage Vb is applied to the gate of the MOS transistor M5, and the MOS transistor M5 turns off. Therefore, the mute is not performed, and the audio signal supplied to the input terminal 20 is output from the output terminal 22 without being attenuated.

The reason why the bias voltage Vb is set to approximately -2 V is that the audio signal supplied to the input terminal 20 has a positive or negative value with respect to the ground level, and the MOS transistor M5 is turned on when the audio signal is negative. This is to prevent the audio signal from being clamped and prevent the audio signal from being distorted.

Next, when the switch 18 is closed (turned on), the gate voltage of the MOS transistor M4 rises and the MOS transistor M4 is turned on. Therefore, the power supply Vdd is applied to the gate of the MOS transistor M5, and the MOS transistor M5 is turned on. Since the resistance between the drain and the source when the MOS transistor M5 is on is several ohms and the resistance of the resistor R10 is several kilohms, the signal supplied to the input terminal 20 is attenuated and the output terminal 22 is substantially grounded. Level.

[0010]

Since the conventional mute circuit supplies the semiconductor integrated circuit 10 with the bias voltage Vb from an external DC power supply 14, an external DC power supply 14 is required. There is a problem that the number of external terminals of the semiconductor integrated circuit 10 increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a mute circuit capable of reducing the number of external terminals by eliminating the need for an external DC power supply by generating a bias voltage in a semiconductor integrated circuit. The purpose is to provide.

[0012]

According to a first aspect of the present invention, there is provided an apparatus for mute M in response to switching of a switch (38).
A power supply voltage or a predetermined negative voltage is supplied to the base of the OS transistor (M5) to turn on and off, and the mute MO
When the S transistor (M5) is turned on, the input signal having a positive or negative value with respect to the ground level is attenuated to stop the output, and when the mute MOS transistor (M5) is turned off, the input signal is output without attenuating. An oscillation circuit for generating an oscillation signal in the mute circuit (44)
And a clamp smoothing circuit (C11, M2, R1, C1) for clamping and smoothing the oscillation signal to obtain the predetermined negative voltage.
With the provision of 2), a predetermined negative bias voltage can be generated inside the semiconductor integrated circuit, so that an external DC power supply becomes unnecessary and the number of external terminals of the semiconductor integrated circuit can be reduced.

According to a second aspect of the present invention, in the mute circuit according to the first aspect, the oscillation circuit (44) is a ring oscillator constituted by a plurality of CMOS inverters (M11 to M16).

According to a third aspect of the present invention, in the mute circuit according to the first aspect, the clamp smoothing circuit (C1
1, M2, R1, and C12) perform clamping using a P-channel MOS transistor (M2) whose gate, source, and back gate are connected to a signal line and whose drain is grounded.

The reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of a mute circuit according to the present invention. 4, the same parts as those in FIG. 4 are denoted by the same reference numerals. In FIG. 1, a power supply Vdd of, for example, +5 V is supplied from a DC power supply 32 to an external terminal 31 of the semiconductor integrated circuit 30. The external terminal 35 is grounded,
The external terminal 37 is grounded via a switch 38.
The external terminal 39 is connected to an external output terminal 42. Here, the output terminal 42 is connected to the input terminal 40 via the resistor R10, and the audio signal is supplied to the input terminal 40 and output from the output terminal 22.

An oscillation circuit 44 is provided inside the semiconductor integrated circuit 30. To describe the oscillation circuit 44, the gate and the drain of the P-channel MOS transistor M11 and the N-channel MOS transistor M12 are commonly connected, the source and the back gate of the MOS transistor M11 are connected to the power supply Vdd, and the source of the MOS transistor M12 is connected. And the back gate is grounded to form a first inverter of CMOS. Similarly,
P-channel MOS transistor M13 and N-channel MO
The S transistor M14 has a gate and a drain commonly connected, a source and a back gate of the MOS transistor M13 connected to a power supply Vdd, a source and a back gate of the MOS transistor M14 grounded, and a CMO.
The second inverter of S is constituted by a P-channel MOS
Transistor M15 and N-channel MOS transistor M
Reference numeral 16 denotes a gate and a drain which are commonly connected.
The source and the back gate of the S transistor M15 are connected to the power supply Vdd, and the source and the back gate of the MOS transistor M16 are grounded to form a third CMOS inverter.

The drains of the MOS transistors M11 and M12 are connected to the gates of the MOS transistors M13 and M14, the drains of the MOS transistors M13 and M14 are connected to the gates of the MOS transistors M15 and M16, and the drains of the MOS transistors M15 and M16. Is connected to the gates of the MOS transistors M11 and M12 via resistors 20 and 21 connected in series to form a ring oscillator. Also, the MOS transistor M1
The capacitor C10 is connected between the drains of the resistors M1 and M12 and the connection point of the resistors R20 and R21, and the oscillation frequency is determined by the resistor R20 and the capacitor C10. MOS transistor M1 which is an output terminal of the oscillation circuit 44
5, the drain of M16 (point A) is connected to one end (point B) of the resistor R1 via the capacitor C11.

An N-channel MOS transistor M1 as a protection element has a drain connected to a power supply Vd through an external terminal 31.
d, and the source, the gate, and the back gate are grounded via the external terminal 35. The drain of the N-channel MOS transistor M3 as a protection element is connected to the external terminal 37, and the source, gate and back gate are grounded via the external terminal 35.

Here, an N-channel MO as a protection element is used.
In the p-type wells forming the S-transistors M1 and M3, an n-type region is used as a collector, a p-type well is used as a base, and a diffusion resistance of the p-type well is used as a base resistance to form a back gate p-type
Parasitic np connected to the n-type region and having the n-type region as the emitter
When an n-transistor is formed and positive static electricity is applied to the external terminals 31 and 37, the parasitic npn transistor breaks down and the parasitic npn from the external terminals 31 and 37.
A surge current flows to the external terminal 35 at the ground level through the collector and the emitter of the transistor.
The circuit formed at 0 is protected from static electricity.

The external terminal 31 is connected to one end of a resistor R3 and the source and back gate of a P-channel MOS transistor M4. The other end of the resistor R3 is connected to the gate of the MOS transistor M4 and to the external terminal 37 via the resistor R4. The drain of the MOS transistor M4 is connected to a connection point between the resistors R1 and R2. Also, at one end of the resistor R1, that is, at the point B,
The source, gate and back gate of the P-channel MOS transistor M2 are connected, and the MOS transistor M2
Are grounded via an external terminal 35.

Here, FIG. 2 shows a sectional structural view of the MOS transistor M2. 2, a p-type region 57 serving as a drain and a p-type region 58 serving as a source of an MOS transistor M2 are provided in an n-type well 56 formed on a semiconductor substrate.
And an n-type region 59 serving as a back gate electrode. A gate oxide film 60 is formed on the n-type well 56 between the p-type regions 57 and 58.
A gate electrode 61 made of polysilicon is provided on the upper part of 0. The drain of the MOS transistor M2 is grounded via the external terminal 35, and the gate, source and back gate are connected to one end of the resistor R1 via the terminal 62.
It operates as a pn junction diode formed on the junction surface between the pn junction and the n-type well 56.

The other end (point C) of the resistor R1 is connected to the resistor R
2 and one end of the capacitor C12, and the other end of the resistor R2 is connected to the gate of the mute N-channel MOS transistor M5. The other end of the capacitor C12 is grounded via an external terminal 35. The drain of the MOS transistor M5 is connected to the external terminal 39, the source is grounded via the external terminal 35, and a resistor R5 is connected between the gate and the back gate.

Here, as shown in FIG. 3A, the oscillating circuit 44 outputs an oscillating signal having a high level of the voltage Vdd and a low level of the ground level GND from the point A. Point B is MO
Since the diode is clamped by the diode formed by the S transistor M2, as shown in FIG. 3B, the high level is the forward voltage drop Vf of the diode and the low level is the voltage − (Vdd).
−Vf). The oscillation signal shown in FIG. 3B is smoothed by a low-pass filter formed by the resistors R1 and R2 and the capacitor C12. At a point C, as shown in FIG. 3C, the DC voltage (Vf-Vdd / 2) Becomes For example, V
Assuming dd = 5V and Vf = 0.6V, the DC voltage is -1.9V. That is, at the point C, a bias voltage Vb of a predetermined negative voltage (about -2 V) is obtained.

Here, when the switch 38 is open (off), the MOS transistor M4 is off, so the bias voltage Vb is applied to the gate of the MOS transistor M5, and the MOS transistor M5 turns off. Therefore, the mute is not performed, and the audio signal supplied to the input terminal 40 is output from the output terminal 42 without being attenuated.

The bias voltage is set to approximately -2 V, for example, because the audio signal supplied to the input terminal 40 has a positive or negative value with respect to the ground level, and the MOS transistor M5 is turned on when the audio signal is negative. This is to prevent the audio signal from being clamped and prevent the audio signal from being distorted.

Next, when the switch 38 is closed (turned on), the gate voltage of the MOS transistor M4 rises and the MOS transistor M4 is turned on. Therefore, the power supply Vdd is applied to the gate of the MOS transistor M5, and the MOS transistor M5 is turned on. Since the resistance between the drain and the source when the MOS transistor M5 is on is several ohms and the resistance value of the resistor R10 is several kilohms, the audio signal supplied to the input terminal 40 is attenuated and the output terminal 42 is substantially turned off. It becomes the ground level.

[0028]

As described above, the first aspect of the present invention provides
By having an oscillation circuit for generating an oscillation signal and a clamp smoothing circuit for clamping and smoothing the oscillation signal to obtain the predetermined negative voltage, a bias voltage of a predetermined negative voltage can be generated inside the semiconductor integrated circuit. In addition, an external DC power supply is not required, and external terminals of the semiconductor integrated circuit can be reduced.

According to the second aspect of the present invention, the oscillation circuit is a ring oscillator constituted by a plurality of CMOS inverters.

According to the third aspect of the present invention, the clamp smoothing circuit performs clamping using a P-channel MOS transistor having a gate, a source, and a back gate connected to a signal line and a drain grounded.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of a mute circuit of the present invention.

FIG. 2 is a sectional structural view of a MOS transistor M2.

FIG. 3 is a signal waveform diagram of each section of the circuit of FIG. 1;

FIG. 4 is a circuit diagram of an example of a conventional semiconductor integrated mute circuit.

[Explanation of symbols]

 Reference Signs List 30 semiconductor integrated circuit 31, 35, 37, 39 external terminal 32 DC power supply 40 input terminal 42 output terminal 44 oscillation circuit 56 n-type well 57, 58 p-type region 59 n-type region 60 gate oxide film 61 gate electrode C10 to C12 Capacitors M11 to M16 MOS transistors R1 to R21 Resistance

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J092 AA02 CA91 CA92 FA00 FR02 HA10 HA17 HA19 HA25 HA29 HA38 KA04 KA11 KA12 KA21 KA32 KA42 KA47 MA21 QA02 TA06 5J098 AA01 AB04 AB34 AC14 AD25 EA09

Claims (3)

[Claims] 1. A power supply voltage or a predetermined negative voltage is supplied to a base of a mute MOS transistor in response to switching of a switch to turn on / off the power supply, and a positive / negative value is set based on a ground level by turning on the mute MOS transistor. A muting circuit that attenuates the input signal and stops the output, and outputs the input signal without attenuating by turning off the mute MOS transistor; an oscillation circuit that generates an oscillation signal; and a clamp and smoothes the oscillation signal. And a clamp smoothing circuit for obtaining the predetermined negative voltage. 2. The mute circuit according to claim 1, wherein said oscillation circuit is a ring oscillator constituted by a plurality of CMOS inverters. 3. The mute circuit according to claim 1, wherein the clamp smoothing circuit performs clamping using a P-channel MOS transistor having a gate, a source, and a back gate connected to a signal line and a drain grounded. Mute circuit.