JPH0865129A - Input circuit - Google Patents

Abstract

PURPOSE: To obtain the input circuit in which the effect by noise of a power supply is reduced. CONSTITUTION: A PMOS transistor(TR) 1 and an NMOS TR 2 are connected in series between a high voltage power supply VCC and a low voltage power supply GND. A common input signal IN is given to gates of the TRs 1, 2, a signal S1 being an inversion of a voltage level of the input signal IN is outputted from an output terminal 3 of the TRs 1, 2. The TR 1 is connected to the high voltage power supply VCC via a diode 4 used to prevent the supply of the current to the high voltage power supply VCC. A capacitor 5 is connected between the diode 4 and the low voltage power supply GND to make the voltage of the TR 1 at the high voltage power supply VCC side stable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit provided in a semiconductor device. Acceleration of operation of semiconductor devices in recent years,
With the decrease in voltage, it is required to improve the characteristics of an input circuit for inputting an input signal. Therefore, it is necessary to prevent malfunction of the input circuit due to power supply noise.

[0002]

2. Description of the Related Art FIG. 7 shows an input circuit in a conventional semiconductor device. The input circuit 20 includes a power supply VCC and a ground GN.
It is a CMOS inverter composed of a PMOS transistor 21 and an NMOS transistor 22 connected in series between D. An output terminal 23 is provided between the transistors 21 and 22. A common input signal IN is input to each gate of the transistors 21 and 22, and the input circuit 20 outputs a signal S10 obtained by inverting the potential of the input signal IN from the output terminal 23.
Is output.

The input circuit 20 recognizes the level of the input signal IN as L and outputs the H-level signal to the output terminal 23 as the first standard voltage and the level of the input signal IN as H and outputs the output terminal 23. The second standard voltage for outputting the L level signal to 23 is determined. For example, the power supply VCC is 3
The first standard voltage is 0.8 volt, and the second standard voltage is 2.4 volt. When the potential of the input signal IN is 0.8 V or less, the PMOS transistor 21 is turned on and the H-level signal S1 is output from the output terminal 23.
0 is output. When the potential of the input signal IN is 2.4 V or higher, the NMOS transistor 22 is turned on and the output terminal 23 outputs the L-level signal S10. When the potential of the input signal IN is 0.8 V to 2.4 V, both the PMOS transistor 21 and the NMOS transistor 22 are turned on, and the output of the output terminal 23 becomes unstable.

[0004]

However, when the semiconductor device is activated, noise is generated in the power supply VCC due to the operation of many other circuits connected to the power supply VCC, and the potential of the power supply VCC is lowered. There are cases. At this time, if the input signal IN having a potential near the standard voltage is input to the input circuit 20, the input circuit 20 may malfunction.

In particular, the potential of the input signal IN is mainly PMOS.
When the potential of the power supply Vcc drops near the first standard voltage for turning on the transistor 21, the first
Will increase with respect to the potential of the power supply VCC, and the ON state of the PMOS transistor 21 will be slightly shallow. As a result, the signal S10 output from the output terminal 23
The potential of is deviated from the expected value, which may cause a circuit connected to the next stage of the input circuit 20 to malfunction.

The present invention has been made to solve the above problems, and an object thereof is to provide an input circuit capable of reducing the influence of noise of a power supply.

[0007]

FIG. 1 is a diagram for explaining the principle of the invention of claim 1. PMOS transistor 1 and NMO
The S-transistor 2 has a high potential power supply VCC and a low potential power supply GND.
And are connected in series. A common input signal IN is input to each gate of the PMOS transistor 1 and the NMOS transistor 2,
Input signal IN from the output terminal 3 between the MOS transistors 2
The signal S1 which is the inverted potential of is output. The PMOS transistor 1 is connected to the high potential power supply VCC through a diode 4 for preventing the inflow of current into the high potential power supply VCC. Capacitor 5 is diode 4 and low potential power supply GND
Is connected between and to stabilize the potential on the high potential side of the PMOS transistor 1.

FIG. 2 is an explanatory view of the principle of the invention of claim 2. In addition to the configuration of the first aspect of the invention, a second PMOS transistor 6 is connected in parallel with the diode 4 between the high potential power supply VCC and the PMOS transistor 1. Second
The input signal IN is input to the gate of the PMOS transistor 6.

According to the third aspect of the invention, the second PMOS transistor has a small driving capability.

[0010]

According to the first aspect of the present invention, the capacitor 5 is charged by the diode 4 to a potential lower than the potential of the high potential power supply VCC by the voltage for turning on the diode 4. When noise occurs in the high-potential power supply VCC and the potential of the power supply VCC drops, the diode 4 also tries to lower the potential on the high-potential side of the PMOS transistor 1.
The fluctuation of the potential on the high potential side of the S transistor 1 is reduced by the charging voltage of the capacitor 5. Therefore, the potential of the signal S1 at the output terminal 3 is almost the expected value.

According to the second aspect of the present invention, when the input signal IN is at L level, the capacitor 5 is charged to the potential of the high potential power supply VCC by the second PMOS transistor 6,
The potential of the signal S1 at the output terminal 3 becomes the potential of the high potential power supply VCC.

According to the invention of claim 3, the second PMOS
High potential power supply Vcc due to small transistor drive capability
Even if the electric potential of the output terminal decreases, the influence on the signal of the output terminal is small, and the electric potential of the signal of the output terminal becomes almost the electric potential of the high-potential power supply.

[0013]

【Example】

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. The same components as those in FIG. 1 will be described with the same reference numerals.

FIG. 3 shows an input circuit 10 of this embodiment provided on a semiconductor device. The input circuit 10 is supplied with a power supply VCC as a high potential power supply and a ground GND as a low potential power supply. The input circuit 10 includes a PMOS transistor 1, an NMOS transistor 2, a diode 11 including an NMOS transistor, and a capacitor 12 including an NMOS transistor.

Diode 11, PMOS transistor 1
And the NMOS transistor 2 has a power supply VCC and a ground G
It is connected in series between ND. The PMOS transistor 1 and the NMOS transistor 2 form a CMOS inverter, and the output terminal 3 is connected to the node between the transistors 1 and 2. PMOS transistor 1 and NM
A common input signal IN is applied to each gate of the OS transistor 2.
Has been entered. PMOS transistor 1 and NMO
The S-transistor 2 is turned on / off based on the level of the input signal IN, and outputs the signal S1 obtained by inverting the potential of the input signal IN from the output terminal 3.

The diode 11 is constructed by connecting the drain and gate of the NMOS transistor to the power source Vcc, and the source of the NMOS transistor is connected to the source of the PMOS transistor 1. Diode 11
Allows a current flowing from the power supply Vcc to the node N1 between the diode 11 and the PMOS transistor 1 and prevents a current from flowing from the node N1 to the power supply Vcc.

The capacitor 12 has the gate of the NMOS transistor as one electrode and is connected to the node N1.
It is configured by connecting the source and drain of the S transistor as the other electrode to the ground GND. The capacitor 12 is charged to a voltage lower than the potential of the power supply VCC by the threshold voltage VthN of the NMOS transistor by the current flowing from the power supply VCC to the diode 11. When the potential of the power supply VCC drops from the set level,
The capacitor 12 stabilizes the potential of the node N1, that is, the high potential side (source side) of the PMOS transistor 1, by the charging voltage.

Next, the input circuit 10 configured as described above.
The operation of will be described with reference to FIG. When the power supply Vcc is supplied to the input circuit 10 and other circuits of the semiconductor device, and the potential of the power supply Vcc is stable at the set level, the capacitor 12 is charged by the diode 11 and the potential of the node N1 becomes the power supply Vcc. Threshold voltage Vth
The value is lower by N.

When noise is generated in the power supply VCC by the operation of many circuits other than the input circuit 10, the potential of the power supply VCC is temporarily lowered. At this time, it is assumed that the potential of the input signal IN is at the voltage level on the ground GND side and has a value that turns on the PMOS transistor 1 and shallowly turns on the NMOS transistor 2.

Then, the potential of the node N1 is the diode 1
Based on the charging voltage due to the coupling capacitance between the gate and drain of No. 1 and the current flowing through the transistors 1 and 2, it tends to decrease as indicated by the broken line. However, the potential of the node N1 is hardly reduced by the charging voltage of the capacitor 12 as shown by the alternate long and short dash line, and is almost equal to (VCC-VthN
) Is kept stable. As a result, the output terminal 3 outputs the signal S1 having a value equal to the potential of the node N1.

As described above, in this embodiment, it is possible to reduce the influence of the noise of the power source Vcc on the potential of the node N1 and suppress the fluctuation of the potential of the node N1, and to output the signal S1 having a stable voltage level. it can.

Further, in this embodiment, the capacitor 1
By increasing the capacitance of 2, the potential of the node N1 can be held more stably without changing the potential of the node N1.

[Second Embodiment] Next, an input circuit of the second embodiment will be described with reference to FIGS. The same components as those in FIG. 3 are designated by the same reference numerals and the description thereof is partially omitted.

FIG. 5 shows an input circuit 15 according to the present embodiment. In addition to the configuration of the input circuit 10, the input circuit 15 is connected between the power supply VCC and the PMOS transistor 1 in parallel with the diode 11. Two PMOS transistors 6 are provided. The input signal IN is input to the gate of the PMOS transistor 6. PMOS transistor 6
Has a small driving capacity, and a small amount of current can flow when turned on. The PMOS transistor 6 is turned on when the input signal IN is at L level, and charges the capacitor 12 to the potential of the power source Vcc.

Next, the input circuit 15 configured as described above.
The operation of will be described with reference to FIG. When the input signal IN is at H level, the capacitor 12 receives the input signal I in the previous cycle.
When N is at the L level, the PMOS transistor 6 has charged up to the potential of the power supply VCC, and the potential of the node N1 is the potential of the power supply VCC.

When the input signal IN changes from the H level to the L level, the NMOS transistor 2 turns off and the PMOS
The transistors 1 and 6 are turned on. Electric charges are supplied to the output terminal 3 via the diode 11 and the PMOS transistor 6, and the potential of the signal S1 rises. Since the driving capability of the PMOS transistor 6 is small, the current to the output terminal 3 is mainly supplied via the diode 11. At this time, the potential of the node N1 drops.

When the potential of the node N1 and the potential of the signal S1 reach (VCC-VthN), no current flows in the diode 11. After this, the potential of the node N1 and the signal S
The potential of 1 is gradually raised to the potential of the power supply VCC by the current flowing through the PMOS transistor 6.

After that, even if noise is generated in the power supply VCC and the potential of the power supply VCC is temporarily lowered, the potential of the node N1 is maintained by the action of preventing the reverse current of the diode 11 and the PMOS transistor 6 having a small driving capability. Almost no change from the set level of the power supply VCC. The potential of the node N1 and the potential of the signal S1 only slightly decrease based on the charging voltage due to the coupling capacitance between the gate and drain of the diode 11 and the current flowing through the PMOS transistor 6.

As described above, in this embodiment, the PMO
The S transistor 6 allows the output terminal 3 to output a signal S1 having a potential equal to the set level of the power supply VCC. Therefore, malfunction of the circuit connected to the next stage of the input circuit 15 can be prevented. For example, it is possible to prevent a through current from flowing through the inverter 16 connected to the input circuit 15.

Further, in this embodiment, since the PMOS transistor 6 has a small driving capability, even if the potential of the power source Vcc drops due to noise, the output terminal 3
The influence on the signal S1 can be reduced.

Further, also in this embodiment, by increasing the capacity of the capacitor 12, the potential of the node N1 can be held more stably at the set level of the power supply VCC.
It should be noted that the capacitor 12 in each of the above embodiments is an NMOS.
A PMOS transistor may be used instead of the transistor. Even when a PMOS transistor is used, its gate may be one electrode and the source and drain may be the other electrode.

The technical ideas other than the claims that can be understood from the above-described embodiments will be described below along with their effects. (A) The input circuit according to claim 1, wherein the capacitor is a MOS transistor having a gate, a source and a drain, the gate of which is one electrode and the source and the drain of which are the other electrodes.

According to this structure, the capacitor can be easily formed by using the MOS transistor formed on the semiconductor substrate. Diode: A diode in this specification is 2
This means a device that has two electrodes and that exhibits a current-voltage characteristic that does not follow Ohm's law. Not only the diode of the PN junction but also the device that connects the collector and base of the NPN transistor and the drain and gate of the NMOS transistor are An element connected to the potential side and an element in which the drain and gate of the PMOS transistor are connected to the low potential side are included.

[0034]

As described above in detail, according to the invention of claim 1, the influence of noise of the power source can be reduced.

According to the invention of claim 2, in addition to the effect of claim 1, a signal having the potential of the high potential power source can be output.
According to the invention of claim 3, even if the potential of the high-potential power supply is lowered, the influence on the signal at the output terminal can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first invention.

FIG. 2 is an explanatory view of the principle of the second invention.

FIG. 3 is a circuit diagram showing an input circuit of the first embodiment.

FIG. 4 is a waveform diagram showing an operation of the input circuit of FIG.

FIG. 5 is a circuit diagram showing an input circuit of a second embodiment.

FIG. 6 is a waveform diagram showing the operation of the input circuit of FIG.

FIG. 7 is a circuit diagram showing a conventional input circuit.

[Explanation of symbols]

 1 PMOS transistor 2 NMOS transistor 3 Output terminal 4 Diode 5 Capacitor 6 Second PMOS transistor IN Input signal GND Ground as low potential power supply S1 Inversion signal VCC Power supply as high potential power supply

Claims (3)

[Claims] 1. A PMO between a high potential power supply and a low potential power supply.
An S transistor and an NMOS transistor are connected in series, a common input signal is input to each gate of the PMOS transistor and the NMOS transistor, and a signal obtained by inverting the potential of the input signal is output from the output terminal between the PMOS transistor and the NMOS transistor. In the input circuit, a diode connected between the high-potential power supply and the PMOS transistor and for preventing current from flowing into the high-potential power supply, and between the diode and the low-potential power supply. An input circuit that is connected and that includes a capacitor for stabilizing the high-side potential of the PMOS transistor. 2. A second PMOS transistor is connected in parallel with the diode between the high potential power source and the PMOS transistor, and the input signal is input to the gate of the second PMOS transistor. Input circuit described. 3. The input circuit according to claim 2, wherein the second PMOS transistor has a small driving capability.