KR20040047265A - Method of forming asymetric MOS transistor for semiconductor device - Google Patents
Method of forming asymetric MOS transistor for semiconductor device Download PDFInfo
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- KR20040047265A KR20040047265A KR1020020075413A KR20020075413A KR20040047265A KR 20040047265 A KR20040047265 A KR 20040047265A KR 1020020075413 A KR1020020075413 A KR 1020020075413A KR 20020075413 A KR20020075413 A KR 20020075413A KR 20040047265 A KR20040047265 A KR 20040047265A
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- active region
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 11
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체 장치 형성 방법에 관한 것으로서, 보다 상세하게는 비대칭 모스형 트랜지스터 형성 방법에 관한 것이다.The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming an asymmetric MOS transistor.
반도체 장치의 소자 고집적화에 따라 모스형 트랜지스터 내의 게이트 전극의 폭도 감소하여 채널의 길이가 감소하게 된다. 이에 따라 채널 펀치 스루(punch through), DIBL(drain induced barrier lowering) 등의 단채널 현상이 문제가되며, 스레숄드 전압(threshold voltage) 롤-오프(roll off) 현상 등도 심각하게 나타난다.As device integration in semiconductor devices increases, the width of gate electrodes in MOS transistors also decreases, resulting in a decrease in channel length. Accordingly, short channel phenomena such as channel punch through and drain induced barrier lowering (DIBL) become a problem, and a threshold voltage roll-off phenomenon also seriously appears.
단채널 효과를 개선하기 위해서는 채널의 불순물 농도를 증가시키는 방법이 사용될 수 있다. 그러나, 채널의 불순물 농도를 높이는 것은 디램 셀의 경우 셀 캐퍼시터 노드(cell capacitor node)와 채널 불순물 농도 차를 급격하게 하여 셀 캐퍼시터의 데이터 보유 시간을 줄이고 리프레시 주기를 감소시킨다.In order to improve the short channel effect, a method of increasing the impurity concentration of the channel may be used. However, increasing the impurity concentration of the channel sharpens the difference between the channel capacitor concentration and the cell capacitor node in the DRAM cell, thereby reducing the data retention time of the cell capacitor and reducing the refresh period.
한편, 단채널 효과는 주로 소오스/드레인 전극에 의해 여기되는 채널 전하의 변화로 인한 것이다. 따라서, 게이트를 중심으로 캐퍼시터가 연결되는 데이터 노드의 반대인 드레인 영역의 게이트 인근의 접합 깊이를 얕게, 가령 100nm 이하로 하면 드레인 전극에 의해 여기되는 채널 전하를 줄여 트랜지스터 내의 단채널 효과를 줄일 수 있다. 그러나, 통상적인 공정에 의해 소오스/드레인을 동시에 형성하면서 소오스/드레인 접합을 얕게 할 경우, 소오스/드레인 영역에서 콘택 홀 형성시 조금만 과식각이 일어나면 누설 전류가 많아지고, 콘택과 기판이나 웰이 직접 단락되는 현상도 발생할 수 있다.On the other hand, the short channel effect is mainly due to the change in the channel charge excited by the source / drain electrodes. Therefore, when the junction depth near the gate of the drain region opposite to the data node to which the capacitor is connected around the gate is shallow, for example, 100 nm or less, the channel charge excited by the drain electrode can be reduced to reduce the short channel effect in the transistor. . However, when the source / drain junctions are made shallow while simultaneously forming the source / drain by a conventional process, a little over-etching occurs during contact hole formation in the source / drain region, and the leakage current increases, and the contact and the substrate or the well are directly Short circuiting may also occur.
이러한 문제를 해결하는 한 방법으로 MOS형 트랜지스터를 가지는 반도체 장치에서 단채널 효과를 억제할 수 있으면서도 셀 캐퍼시터를 위한 리프레시 주기 감소와 활성 영역에 콘택을 형성할 때 과식각으로 인한 전류 누설의 문제를 함께 최소화하도록 드레인과 소오스 영역의 접합 구조가 다른 비대칭 모스형 트랜지스터가 제안되었다. 그러나, 소오스 영역과 드레인 영역의 구조를 달리하기 위해서는 통상의 MOS형 트랜지스터를 제조하는 방법과 다른 방법이 필요하며 보다 효율적인 방법을 개발하는 것이 요청되고 있다.One way to solve this problem is to reduce the short-channel effect in semiconductor devices with MOS transistors, while reducing the refresh period for cell capacitors and the problem of current leakage due to over-etching when forming contacts in the active region. In order to minimize, asymmetric MOS transistors with different junction structures of drain and source regions have been proposed. However, in order to change the structure of the source region and the drain region, a method different from a conventional method of manufacturing a MOS transistor is required, and it is required to develop a more efficient method.
본 발명은 단채널 효과를 억제할 수 있으면서도 셀 캐퍼시터를 위한 리프레시 주기 감소와 활성 영역에 콘택을 형성할 때 과식각으로 인한 전류 누설의 문제를 함께 최소화할 수 있는 효율적인 반도체 장치의 비대칭 모스형 트랜지스터 형성 방법을 제공하는 것을 목적으로 한다.According to the present invention, an asymmetrical MOS transistor of an efficient semiconductor device can be suppressed while minimizing the refresh cycle for the cell capacitor and minimizing the problem of current leakage due to overetching when forming a contact in the active region. It is an object to provide a method.
도1, 도3 내지 도5는 본 발명의 일 실시예인 디램을 형성하는 중요 단계들을 나타내는 셀 영역의 공정 단면도들이다.1 and 3 to 5 are cross-sectional views of a cell region showing important steps for forming a DRAM, which is an embodiment of the present invention.
도2는 도1의 상태에서 반도체 장치의 개별 셀 부분을 위에서 본 평면도이다.FIG. 2 is a plan view of an individual cell portion of a semiconductor device viewed from above in the state of FIG.
도6은 고농도 이온주입이 이루어지는 단계에서 이온주입 마스크로 사용되는 필라형 포토레지스트 패턴이 형성된 상태를 나타내는 평면도이다.6 is a plan view showing a state in which a pillar-type photoresist pattern used as an ion implantation mask is formed in a step where a high concentration of ion implantation is performed.
도7 및 도8은 도6의 상태에서 기판을 AA 및 BB의 방향에 따라 절단한 단면을 나타내는 도면이다.7 and 8 are cross-sectional views of substrates cut along AA and BB in the state shown in FIG.
상기 목적을 달성하기 위한 본 발명은 셀 영역에서 활성 영역이 게이트 라인과 수직 방향으로 길게 형성되며 두 게이트 라인 사이에 공통의 드레인 영역이 형성되는 반도체 장치의 형성 방법에 있어서, 활성 영역의 길이 방향 중간이며 두 게이트 라인 사이에 활성 영역의 길이 방향과 수직한 방향으로 돌출되는 가지부를 형성하고, 활성 영역에 대한 이온주입 단계에서 가지부가 접속되는 활성 영역의 중간에 이온주입 마스크를 형성하고 고에너지 이온주입을 실시하는 단계가 더 구비되는 것을 특징으로 한다.SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of forming a semiconductor device in which an active region is elongated in a vertical direction with a gate line in a cell region and a common drain region is formed between two gate lines. And forming branch portions protruding in the direction perpendicular to the longitudinal direction of the active region between the two gate lines, and forming an ion implantation mask in the middle of the active region to which the branch portions are connected in the ion implantation step for the active region and It characterized in that the step is further provided.
본 발명에 의해 형성되는 반도체 장치의 각 셀에서 활성 영역의 중간은 드레인 영역이 되며 얕은 접합 구조를 가진다. 게이트 라인을 기준으로 드레인 영역 반대편의 활성 영역은 깊은 접합 구조를 가지는 소오스 영역이 된다. 그리고, 드레인 영역과 이어지는 가지부는 드레인 영역의 일부라 할 수 있으나 깊은 접합 구조를 가지며 통상 비트라인과의 접속을 위한 콘택이 형성되는 영역이다.In each cell of the semiconductor device formed by the present invention, the middle of the active region becomes a drain region and has a shallow junction structure. The active region opposite the drain region with respect to the gate line becomes a source region having a deep junction structure. The drain region and the branch portion subsequent to the drain region may be a part of the drain region, but have a deep junction structure, and are regions in which a contact for connecting to the bit line is formed.
이하 도면을 참조하면서 실시예를 통해 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도1, 도3 내지 도5는 본 발명의 일 실시예인 디램을 형성하는 중요 단계들을 나타내는 셀 영역의 공정 단면도들이다.1 and 3 to 5 are cross-sectional views of a cell region showing important steps for forming a DRAM, which is an embodiment of the present invention.
도1을 참조하면, 기판(1)에 활성 영역을 정의하는 트랜치형 소자 분리막(3)을 형성한다. 활성 영역은 셀 영역에서 일방으로 타방보다 길게 형성되고 그 중간 부분에서 길게 형성되는 방향과 수직하게 가지부가 형성된다. 기판 활성 영역에 게이트 절연막(11)이 형성되고, 게이트를 이룰 게이트 도전막(13)과 게이트 위를 덮는 보호용 실리콘 질화막(15)이 적층된다. 패터닝을 통해 보호용 실리콘 질화막(15), 게이트 도전막(13), 게이트 절연막(11)의 층구조를 가진 게이트 라인(16)이 형성된다.Referring to FIG. 1, a trench type isolation layer 3 is formed on a substrate 1 to define an active region. The active region is formed in one direction longer than the other in the cell region, and the branch portion is formed perpendicular to the direction formed longer in the middle portion. A gate insulating film 11 is formed in the substrate active region, and a gate conductive film 13 to form a gate and a protective silicon nitride film 15 covering the gate are stacked. Through patterning, a gate line 16 having a layer structure of a protective silicon nitride film 15, a gate conductive film 13, and a gate insulating film 11 is formed.
도2는 도1의 상태에서 반도체 장치의 개별 셀 부분을 위에서 본 평면도이다. 도2를 참조하면, 게이트 라인(16)은 활성 영역(14)의 길이 방향과 수직하며 가지부(18)와 평행하게 형성됨을 알 수 있다. 게이트 라인(16)과 활성 영역(14)이 겹치는 부분이 채널(22)이 되며, 게이트 라인(16)을 중심으로 활성 영역(14)의 길이 방향 양 단부가 캐퍼시터 하부 전극의 콘택 플러그와 연결되는 소오스 영역(24), 게이트 라인(16)을 중심으로 소오스 영역(24)의 상대편에 있는 부분이며 활성 영역(14)의 중간 부분이 공통 드레인 영역(26)이다. 가지부(18)는 공통 드레인 영역(26)과 맞닿아 있으나 채널 영역(22)과는 드레인 영역(26)을 통해 연결될 뿐이다.FIG. 2 is a plan view of an individual cell portion of a semiconductor device viewed from above in the state of FIG. Referring to FIG. 2, it can be seen that the gate line 16 is formed perpendicular to the longitudinal direction of the active region 14 and parallel to the branch portion 18. The overlapping portion of the gate line 16 and the active region 14 becomes the channel 22, and both ends of the active region 14 in the length direction of the active region 14 are connected to the contact plug of the capacitor lower electrode with respect to the gate line 16. The portion of the source region 24 and the gate line 16 which are opposite to the source region 24 and the middle portion of the active region 14 are the common drain region 26. The branch portion 18 is in contact with the common drain region 26 but is only connected to the channel region 22 through the drain region 26.
도3을 참조하면, 도1과 같이 게이트 라인(16)이 형성된 상태에서 기판 전면에 식각 정지용 얇은 실리콘 질화막(17)이 적층된다. 이어서 게이트 라인(16)을 이온주입 마스크로 이온주입을 실시한다. 소오스/드레인 영역(24,26) 및 가지부에 저농도의 얕은 이온주입 영역이 형성된다.Referring to FIG. 3, a thin silicon nitride film 17 for etch stop is stacked on the entire surface of the substrate in the state where the gate line 16 is formed as shown in FIG. 1. Subsequently, the gate line 16 is implanted with an ion implantation mask. Low concentration of shallow ion implantation regions are formed in the source / drain regions 24 and 26 and the branches.
도4를 참조하면, 실리콘 산화막 적층과 에치백을 통해 게이트 라인 측벽에 스페이서(31)가 형성된다. 그리고, 도면과 같이 스페이서가 형성된 상태에서 활성 영역에 소오스/드레인 영역과 같은 종류의 불순물로 얕은 저농도 이온주입이 더 실시될 수 있다.Referring to FIG. 4, spacers 31 are formed on the sidewalls of the gate lines through the silicon oxide layer stack and the etch back. As shown in the drawing, a shallow concentration of ion implantation may be further performed in the active region with impurities of the same type as the source / drain regions in the active region.
도5를 참조하면, 셀 영역에서 각 셀을 이루는 활성 영역의 중간 부분을 제외한 소오스 영역과 가지부에 고농도 고에너지 이온주입이 이루어지고 깊은 접합 영역(35)이 형성된다. 고에너지 이온주입을 위해 공통 드레인 영역을 커버하는 이온주입 마스크로 필라형 포토레지스트 패턴(33)이 이용된다.Referring to FIG. 5, a high concentration of high energy ion implantation is performed in the source region and the branch portion except for the middle portion of the active region constituting each cell in the cell region, and a deep junction region 35 is formed. A pillar-type photoresist pattern 33 is used as an ion implantation mask covering a common drain region for high energy ion implantation.
도6은 고농도 이온주입이 이루어지는 단계에서 이온주입 마스크로 사용되는 필라형 포토레지스트 패턴(33)이 형성된 상태를 나타내는 평면도이다. 따라서, 각 셀의 공통 드레인 영역(26)에서는 고농도의 불순물이 주입된 깊은 접합이 이루어지지 않고 얕은 접합 상태를 유지한다. 한편, 활성 영역 양 단의 소오스 영역(24)과, 드레인 영역(26)에 직접 연결되는 가지부(18)에는 깊은 접합이 이루어진다. 따라서, 소오스 영역(24)과 가지부(18)에 캐퍼시터나 비트라인과 연결되는 콘택을 형성하기 위해 콘택 홀 식각이 이루어질 때 다소의 과식각이 이루어지는 경우에도 누설 전류나 기판과 콘택의 단락의 문제가 방지될 수 있다.FIG. 6 is a plan view showing a state in which a pillar-shaped photoresist pattern 33 used as an ion implantation mask is formed in a step where a high concentration of ion implantation is performed. Therefore, in the common drain region 26 of each cell, a deep junction in which a high concentration of impurities are injected is not formed, and a shallow junction state is maintained. On the other hand, a deep junction is made between the source region 24 across the active region and the branch portion 18 directly connected to the drain region 26. Therefore, even when a slight overetch occurs when contact hole etching is performed to form a contact connected to a capacitor or a bit line in the source region 24 and the branch portion 18, there is a problem of leakage current or short circuit between the substrate and the contact. Can be prevented.
도7 및 도8은 도6의 상태에서 포토레지스트 패턴(33)을 제거하고 기판을 AA 및 BB의 방향에 따라 절단한 단면을 나타내는 도면이다. 소오스와 가지부에서 불순물 이온주입층이 깊은 접합 구조를 가지고 공통 드레인이 얕은 접합구조를 가짐을 알 수 있다.7 and 8 are cross-sectional views in which the photoresist pattern 33 is removed in the state of FIG. 6 and the substrate is cut along AA and BB directions. It can be seen that the impurity ion implantation layer has a deep junction structure in the source and branch portions, and the common drain has a shallow junction structure.
본 발명에 따르면, 얕은 접합 구조의 드레인 영역을 형성하여 단채널 효과를 억제할 수 있으면서도 채널의 도핑 농도를 증가시키지 않아 셀 캐퍼시터를 위한 리프레시 주기의 감소를 방지할 수 있다. 또한, 비트라인이나 캐퍼시터와 연결을 위한 콘택을 형성할 때 과식각으로 인한 전류 누설의 문제를 억제하여 콘택 홀 식각 공정의 공정 마아진을 증가시킬 수 있다.According to the present invention, it is possible to form the drain region of the shallow junction structure to suppress the short channel effect while increasing the doping concentration of the channel, thereby preventing the reduction of the refresh period for the cell capacitor. In addition, when forming a contact for connection with a bit line or a capacitor, it is possible to suppress the problem of current leakage due to overetching, thereby increasing the process margin of the contact hole etching process.
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| KR1020020075413A KR20040047265A (en) | 2002-11-29 | 2002-11-29 | Method of forming asymetric MOS transistor for semiconductor device |
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