KR20040046388A - Manufacturing method of a thin film transistor array panel - Google Patents

Abstract

PURPOSE: A method for manufacturing a TFT(Thin Film Transistor) substrate is provided to be capable of preventing the increase of the contact resistance between a sub data pad and a probe tip in a gross test for securing the reliability of the test. CONSTITUTION: A gate line is formed on an insulation substrate(110). At this time, the gate line includes a gate line(121), a gate pad(125), and a gate electrode(123). A gate isolating layer(140) is formed on the gate line. A semiconductor layer(151,154) is formed on the gate isolating layer. A resistive contact layer(161,163) is formed on the semiconductor layer. A data line is formed on the resistive contact layer, wherein the data line includes a data line, a drain electrode(175), a source electrode(173), and a data pad(179). A protection layer is formed on the data line. A photoresist pattern is formed on the protection layer, wherein the photoresist pattern has the first portion having the first thickness and the second portion having the second thickness. A contact hole is formed by selectively etching the protection layer and the data pad using the photoresist pattern as an etching mask for exposing the drain electrode. A convexoconcave portion is formed on the data pad. A pixel electrode(190) is connected with the drain electrode through the contact hole.

Description

Manufacturing method of a thin film transistor array panel

The present invention relates to a method for manufacturing a thin film transistor substrate.

A thin film transistor (TFT) substrate is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and a data line, and a pixel connected to the thin film transistor. A gate insulating layer covering and insulating an electrode, a gate wiring, and an interlayer insulating layer covering and insulating a thin film transistor and a data wiring.

After forming the thin film transistor substrate, a gross test is performed to check the operation. The gross test is to check the operation of the tester by touching the probe tip of the tester with the auxiliary data pad and applying a voltage.

However, when the probe tip is in contact with the auxiliary data pad for gross inspection, the probe tip is not fixed, causing the scratch on the auxiliary data pad to scratch, forming scratches on the auxiliary data pad and depositing the auxiliary data pad residue on the probe tip. However, indium tin oxide (ITO) or indium zinc oxide (IZO) forming an auxiliary data pad, a thin high resistance layer is formed on the surface during deposition. This is because the oxygen content of these surfaces increases due to the plasma gas remaining after deposition. Therefore, the surface debris of the auxiliary data pad has a high specific resistance, and if such material accumulates on the probe tip, the contact resistance of the probe tip becomes excessively large, thereby reducing the reliability of the test.

Accordingly, an object of the present invention is to solve the above problems, and to ensure the reliability of the test by preventing the contact resistance between the auxiliary data pad and the probe tip from increasing during the gross test.

1A is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 1B is a cross-sectional view taken along line Ib-Ib 'of FIG. 1A.

2A to 2E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

3A is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

3B and 3C are cross-sectional views taken along lines IIIb-IIIb 'and IIIc-IIIc' of FIG. 3A, respectively.

4A to 8B are diagrams for describing a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

※ Explanation of code for main part of drawing ※

95: auxiliary gate pad 97: auxiliary data pad

110: insulated substrate 121: gate line

123: gate electrode 125: gate pad

131: sustain electrode line 140: gate insulating layer

151, 154, 157, 159: semiconductor layer 161, 163, 165, 167, 169: ohmic contact layer

171: data line 173: source electrode

175: drain electrode 177: electrode for storage capacitor

179: data pad 190: pixel electrode

Method of manufacturing a thin film transistor substrate according to the present invention for achieving the above object comprises the steps of forming a gate wiring including a gate line, a gate pad and a gate electrode on an insulating substrate, forming a gate insulating layer on the gate wiring, Forming a semiconductor layer over the gate insulating layer, forming a resistive contact layer over the semiconductor layer, forming a data line including a data line, a drain electrode, a source electrode, and a data pad over the resistive contact layer, over the data line Forming a protective layer, forming a photosensitive layer pattern including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, using the photosensitive layer pattern as a mask on the protective layer; The protective layer and the data pad are etched to form a contact hole for exposing the drain electrode, and the unevenness of the data pad is formed. And a step, forming a pixel electrode via a contact hole on the protective layer connected to the drain electrode is formed.

Or forming a gate wiring including a gate line, a gate electrode, and a gate pad on an insulating substrate, sequentially stacking a gate insulating layer, a semiconductor layer not doped with impurities, a semiconductor layer doped with impurities, and a metal layer on the gate wiring. A step of etching the metal layer, the semiconductor layer doped with impurities, the semiconductor layer doped with impurities, the data wiring including the source electrode, the drain electrode, the data line, and the data pad, the ohmic contact layer having the same planar pattern as the data line, Forming a semiconductor layer having the same planar pattern as the ohmic contact layer except for a predetermined region between the source electrode and the drain electrode, forming a protective layer on the data line, a first portion having a first thickness on the protective layer; Forming a photosensitive layer pattern comprising a second portion having a second thickness thicker than the first thickness Forming a contact hole exposing the drain electrode by etching the passivation layer and the data pad using the photosensitive layer pattern as a mask, and forming an unevenness in the data pad; a pixel connected to the drain electrode through the contact hole on the passivation layer Forming an electrode.

The data line is formed of a double layer of a chromium layer and an aluminum layer, and the unevenness is formed by partially removing the aluminum layer. The first portion of the photosensitive layer pattern is formed at a position corresponding to the uneven portion of the unevenness of the data pad.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. In contrast, when a part is just above another part, it means that there is no other part in between.

Now, a thin film transistor substrate according to an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment]

1A is a layout view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line Ib-Ib ′ of FIG. 1A.

As shown in FIGS. 1A to 1B, gate wirings 121, 123, and 125 are formed on the transparent insulating substrate 110. The gate wires 121, 123, and 125 are connected to one end of the gate line 121 and the gate line 121 that are formed to extend in the horizontal direction, and receive a gate signal from the outside and transfer the gate signal to the gate line 121. The pad 125 includes a gate electrode 123 that is a part of the gate line 121.

The gate insulating layer 140 is formed on the entire surface of the substrate including the gate wirings 121, 123, and 125. On the gate insulating layer 140 of the portion corresponding to the gate electrode 123, the semiconductor layers 151 and 154 formed of a semiconductor material such as amorphous silicon and a semiconductor material such as amorphous silicon are doped with high concentrations of impurities. The ohmic contact layers 161, 163, 165, 167, and 169 are formed.

On the ohmic contacts 161, 163, 165, 167, and 169 and the gate insulating layer 140, the data wires 171, 173, 175, and 179 and the storage capacitor electrode 177 are provided with chromium patterns 711, 731, and 751. 791 and aluminum layers 712, 732, 752, and 792. The storage capacitor electrode 177 is formed to overlap the gate line 121 to improve the storage capacitance, and may not be formed when the storage capacitance is sufficient.

The data wires 171, 173, 175, and 179 are perpendicular to the gate line 121 to branch to the data line 171 and the data line 171 to define a pixel area, and are also connected to the ohmic contact layer 163. It is connected to one end of the source electrode 173 and the data line 171, and is separated from the data pad 179 and the source electrode 173 to which an image signal from an external source is applied. A drain electrode 175 formed over the opposing ohmic contact 165 of 173.

The data pad 179 has irregularities. This is formed by the groove H formed by removing a predetermined region of the aluminum pattern 792. The number of grooves H may be more or less as needed.

The protective layer 180 is formed on the data wires 171, 173, 175, and 179 and the storage capacitor electrode 177. First to fourth contact holes 181 to 184 are formed in the passivation layer 180. The first contact hole 181 exposes the drain electrode 175, the second contact hole 182 exposes the gate pad 125, and the third contact hole 183 exposes the data pad 179. The fourth contact hole 184 is formed to expose the storage capacitor electrode 177.

The pixel electrode 190 and the second contact hole 182 connected to the drain electrode 175 and the storage capacitor electrode 177 through the first and fourth contact holes 181 and 184, respectively, on the passivation layer 180. An auxiliary gate pad 95 connected to the gate pad 125 and an auxiliary data pad 97 connected to the data pad 179 through the third contact hole 183 are formed. At this time, the auxiliary data pad 97 is formed along the inside of the groove H formed in the upper portion of the data pad 179.

As described above, when the auxiliary data pad 97 is formed along the inside of the groove H, the surface of the auxiliary data pad 97 also has irregularities. If the surface of the auxiliary data pad 97 has irregularities, the probe tip does not slip during the gross inspection. In addition, the buffering action of the aluminum pattern 792 located below the probe tip when contacting the probe tip minimizes the resistance between the probe tip and the auxiliary data pad 97.

A method of manufacturing the thin film transistor substrate described above will be described with reference to FIGS. 2A through 2E. 2A to 2E are diagrams illustrating a method of manufacturing a thin film transistor substrate according to the present invention in order of process.

First, as shown in FIG. 2A, a metal layer is formed on the transparent insulating substrate 110 and then patterned by a photolithography process to form gate wirings 121, 123, and 125. The gate insulating layer 140 is formed on the gate lines 121 123 and 125.

Subsequently, an amorphous silicon layer without doping impurities and an amorphous silicon layer doped with impurities at high concentration are formed on the gate insulating layer 140, and then the amorphous silicon layer is etched by a photolithography process to immediately above the gate insulating layer 140. The semiconductor layers 151 and 154 and the ohmic contact layer patterns 160A and 161 are formed.

As shown in FIG. 2B, the chromium patterns 711, 731, 751, 771, and 791 are formed by forming a chromium layer and an aluminum layer on the substrate including the ohmic contact layer patterns 160A and 161 and patterning the same by a photolithography process. ) And the data wirings 171, 173, 175, and 179 which are a plurality of layers of the aluminum pattern 712. 732. 752. 772. 792 and the storage capacitor electrode 177.

A portion of the source electrode 173 is formed outside the semiconductor layer 154, and the semiconductor layer 154 between the source and drain electrodes 173 and 175 becomes a channel portion. The ohmic contact layer is completed by forming the source and drain electrodes 173 and 175 and then etching and removing the ohmic contact layer 160A therebetween using the source and drain electrodes 173 and 175 as an etch mask.

As shown in FIG. 2C, the protective layer 180 and the photosensitive layer PR are formed on the entire surface of the substrate including the data lines 171, 173, 175, and 179 and the storage capacitor electrode 177.

The photosensitive layer is exposed and developed through the photomask MP having the mask pattern including the slit pattern SP to form the photosensitive layer pattern PR. The slit pattern SP is used to form a groove in the data pad 179 and is disposed on the data pad 179. Since the slit pattern SP reduces exposure compared to other portions, the thickness of the photosensitive layer is thinner on the data pad 179 than in other regions.

As shown in FIG. 2D, the protective layer 180 and the aluminum pattern 791 are etched using the photosensitive layer pattern PR as a mask to form the first, second, and fourth contact holes 181, 182, and 184 and the grooves H. ).

As illustrated in FIG. 2E, the photosensitive layer pattern PR formed on the data pad 179 is removed by etch back. At this time, the photosensitive layer pattern PR formed in addition to the data pad 179 is also removed by a predetermined thickness. Thereafter, the protective layer 180 formed on the data pad 179 is removed to form the third contact hole 183.

Finally, after removing the remaining photoresist layer pattern PR, IZO is deposited on the passivation layer 180. The IZO layer is patterned to form the pixel electrode 190, the auxiliary data pad 179, and the auxiliary gate pad 95 (see FIG. 1B). The auxiliary data pad 97 is formed along the inside of the groove H to have irregularities.

Second Embodiment

3A is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIGS. 3B and 3C are cross-sectional views taken along lines IIIb-IIIb 'and IIIc-IIIc' of FIG. 3A.

As shown in FIGS. 3A to 3C, gate wirings 121, 123, and 125 and a storage electrode line 131 are formed directly on the transparent insulating substrate 110.

The gate lines 121, 123, and 125 include a gate line 121, a gate pad 125, and a gate electrode 123. The storage electrode line 131 overlaps with the storage capacitor electrode 177 connected to the pixel electrode 190, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. The storage electrode line 131 is formed of the pixel electrode 190 and the gate line 121. It may not be formed if the holding capacity generated by the overlap is sufficient.

A gate insulating layer 140 is formed on the gate wirings 121, 123, and 125 and the storage electrode line 131, and the semiconductor layers 151, 154, 157, and 159 and the ohmic contact layer (eg, on the gate insulating layer 140). 161, 163, 165, 167, and 169 are formed.

And a data line formed of a double layer of chromium patterns 711, 731, 751, 771, and 791 and aluminum patterns 712, 732, 752, 772, and 792 on the ohmic contacts 161, 163, 165, 167, and 169. 171, 173, 175, and 179 and sustain electrodes 177 are formed.

The data lines 171, 173, 175, and 179 include a data line 171, a data pad 179, a source electrode 173, and a drain electrode 175. The data wires 171, 173, 175, and 179, the storage capacitor electrode 177, and the ohmic contact layers 161, 163, 165, 167, and 169 are formed in the same planar pattern, and the semiconductor layers 151, 154, 157 and 159 are formed in the same planar pattern as those except for the channel portion 154. In other words, the source electrode 173 and the drain electrode 175 are separated from the channel portion 154, and the ohmic contact layers 163 and 165 disposed under the source and drain electrodes 173 and 175 are also separated from each other. 154 are connected without separation to form a channel of the thin film transistor.

The data pad 179 has irregularities. The unevenness is due to the groove H formed in the aluminum pattern 792, which is the upper layer of the data pad 179. The number of grooves H may be more or less as needed. The storage capacitor electrode 177 is not formed when the storage electrode line 131 is not formed.

The passivation layer 180 including the first to fifth contact holes 181 to 185 is formed on the data lines 171, 173, 175, and 179 and the storage capacitor electrode 177. The first contact hole 181 exposes the drain electrode 175, the second contact hole 182 exposes the gate pad 125, and the third contact hole 183 exposes the data pad 179. The fourth and fifth contact holes 183 and 184 expose the storage capacitor electrode 177. The pixel electrode 190 and the second contact hole are respectively connected to the drain electrode 175 and the storage capacitor electrode 177 through the first, fourth, and fifth contact holes 181, 184, and 185 on the passivation layer 180. An auxiliary gate pad 95 is formed to be connected to the gate pad 125 through 184. In addition, the auxiliary data pad 97 is connected to the data pad 179 through the third contact hole. The auxiliary data pad 97 is formed along the inside of the groove H.

A method of manufacturing the thin film transistor substrate according to the second embodiment will be described with reference to FIGS. 4A through 8B as follows. 4A to 8B are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate according to the second embodiment in the order of process.

First, as shown in FIGS. 4A to 4B, a gate layer 121, 123, and 125 are formed by forming and then patterning a metal layer directly on the transparent insulating substrate 110. The gate insulating layer 140, the amorphous silicon layer 150 which is not doped with impurities, the amorphous silicon layer 160 which is doped with impurities, and the chromium layer are formed on the gate wirings 121, 123, and 125 and the storage electrode line 131. 701 and an aluminum layer 702 are formed.

The photosensitive layer is formed directly on the aluminum layer 702, and then exposed and developed to form the photosensitive layer pattern PR1. The photoresist layer pattern PR may include the data line 171, 173, 175, and 179 and the storage capacitor electrode 177 between the source and drain electrodes, which will be the channel portion 154 of the thin film transistor. The thickness is made thinner than the second part B, which is a part to be formed, and all the photosensitive layers of the other part C are removed to expose the aluminum layer 702.

Such a method of controlling the thickness of the photosensitive layer pattern PR1 may be formed by forming a slit or lattice pattern or using a semi-transparent layer, and may be selected and used as necessary.

As shown in FIGS. 5A to 5B, the aluminum layer 702, the chromium layer 701, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon doped with impurities are formed using the photosensitive layer pattern PR1 as a mask. Data layers 171, 173, 175, and 179 formed of aluminum patterns 711, 731, 751, 771, and 791 and chrome patterns 712, 732, 752, 772, and 792 by sequentially etching the silicon layer 150. And the storage capacitor electrode 177, the ohmic contacts 161, 162, 163, 165, and 169, and the semiconductor layers 151, 153, 157, and 159.

In more detail, the etching using the photosensitive layer pattern PR1 as a mask is performed in multiple steps. First, the amorphous silicon layer 160 doped with impurities is exposed by wet etching a region (third portion: C) where the photosensitive layer pattern PR1 is not formed to remove the aluminum layer 702 and the chromium layer 701. .

Thereafter, together with the photosensitive layer pattern PR1 of the first part A, the amorphous silicon layer 160 doped with the impurity of the third part C and the amorphous silicon layer 150 without the dopant are dry-etched to form a semiconductor. The layer is completed to form an ohmic contact layer in which the channel portion is not separated, wherein the photosensitive layer of the second part B is also partially etched.

Next, the aluminum layer 702 on the upper portion of the channel portion is exposed by ashing to remove the photosensitive layer residue of the first portion (A).

Subsequently, the aluminum layer 702, the chromium layer 701 and the amorphous silicon layer 160 doped with impurities are etched in the first portion A to etch the data lines 171, 173, 175, and 179 and the storage capacitor electrode. 177, the semiconductor layers 161, 163, and 165, and the ohmic contacts 151 and 154 are completed. Thereafter, the photosensitive layer PR of the second part B is removed.

The protective layer 180 and the photosensitive layer are formed on the entire surface of the substrate including the data lines 171, 173, 175, and 179 and the storage capacitor electrode 177 in FIGS. 6A to 6B.

The photosensitive layer is exposed and developed through the photomask MP having the mask pattern including the slit pattern SP to form the photosensitive layer pattern PR2. The slit pattern SP is used to form a groove in the data pad 179 and is disposed on the data pad 179. Since the slit pattern SP reduces exposure compared to other portions, the thickness of the photosensitive layer is thinner on the data pad 179 than in other regions.

As shown in FIGS. 7A to 7B, the protective layer 180 and the aluminum patterns 752, 772, and 792 are etched using the photosensitive layer pattern PR as a mask to form first, second, fourth, and fifth contact holes 181. , 182, 184, and 185 and the groove H are formed.

8A to 8B, the photosensitive layer pattern PR2 formed on the data pad 179 is removed by etch back. At this time, the photosensitive layer pattern PR2 formed in addition to the data pad 179 is also removed by a predetermined thickness. Thereafter, the protective layer 180 formed on the data pad 179 is removed to form the third contact hole 183.

Finally, after removing the remaining photoresist layer pattern PR2, IZO is deposited on the passivation layer 180. The IZO layer is patterned to form the pixel electrode 190, the auxiliary data pad 97, and the auxiliary gate pad 95 (see FIGS. 3B and 3C). The auxiliary data pad 97 is formed along the inside of the groove H.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the method according to the present invention can form a groove, so that the auxiliary data pad is formed along the inside of the groove to minimize the resistance between the auxiliary data pad and the probe tip to improve the reliability of the test. . And using the slit pattern does not require an additional process when forming the groove.

Claims (6)

Forming a gate wiring including a gate line, a gate pad, and a gate electrode on the insulating substrate, Forming a gate insulating layer on the gate wiring; Forming a semiconductor layer on the gate insulating layer, Forming an ohmic contact layer over the semiconductor layer; Forming a data line including a data line, a drain electrode, a source electrode, and a data pad on the ohmic contact layer; Forming a protective layer on the data line; Forming a photosensitive layer pattern on the protective layer, the photosensitive layer pattern including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; Forming a contact hole exposing the drain electrode by etching the protective layer and the data pad by using the photosensitive layer pattern as a mask, and forming irregularities in the data pad; Forming a pixel electrode connected to the drain electrode through a contact hole on the passivation layer. Forming a gate wiring including a gate line, a gate electrode, and a gate pad on the insulating substrate, Sequentially depositing a gate insulating layer, a semiconductor layer not doped with impurities, a semiconductor layer doped with impurities, and a metal layer on the gate wiring; Etching the metal layer, the semiconductor layer doped with impurities, the semiconductor layer doped with impurities, a data wiring including a source electrode, a drain electrode, a data line, and a data pad, an ohmic contact layer having the same planar pattern as the data wiring; Forming a semiconductor layer having the same planar pattern as the ohmic contact layer except for a predetermined region between the source electrode and the drain electrode; Forming a protective layer on the data line; Forming a photosensitive layer pattern on the protective layer, the photosensitive layer pattern including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; Forming a contact hole exposing the drain electrode by etching the protective layer and the data pad by using the photosensitive layer pattern as a mask, and forming irregularities in the data pad; Forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer. The method of claim 1 or 2, The data line is formed of a double layer of a chromium layer and an aluminum layer, and the unevenness is formed by partially removing the aluminum layer. The method of claim 1 or 2, And a first portion of the photosensitive layer pattern is formed at a position corresponding to the uneven portion of the unevenness of the data pad. The method of claim 1 or 2, Forming the photosensitive layer pattern, Disposing an optical mask having a mask pattern including a slit pattern corresponding to a predetermined area of the data pad on the photosensitive layer; Exposing and developing the photosensitive layer through the photomask. The method of claim 1 or 2, Forming the irregularities in the data pad, Etching the protective layer and the data pad using the photosensitive layer pattern as a mask to form grooves in the first to second contact holes and the data pad in the protective layer; Removing the protective layer formed on the data pad after removing the photosensitive layer pattern having the first thickness by etch back to form a third contact hole; Removing the photosensitive layer pattern formed in a region other than the data pad.