KR20040046340A - Fabricating Method Of Nonvolatile Memory Device - Google Patents

Abstract

PURPOSE: A method for manufacturing a non-volatile memory device is provided to prevent the etching damage for an electric charge storing layer and restrain an under-cut region from being generated at the lateral portion of a lower oxide pattern by using a spacer. CONSTITUTION: A lower oxide pattern(115), an electric charge storing pattern(125), and a sacrificial oxide pattern(135) are sequentially deposited on a semiconductor substrate(100). A spacer(160) is formed at the sidewalls of the lower oxide pattern, the electric charge storing pattern, and the sacrificial oxide pattern. The electric charge storing pattern and the semiconductor pattern are selectively exposed to the outside by removing the sacrificial oxide pattern and the spacer. An upper oxide layer is formed on the entire surface of the resultant structure.

Description

Fabrication Method Of Nonvolatile Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nonvolatile memory of a Sonos type.

A nonvolatile memory device is a semiconductor device that can maintain stored information even when power is not supplied. The demand for such a nonvolatile memory device is rapidly increasing as the electronic device becomes smaller and more portable, and a flash memory device having a floating gate is most commonly used.

The flash memory uses a high potential difference of approximately 10 V or more during program and erase operations. The program and erase operations are processes for changing information stored in a cell transistor of the flash memory. On the other hand, the flash memory having the floating gate is provided with a plurality of pumping circuits in the peripheral circuit region to form a high potential difference of 10V or more. In addition, the transistors and the wirings arranged in the flash memory have a difficulty of being formed so as not to breakdown even at the high potential difference. Accordingly, research has recently been conducted on SONOS type nonvolatile memory devices using an insulating film having a trap site, particularly a silicon nitride film, as a charge storage film.

1 and 2 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the prior art.

Referring to FIG. 1, a lower oxide film 20, a charge storage film, a sacrificial oxide film, and an antireflection film are sequentially formed on the semiconductor substrate 10. As the charge storage film, a silicon nitride film having a large number of trap sites is commonly used. The number of charge trapped at the trap site affects the magnitude of the read current, and this process is used as the operating principle of the sonos type nonvolatile memory. The anti-reflection film is a material film for the convenience of subsequent photographic processes, in which a silicon oxynitride film is usually used.

A photoresist pattern 60 is formed on the anti-reflection film to expose a predetermined region of the semiconductor substrate by using a conventional photolithography process. Thereafter, an etching process using the photoresist pattern 60 as an etching mask is performed until the lower oxide layer 20 is exposed. Accordingly, the charge storage layer pattern 30, the sacrificial oxide layer pattern 40, and the anti-reflection layer pattern 50 that are sequentially stacked are interposed between the lower oxide layer 20 and the photoresist pattern 60.

Referring to FIG. 2, the photoresist pattern 60, the anti-reflection film pattern 50, and the sacrificial oxide film pattern 40 are sequentially removed. The photoresist pattern 60 may be removed by ashing, and the anti-reflection film pattern 50 and the sacrificial oxide pattern 40 may be removed by wet etching. Thereafter, an upper oxide layer 80 is formed on the entire surface of the semiconductor substrate from which the sacrificial oxide pattern 40 is removed. A gate electrode 90 is formed on the upper oxide layer 80 to pass over an upper sidewall of the charge storage layer pattern 30.

On the other hand, removing the anti-reflection film pattern 50 may cause etching damage 33 to the charge storage film pattern 30. As described above, the anti-reflection film pattern 50 is formed of a silicon oxynitride film, and the wet etching process of removing the anti-reflection film pattern 50 does not have excellent etching selectivity with respect to the charge storage film pattern 30. Accordingly, the side surface of the charge storage layer pattern 30 exposed in the step of removing the anti-reflection layer pattern 50 may be etched damage 33. Since the etching damage 33 may cause a malfunction of the nonvolatile memory, a technique for preventing the etching damage 33 is required.

In order to prevent such a problem, a method of increasing the thickness of the rare production layer pattern 40 without using the anti-reflection film pattern 50 has been attempted. 3 and 4 are process cross-sectional views illustrating a method of manufacturing a nonvolatile memory device using the method of increasing the thickness of the sacrificial oxide pattern 40 as described above.

3 and 4, after forming the lower oxide layer 20, the charge storage layer, and the sacrificial oxide layer that are sequentially stacked on the semiconductor substrate 10, a photoresist pattern 60 is formed on the resultant. The sacrificial oxide film is formed thicker than the case described with reference to FIG. 1. An etching process using the photoresist pattern 60 as an etching mask is performed, and the charge storage layer pattern 30 and the sacrificial oxide layer pattern 40 ′ interposed between the lower oxide layer 20 and the photoresist pattern 60. ).

Thereafter, the photoresist pattern 60 and the sacrificial oxide layer pattern 40 ′ are sequentially removed. Removing the sacrificial oxide pattern 40 'is performed by a wet etching method. As described above, the thick sacrificial oxide pattern 40' etches the lower oxide layer 20 having a thickness of several tens of microseconds. Accordingly, an undercut region 99 is formed under the charge storage layer pattern 30. Thereafter, the upper oxide film 80 and the gate electrode 90 are formed in the same manner as described with reference to FIG. 2. As a result, the undercut region 99 may fill the upper oxide layer 80, which is a chemical vapor deposition oxide layer, instead of the lower oxide layer 20, which is a thermal oxide layer, or may remain as a void. The undercut region 99 included in the cell transistor in which the information is stored may deteriorate the characteristics of the sonos type nonvolatile memory, which is not preferable.

An object of the present invention is to provide a method of manufacturing a nonvolatile memory device that can prevent the etching damage to the charge storage layer.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of preventing the formation of an undercut region on the side surface of a lower oxide film pattern.

1 and 2 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the prior art.

3 and 4 are process cross-sectional views illustrating yet another method for manufacturing a nonvolatile memory device according to the prior art.

5 through 10 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

11 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device in accordance with another embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a non-volatile memory device comprising the step of forming a spacer covering the sides of the charge storage layer pattern and the lower oxide layer pattern. In this method, a lower oxide pattern, a charge storage layer pattern, and a sacrificial oxide pattern are sequentially formed on a semiconductor substrate, and spacers are formed on sidewalls of the lower oxide pattern, the charge storage layer pattern, and the sacrificial oxide pattern. And removing the oxide layer pattern and the spacer together to expose the charge storage layer pattern and the semiconductor substrate on its side. Thereafter, an upper oxide layer is formed on the entire surface of the semiconductor substrate to which the charge storage layer pattern is exposed.

In this case, the lower oxide layer pattern may be formed by a thermal oxidation technique, and the upper oxide layer may be formed by using a combination of a thermal oxidation technique and a chemical vapor deposition technique. The charge storage layer pattern may be formed of a silicon nitride layer or a silicon oxynitride layer, and the spacer may be formed of the same material as the sacrificial oxide layer pattern, that is, a silicon oxide layer.

In addition, an anti-reflection film including one of a silicon oxynitride film and a silicon nitride film may be further formed on the sacrificial oxide film pattern. In this case, the step of removing the anti-reflection film is further performed before forming the spacer. After forming the upper oxide layer, a gate electrode passing over an upper sidewall of the charge storage layer pattern may be further formed.

It is preferable that the width of the spacer is at least thicker than the thickness of the sacrificial oxide film pattern. In addition, the removing of the sacrificial oxide pattern and the spacer is preferably performed by a wet etching method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

5 through 10 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 5, the lower oxide film 110, the charge storage film 120, the sacrificial oxide film 130, and the anti-reflection film 140 are sequentially formed on the semiconductor substrate 100. Thereafter, a photoresist pattern 150 is formed to expose a predetermined region of the anti-reflection film 140 using a conventional photolithography process.

The lower oxide film 110 is a silicon oxide film formed by thermally oxidizing an upper surface of the semiconductor substrate 100, and the sacrificial oxide film 130 is a silicon oxide film formed through a chemical vapor deposition (CVD) process. (SiO ₂ ). The charge storage film 120 is preferably a silicon nitride film (Si ₃ N ₄ ) known to be rich in charge trapping positions, it may be a silicon oxynitride film (SiON). The anti-reflection film 140 is at least one material selected from a silicon oxynitride film, a silicon oxide film, and a silicon nitride film.

Referring to FIG. 6, the anti-reflection film 140 and the sacrificial oxide film 130 are etched using the photoresist pattern 150 as an etching mask. Accordingly, the lower oxide film 110, the charge storage film 120, the sacrificial oxide film pattern 135, and the anti-reflection film pattern 145 are sequentially formed on the semiconductor substrate 100 under the photoresist pattern 150. The charge storage layer 120 is exposed around the photoresist pattern 150. An etching process for forming the sacrificial oxide film pattern 135 and the anti-reflection film pattern 145 is performed by an anisotropic etching method.

Referring to FIG. 7, the photoresist pattern 150 is removed to expose the anti-reflection film pattern 145. The photoresist pattern 150 is preferably removed using a gas containing oxygen such as ozone, and may further comprise a step of cleaning with a wet cleaning solution such as sulfuric acid.

Subsequently, the charge storage layer 120 and the lower oxide layer 110 are sequentially etched using the anti-reflection layer pattern 145 and the sacrificial oxide layer pattern 135 as an etching mask. Accordingly, the lower oxide film pattern 115 and the charge storage film pattern 125 are sequentially stacked below the antireflection film pattern 145. On the other hand, the etching process may cause etching damage to the upper surface of the semiconductor substrate 100 used as the channel region. In order to minimize such etching damage, the etching process is preferably a dry etching process using a low power plasma. As another method for preventing the etching damage, an etching process for forming the charge storage layer pattern 125 may be performed such that the lower oxide layer pattern 115 remains on the semiconductor substrate 100. In addition, the photoresist pattern 150 may be removed after being used in etching the charge storage layer 120 and the lower oxide layer 110.

A spacer insulating layer is formed on the entire surface of the semiconductor substrate on which the charge storage layer pattern 125 and the lower oxide layer pattern 115 are formed. The spacer insulating layer is anisotropically etched to form spacers 160 on sidewalls of the lower oxide layer pattern 115, the charge storage layer pattern 125, the sacrificial oxide layer pattern 135, and the anti-reflection layer pattern 145. The spacer insulating layer may be formed to be at least thicker than the thickness of the sacrificial oxide layer pattern 135. The spacer 160 may be formed of the same material as the sacrificial oxide pattern 135, that is, a silicon oxide layer.

Referring to FIG. 8, the upper surface of the sacrificial oxide layer pattern 135 is exposed by removing the anti-reflection layer pattern 145 using the spacer 160 as an etching mask. The etching process for removing the anti-reflection film pattern 145 uses an etching recipe having an etching selectivity with respect to the silicon oxide film, and preferably, an isotropic wet etching method using an etching solution containing phosphoric acid.

The charge storage layer pattern 125 is protected from the etching process using the phosphoric acid by the sacrificial oxide layer pattern 135 and the spacer 160 covering the top and side surfaces thereof, respectively. On the other hand, the upper edge of the spacer 160 may be smoothed by the etching process.

Referring to FIG. 9, the exposed sacrificial oxide layer pattern 135 is removed to expose the charge storage layer pattern 125. The sacrificial oxide layer pattern 135 may be removed by isotropic etching using an etching recipe having an etch selectivity with respect to the charge storage layer pattern 125. To this end, the etching process is carried out using an etching solution containing hydrofluoric acid. Accordingly, the spacer 160 formed of the silicon oxide layer is etched together with the sacrificial oxide layer pattern 135.

In this case, when the spacer 160 remains, the operation characteristics of the cell transistor may be adversely affected. Therefore, when the sacrificial oxide layer pattern 135 is removed, the spacer 160 may be completely removed. To this end, the width of the spacer 160 is thinner than the thickness of the sacrificial oxide pattern 135. However, when the spacer 160 is too thin, the undercut region mentioned in the related art may be formed by removing the sacrificial oxide layer pattern 135. As a result, the spacer 160 is preferably similar to the thickness of the sacrificial oxide pattern 135 remaining immediately before the removal process. To this end, the spacer insulating film is formed in consideration of the thickness, etc., which are recessed in the anti-reflection film pattern 145 removal process or the like as described above.

Referring to FIG. 10, an upper oxide layer 170 is formed on an entire surface of the semiconductor substrate from which the sacrificial oxide pattern 135 and the spacer 160 are removed. The upper oxide film 170 may be formed by a combination of a thermal oxidation process and a chemical vapor deposition process.

The gate electrode 180 passing through the sidewall of the charge storage layer pattern 125 is formed on the upper oxide layer 170. The gate electrode 180 is preferably formed of polycrystalline silicon.

11 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device in accordance with another embodiment of the present invention.

Referring to FIG. 11, when comparing this embodiment with the embodiment described with reference to FIGS. 5 to 10, the photoresist pattern 150 is formed directly on the sacrificial oxide film without forming the anti-reflection film (140 in FIG. 5). The difference is in that. That is, the lower oxide film 110, the charge storage film 120, the sacrificial oxide film, and the photoresist pattern 150 that are sequentially stacked on the semiconductor substrate 100 are formed. The photoresist pattern 150 exposes the sacrificial oxide film in a predetermined region.

The exposed sacrificial oxide layer is etched by performing an anisotropic etching process using the photoresist pattern 150 as an etching mask. Accordingly, a sacrificial oxide layer pattern 135 is formed between the charge storage layer 120 and the photoresist pattern 150. Subsequently, after the photoresist pattern 150 is removed, the charge storage layer 120 and the lower oxide layer 110 are sequentially etched using the sacrificial oxide layer pattern 135 as an etching mask. As a result, a lower oxide layer pattern (115 in FIG. 7) and a charge storage layer pattern (125 in FIG. 7) that are sequentially stacked on the semiconductor substrate 100 are formed below the sacrificial oxide layer pattern 135.

Subsequently, as described with reference to FIGS. 7 to 10, a spacer (170 of FIG. 7) is formed, and the sacrificial layer pattern 135 is removed using the spacer mask as an etching mask. These processes are carried out according to one embodiment described above.

According to the present invention, a spacer covering sidewalls of the charge storage layer pattern and the lower oxide layer pattern is formed. In this case, the spacer is used as an etching mask to prevent etching damage in the etching process for removing the sacrificial pattern. In addition, the spacer prevents a problem that an undercut region is formed. Accordingly, a cell transistor of a sonos type nonvolatile memory in which no etching damage, voids, or the like are formed can be manufactured.

Claims (10)

Forming a lower oxide layer pattern, a charge storage layer pattern, and a sacrificial oxide layer pattern sequentially stacked on the semiconductor substrate; Forming a spacer on sidewalls of the lower oxide pattern, the charge storage layer pattern, and the sacrificial oxide pattern; Removing the sacrificial oxide pattern and the spacer together to expose the charge storage layer pattern and the semiconductor substrate on the side surface thereof; And And forming an upper oxide layer on the entire surface of the semiconductor substrate to which the charge storage layer pattern is exposed. The method of claim 1, And forming the lower oxide layer pattern using a thermal oxidation technique. The method of claim 1, And forming the upper oxide layer using a thermal oxidation technique and a chemical vapor deposition technique. The method of claim 1, The charge storage layer pattern may be formed of a silicon nitride layer or a silicon oxynitride layer. The method of claim 1, And an antireflection film including one of a silicon oxynitride film and a silicon nitride film is further disposed on the sacrificial oxide film pattern. The method of claim 5, wherein And removing the anti-reflection film before forming the spacers. The method of claim 1, And the spacer is formed of a silicon oxide film. The method of claim 1, The width of the spacer is at least thicker than the thickness of the sacrificial oxide film pattern manufacturing method of a nonvolatile memory device. The method of claim 1, The removing of the sacrificial oxide pattern and the spacer is a method of manufacturing a nonvolatile memory device, characterized in that the wet etching method. The method of claim 1, And forming a gate electrode passing over an upper sidewall of the charge storage layer pattern after the upper oxide layer is formed.