JP2013149647A - Semiconductor nonvolatile storage device manufacturing method and semiconductor nonvolatile storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that microfabrication of a MONOS memory transistor cannot be achieved because a channel width finer than a pattern resolution limit of a photolithographic technique using vacuum-ultraviolet light as an exposure light source cannot be manufactured.SOLUTION: In a semiconductor nonvolatile storage device manufacturing method, a channel width finer than a pattern resolution limit of a photolithographic technique using vacuum-ultraviolet light as an exposure light source by using a cavity generated when an insulation film for forming a sidewall is formed is formed in a facing space between a pair of thin film structures. When the thin film structures are used as components of other elements, the semiconductor nonvolatile storage device can be applied to various memory cells and circuit structures.

Description

  The present invention relates to a manufacturing method and a structure of a semiconductor nonvolatile memory device provided on a semiconductor substrate. In particular, the present invention relates to a manufacturing method and a structure of a semiconductor nonvolatile memory device having a narrow channel width which is difficult to manufacture by a photolithography technique using vacuum ultraviolet light as an exposure light source.

A semiconductor nonvolatile memory device generally has a MIS type memory transistor (hereinafter referred to as MIS type memory transistor) structure.
The MIS type memory transistor includes, for example, a source region, a drain region, and a channel region sandwiched between them in an element region defined by an element isolation film provided on a semiconductor substrate, and a memory insulating film above the channel region. And a memory gate electrode are stacked.
Information is stored using the difference between the threshold voltage when charges are accumulated in the memory insulating film and the threshold voltage when charges are not accumulated.

In the MIS type memory transistor having such a structure, the memory insulating film has a structure in which a plurality of insulating films are stacked, and one of the insulating films is used as a charge storage film, and is stored in a charge trap in the charge storage film. There are known a MNOS (Metal-Nitride-Oxide-Silicon) type and a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that store information by controlling the amount of charge to be generated.
In particular, since the MONOS type has a feature that data can be read and written at a low voltage, it is attracting attention as being suitable for an electronic device aiming at low power consumption.

  In general, a MIS type memory transistor is formed in an element region surrounded by an element isolation film. When an element region is provided by a LOCOS (Local-Oxidation-of-Silicon) method, which is well known as an element isolation method, the manufacture thereof is performed. As a feature of the method, there is an inclined structure in which the end of the element isolation film surrounding the element region is gradually thinned toward the end of the element region. Such an inclined portion is referred to as a bird's beak in accordance with the shape of a bird's beak.

When the MIS type memory transistor is provided in the element region defined by the element isolation film formed by the LOCOS method, the element is arranged so that the end of the memory gate electrode straddles the bird's beak region at the end of the element region in plan view. The structure is provided on the separation region.
Such a structure is well known. For example, Patent Document 1 illustrates a cross-sectional view.

The prior art shown in Patent Document 1 will be described with reference to FIG.
FIG. 15 is a diagram rewritten for easy explanation of the technique described in Patent Document 1, and is a MONOS type transistor which is a typical MIS type memory transistor in an element region provided by forming an element isolation film by the LOCOS method. It is sectional drawing which showed the typical formation technique which forms a memory transistor to process order.

  First, as shown in FIG. 15A, a pad oxide film 102 is formed on the surface of the semiconductor substrate 101. Next, an oxidation-resistant mask 103 made of a silicon nitride film is formed with a predetermined line width Wa in a region to be an element region in a later process. The line width Wa is intended to be the channel width of a MONOS type memory transistor completed through a later process, and is a designed channel width.

  The channel width refers to the distance between the source region and the drain region. For example, when the channel width is 0.5 μm, the source region and the drain region face each other over 0.5 μm. Note that the channel length refers to the distance from the source region to the drain region.

  As is known, since a current flows in the channel length direction and a current path exists in the channel width direction, the magnitude of the channel width is related to the current driving capability of the MIS type memory transistor, and the magnitude of the channel length is , Related to the operating speed. Generally, a small MIS type memory transistor capable of high-speed operation has a short channel width and channel length.

Next, as shown in FIG. 15B, an element isolation film 104 made of a silicon oxide film is formed in a region not covered with the oxidation resistant mask 103 by a known thermal oxidation method using water vapor. When the formation of the element isolation film 104 is completed, the end portion of the oxidation resistant mask 103 is turned up. This is because a silicon oxide film grows under the end portion of the oxidation-resistant mask and a bird's beak is formed by a distance indicated by a distance Wb.
Note that the portion immediately below the oxidation-resistant mask 103 has the thickness of the pad oxide film 102 because the oxidation does not proceed.

  Next, as shown in FIG. 15C, the element region 105 is formed by removing the oxidation resistant mask 103 and the pad oxide film 102 after the element isolation film 104 is formed. Thereafter, the memory insulating film 106 and the memory gate electrode 107 are formed so as to straddle the bird's beak region from the element region 105 to the element isolation film 104.

  In the case of a MONOS memory transistor, the memory insulating film 106 is a laminated film in which a charge storage layer that stores charges is sandwiched between a first insulating film that functions as a tunnel oxide film and a second insulating film that is a top oxide film. The first insulating film, the charge storage layer, and the second insulating film are stacked in this order from the semiconductor substrate 101 direction.

  Thereafter, although not shown, a source region and a drain region are formed in the element region 105 using the memory gate electrode 107 as a mask to complete a MONOS type memory transistor.

The channel region of the MONOS memory transistor is formed in, for example, a rectangular shape with a predetermined channel length and channel width as a region where the memory gate electrode and the element region are aligned. In the case of FIG. 15C, the depth direction from the front of the drawing is the channel length direction, and the horizontal direction of the drawing is the channel width direction.
In the example shown in FIG. 15C, the channel width is actually the effective channel width Wc (actually because the oxidation proceeds in the lateral direction of the drawing by the distance Wb of the bird's beak portion and bites into the channel region. The distance that functions as the channel width is a distance obtained by subtracting the distance Wb from the line width Wa.

JP-A-5-343695 (page 2, FIG. 6)

  When designing an MIS type memory transistor, in forming an element region using the LOCOS method, a channel width is designed in consideration of generation of this bird's beak, that is, oxidation proceeds to the channel region by a distance Wb of the bird's beak portion. There is a need.

In the example shown in FIG. 15, the distance Wb of the bird's beak portion is, for example, about 200 nm when the thickness of the element isolation film 104 is 500 nm.
In this example, in the case of an element having a large channel width (for example, the line width Wa is 10,000 nm), the bird's beak portion is negligibly small. However, in the case of an element with a small channel width (for example, the line width Wa is 1000 nm), the effective channel width becomes extremely small. In this case, the variation caused by the formation of the element isolation film causes the variation of the effective channel width, and as a result, the electric characteristics as the element also vary.

  By the way, a method of manufacturing an MIS type memory transistor without using the LOCOS method is also known. However, such a method cannot be applied to all semiconductor nonvolatile memory devices because the manufacturing process becomes more complicated and a special processing apparatus is required for manufacturing.

  Whether or not the LOCOS method is used in the manufacture of a semiconductor nonvolatile memory device, the mask pattern itself determines the size of the main part of the MIS type memory transistor such as the channel width. is there. As you know, the photolithographic technology that uses vacuum ultraviolet light as an exposure light source has the limitations of pattern resolution. Even if an attempt is made to obtain a finer element region to form a pattern with a narrower line width, a pattern smaller than the limit of pattern resolution cannot be formed.

  Therefore, even if an attempt is made to obtain a MIS-type memory transistor that is finer and does not vary in electrical characteristics due to the recent trend of semiconductor non-volatile memory devices with low power consumption and high integration, pattern resolution determined by the photolithography technology used. An MIS type memory transistor having a channel width smaller than the above limit could not be formed.

  The manufacturing method and structure of the semiconductor nonvolatile memory device of the present invention are for solving such problems. The object is to stably provide an MIS type memory transistor having a channel width finer than the pattern resolution limit of an exposure apparatus used for pattern processing.

  In order to achieve the above object, a method for manufacturing a semiconductor nonvolatile memory device according to the present invention employs the following.

A method for manufacturing a semiconductor nonvolatile memory device, wherein a source region, a channel region, and a drain region are provided on a semiconductor substrate, a memory insulating film is provided on the semiconductor substrate above the channel region, and a memory gate electrode is provided on the memory insulating film. ,
A structure forming step of forming a set of thin film structures at a predetermined interval on the upper portion of the semiconductor substrate above the portion for forming the channel region;
An insulating film forming step of covering the set of thin film structures and forming an insulating film so as to form a gap in the gap;
Etching back the insulating film in the direction of the semiconductor substrate to expose the air gap, leaving the insulating film as a sidewall on the vertical end surface of the thin film structure facing the interval;
A memory insulating film forming step of forming a memory insulating film on the semiconductor substrate at an interval;
A memory gate electrode forming step of forming a memory gate electrode on the memory insulating film;
Using the thin film structure and sidewalls and the memory gate electrode as a mask, a predetermined impurity ion is implanted into the semiconductor substrate to form a source region, a channel region, and a drain region,
It is characterized by having.

  With such a configuration, it is possible to form a semi-nonconductive nonvolatile memory device having a channel width finer than the pattern resolution limit of the photolithography process using vacuum ultraviolet light as an exposure light source.

A method for manufacturing a semiconductor nonvolatile memory device, wherein a source region, a channel region, and a drain region are provided on a semiconductor substrate, a memory insulating film is provided on the semiconductor substrate above the channel region, and a memory gate electrode is provided on the memory insulating film. ,
An element isolation step of forming an element isolation film on the surface of the semiconductor substrate;
A structure forming step of forming a set of thin film structures at a predetermined interval on the upper portion of the element isolation film above the portion forming the channel region;
An insulating film forming step of covering the set of thin film structures and forming an insulating film so as to form a gap in the gap;
An etching back step of etching away the insulating film in the direction of the semiconductor substrate to expose the voids and leaving the insulating film as a sidewall on the vertical end surface of the thin film structure facing the interval;
An exposure step of exposing the surface of the semiconductor substrate by etching away the element isolation film at intervals using the thin film structure and sidewalls as a mask;
A memory insulating film forming step of forming a memory insulating film on the semiconductor substrate at intervals;
A memory gate electrode forming step of forming a memory gate electrode on the memory insulating film;
Using the thin film structure and sidewalls and the memory gate electrode as a mask, a predetermined impurity ion is implanted into the semiconductor substrate to form a source region, a channel region, and a drain region,
It is characterized by having.

  With such a configuration, a semiconductor nonvolatile memory device having a fine channel width can be formed in the element isolation region.

  After the region forming step, there may be provided an impurity concentration changing step of changing the impurity concentration of the channel region by implanting predetermined impurity ions into the channel region.

  With such a configuration, the threshold voltage of the semiconductor nonvolatile memory device of the present invention can be arbitrarily adjusted.

  In order to achieve the above object, the semiconductor nonvolatile memory device of the present invention employs the following configuration.

A semiconductor nonvolatile memory device having a source region, a channel region, and a drain region in a semiconductor substrate, a memory insulating film on the semiconductor substrate above the channel region, and a memory gate electrode on the memory insulating film,
A set of thin film structures having sidewalls on the vertical end surfaces of the semiconductor substrate above the channel region are provided at predetermined intervals,
In the pair of thin film structures, the facing direction thereof matches the channel width direction of the channel region,
The channel width is narrower than the interval, and is characterized by being equal to or wider than the distance between the sidewalls facing the interval.

  With such a configuration, the area efficiency of the semiconductor nonvolatile memory device is improved.

An element isolation film is provided on the surface of the semiconductor substrate,
A thin film structure may be provided above the element isolation film, and the channel region may be provided below the element isolation film.

  With such a configuration, the area efficiency of the semiconductor nonvolatile memory device provided in the element isolation region is improved.

  According to the present invention, a semiconductor nonvolatile memory device having a channel width smaller than the pattern resolution limit of a photolithography process using vacuum ultraviolet light as an exposure light source can be formed. For this reason, fine semiconductor nonvolatile memory devices that could not be realized by the prior art can be formed without variation.

It is a figure explaining the outline | summary of this invention, Comprising: It is sectional drawing explaining the mode of a cross section in order of the manufacturing method. It is a figure which shows the manufacturing method of the semiconductor non-volatile device in the 1st Embodiment of this invention, and is a flowchart which shows the process which comprises a manufacturing method in order. It is sectional drawing which shows the structure formation process in the 1st Embodiment of this invention. It is sectional drawing which shows the insulating film formation process in the 1st Embodiment of this invention. It is sectional drawing which shows the etch-back process in the 1st Embodiment of this invention. It is sectional drawing which shows the memory insulating film formation process in the 1st Embodiment of this invention. It is sectional drawing which shows the memory gate electrode formation process in the 1st Embodiment of this invention. It is sectional drawing which shows the area | region formation process in the 1st Embodiment of this invention. It is sectional drawing which shows the wiring formation process in the 1st Embodiment of this invention. It is sectional drawing explaining the detail of the insulating film formation process in the 1st Embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor non-volatile memory device in the 2nd Embodiment of this invention, and is a flowchart which shows the process which comprises a manufacturing method in order. It is sectional drawing which shows the exposure process in the 2nd Embodiment of this invention. 1 is a plan view showing a structure of a semiconductor nonvolatile memory device according to a manufacturing method of a semiconductor nonvolatile memory device according to a first embodiment of the present invention, in which a thin film structure is used as a gate electrode of an address transistor of a memory cell. 11 is a plan view showing a structure of a semiconductor nonvolatile memory device according to a method for manufacturing a semiconductor nonvolatile memory device according to a second embodiment of the present invention, in which a thin film structure is a load resistor connected to a source region of a MONOS type memory transistor. It is. It is a figure which shows the manufacturing method of the semiconductor non-volatile memory device known conventionally, and is sectional drawing explaining the process of forming a MONOS type | mold memory transistor using the LOCOS method.

A method for manufacturing a semiconductor nonvolatile memory device and a semiconductor nonvolatile memory device according to the present invention utilize voids that are generated when an insulating film that later becomes a sidewall of a thin film structure is formed in a space between a pair of thin film structures. Then, a semiconductor nonvolatile memory device having a channel width finer than the pattern resolution limit of the photolithography process using vacuum ultraviolet light as an exposure light source is formed.
A major feature is that the distance between the element regions corresponding to the channel width is not determined by a predetermined pattern formed by patterning, but a gap generated when another film is formed is used.

  First, features of the semiconductor nonvolatile memory device of the present invention will be described. Next, the manufacturing method will be described in detail as Example 1, and the structure will be described in detail as Example 2.

Hereinafter, the features of the present invention will be described with reference to FIG.
FIG. 1 is a cross-sectional view showing the manufacturing method of the present invention in the order of steps, and is a diagram schematically showing a configuration unnecessary for explanation. This cross-sectional view is a diagram in which a part of the semiconductor nonvolatile memory device is cut, and shows a direction (channel length direction) in which a current flows between the front side and the back side of the drawing. . That is, FIG. 15 is a view illustrating a cross section when a current flows between a source region and a drain region, that is, a structure in which a current flows in a channel length direction, and is cut in a channel width direction, and is a diagram illustrating a conventional technique. FIG.

1A is a structure forming process, FIG. 1B is an insulating film forming process, FIG. 1C is an etch back process, FIG. 1D is a memory insulating film forming process, and FIG. FIG. 1E shows a memory gate electrode forming step, and FIG. 1F shows a region forming step.
Reference numeral 1 denotes a semiconductor substrate, 2a denotes a thin film structure, and 4 denotes an insulating film. 4a and 4b are side walls formed by etching back the insulating film 4. Reference numeral 5 denotes a gap, 6 denotes a channel region, 7 denotes a memory insulating film, 8a denotes a memory gate electrode, and 9a denotes a diffusion region which is a source region and a drain region.

First, as shown in FIG. 1A, for example, a pair of thin film structures 2a are formed oppositely on a semiconductor substrate 1 made of silicon having a P-type conductivity. The thin film structure 2a is made of, for example, polycrystalline silicon.
The distance W0 at which the thin film structures 2a face each other is equal to or close to the pattern resolution limit of the photolithography process using vacuum ultraviolet light as an exposure light source. For example, if the thickness of the thin film structure 2a is about 350 nm, it is about 450 nm.

  If this distance is narrower than the pattern resolution limit of the photolithography process, the thin film structure 2a itself cannot be formed correctly. Of course, it may be slightly widened in view of processing errors and the like, but the slightly widened distance varies depending on the performance of the exposure apparatus used, the material of the thin film structure 2a, and the material of the insulating film described later. It is difficult to express numerically. For this reason, it is advisable to determine the distance in advance through experiments or the like.

  Next, as shown in FIG. 1B, the insulating film 4 is formed with a predetermined thickness. This formation is performed by a known chemical vapor deposition method. This technique is hereinafter referred to as a CVD (Chemical-Vapor-Deposition) method. The insulating film 4 is formed of, for example, a silicon oxide film.

The pair of thin film structures 2a are opposed to each other at a distance W0 that matches or is close to the pattern resolution limit of the photolithography process using vacuum ultraviolet light as an exposure light source. A gap 5 without the insulating film 4 is formed in the interval between the structures 2a.
This is because the insulating film 4 is formed so that the vicinity of the upper end portions of the thin film structure 2a are stretched and connected to each other before the insulating film 4 is formed on the side wall of the thin film structure 2a with a sufficient film thickness. This is because a lid is placed on the space between the bodies 2a. As a result, the gap 5 is formed.

  Such a gap 5 can be formed because the thin film structure 2a is formed opposite to the pattern resolution limit of the photolithography process or at a distance W0 close thereto. The formation of the void 5 will be described later in more detail.

Next, as shown in FIG. 1C, the insulating film 4 is etched back (also referred to as etching back) to form side walls 4a and 4b on the side walls of the thin film structure 2a.
The insulating film 4 is removed by etching in the direction of the semiconductor substrate 1 to expose the gap 5, and the thin film structure 2 a
The insulating film 4 is left as a sidewall on the vertical end face of the thin film structure 2a facing the gap.

  As for the side wall, the side where the thin film structures 2a oppose each other is 4a, and the side which does not oppose is 4b. The side wall 4a on the side facing the thin film structure 2a has a smaller planar film thickness than the side wall 4b on the side not facing due to the presence of the gap 5, and the side walls 4a face each other with a distance W apart. The distance W at which the sidewalls 4a face each other is smaller than the pattern resolution limit of the photolithography process using vacuum ultraviolet light as the exposure light source (distance W0> distance W in the example of FIG. 1).

  This is the feature of the present invention. In forming the insulating film 4, the gaps 5 are intentionally provided in the space between the opposing thin film structures 2a, so that the side walls 4a have a size smaller than the pattern resolution limit of the photolithography process using vacuum ultraviolet light as an exposure light source. The distance W corresponds to the channel width of the channel region 6 of the semiconductor nonvolatile memory device formed by the manufacturing method of the present invention.

Next, as shown in FIG. 1D, a memory insulating film 7 is formed on the channel region 6 so as to cover the sidewalls 4a and the thin film structure 2a.
The memory insulating film 7 is, for example, a so-called ONO structure in which a first insulating film that is a silicon oxide film, a charge storage layer, and a second insulating film that is a silicon oxide film are stacked from the semiconductor substrate 1 side. This is a laminated film. Although not shown, the film is processed by a photolithography process using a predetermined photomask and an etching process after film formation, resulting in the structure shown in FIG.

  Thereafter, as shown in FIG. 1E, a memory gate electrode 8 a made of, for example, polycrystalline silicon is formed on the memory insulating film 7. The polycrystalline silicon film is formed by, for example, a known CVD method and is processed by a photolithography process and an etching process using a predetermined photomask after the film formation, which is not shown, and has a structure shown in FIG.

  Further, as shown in FIG. 1 (f), an impurity is added to the semiconductor substrate 1 by an ion implantation method, and an annealing process is performed in an inert gas atmosphere to electrically activate the impurity. A diffusion region 9a corresponding to the drain region is formed.

In the ion implantation process shown in FIG. 1 (f), the distance W, which is the distance between the opposing sidewalls 4a used as a mask, is a fine dimension that could not be realized by a photolithography process using vacuum ultraviolet light as an exposure light source. Therefore, the channel region 6 can be formed more finely than in the past.
As already described, FIG. 1 shows a direction in which a current flows between the front side and the back side of the drawing. Therefore, as the width of the channel region 6 (the horizontal direction in the drawing) becomes narrower, the semiconductor nonvolatile The memory device can be miniaturized.

Since the sidewall and the thin film structure are elements necessary for forming a semiconductor nonvolatile memory device having a narrow channel width, the sidewall and the thin film structure may be removed after forming the diffusion region 9a as much as possible. However, these can also be used as wiring.
For example, when the thin film structure 2a is made of polycrystalline silicon having an N conductivity type, the thin film structure 2a can also function as a wiring or a gate electrode of a transistor. For example, it can be used as a gate electrode of an address transistor or a read load transistor. In this case, it is necessary to ensure sufficient insulation between the semiconductor substrate and the thin film structure and between the memory gate electrode and the thin film structure, and an insulating film such as a silicon oxide film is provided at the interface.

  Hereinafter, the manufacturing method of the present invention will be described in detail as Example 1 with reference to the drawings. In the description, a case where a MONOS type memory transistor having a conductivity type N is formed as a semiconductor nonvolatile memory device on the surface of the semiconductor substrate 1 having a conductivity type P will be described as an example. The cross-sectional view used for the description is a cross-sectional view in the same direction as FIG.

[Detailed Description of First Embodiment of Manufacturing Method; FIGS. 2 to 10]
The first embodiment is a manufacturing method for forming a set of thin film structures 2a directly on a semiconductor substrate.
Hereinafter, a method for manufacturing the semiconductor nonvolatile memory device according to the first embodiment will be described with reference to FIGS.
FIG. 2 is a flowchart of the manufacturing method shown in the order of steps constituting the outline of the first embodiment. 3 to 10 are cross-sectional views for explaining in detail the steps constituting the flowchart shown in FIG. 2, and are diagrams schematically showing the steps in the same manner as in FIG. FIG. 10 is a diagram for explaining how the air gap is formed.

  The flow chart of the manufacturing method shown in FIG. 2 includes a structure forming process P10, an insulating film forming process P20, an etch back process P30, a memory insulating film forming process P40, a memory gate electrode forming process P50, a region forming process P60, and a wiring forming process P01. It shows the flow. Each manufacturing process will be described with reference to FIGS.

  Further, in FIGS. 3 to 10, the reference numeral 1 denotes a semiconductor substrate, and 2 denotes a first polycrystalline silicon film. Reference numeral 2a denotes a thin film structure, which is formed by processing the first polycrystalline silicon film 2. 3 represents a photoresist pattern, and 4 represents an insulating film. Reference numerals 4a and 4b denote sidewalls formed on the vertical end surface of the thin film structure 2a by etching back the insulating film 4. Reference numeral 5 denotes a gap, and 6 denotes a channel region. Reference numeral 7 denotes a memory insulating film, which is a laminated structure including a first insulating film 7a that is a silicon oxide film, a second insulating film 7b that is a charge storage layer, and a third insulating film 7c that is a silicon oxide film. Have Reference numeral 8 denotes a second polycrystalline silicon film, and 8a denotes a memory gate electrode formed by processing the second polycrystalline silicon film. Reference numeral 9 denotes an impurity, and 9a denotes a diffusion region formed by activating the impurity 9. Reference numeral 10 denotes an interlayer insulating film, 11 denotes a contact hole, and 12 denotes a metal wiring.

[Description of Structure Forming Step P10: FIGS. 2 and 3]
First, the structure forming step P10 will be described with reference to FIGS. This manufacturing process is a process of forming a set of thin film structures having a predetermined interval.

First, as shown in FIG. 3A, a first polycrystalline silicon film 2 is formed on a semiconductor substrate 1. The first polycrystalline silicon film 2 is formed with a thickness of 350 nm by a CVD method using monosilane (SiH ₄ ) as a reaction gas.
Next, a photoresist is coated on the first polycrystalline silicon film 2 by a known spin coating method. Thereafter, a predetermined photoresist mask is used to expose and develop the photoresist into a predetermined shape using a known photolithography technique, and a set of photoresist patterns is formed on a predetermined portion of the first polycrystalline silicon film 2. 3 is formed.

  The distance between the pair of photoresist patterns 3 is equal to or close to the pattern resolution limit of the photolithography process using vacuum ultraviolet light as an exposure light source, and is, for example, about 450 nm.

Next, as shown in FIG. 3B, the first polycrystalline silicon film is formed by dry etching using the photoresist pattern 3 as an etching resistant mask and using chlorine (Cl ₂ ) and hydrogen bromide (HBr) as reaction gases. 2 is processed.
Since the photoresist patterns 3 are opposed to each other with an interval of about 450 nm, the interval between the pair of thin film structures 3a processed by dry etching with high selectivity to the photoresist pattern 3 is also about 450 nm. Since this distance is the distance W0 in FIG. 1, this is also shown in FIG.

By the way, the aspect ratio (the ratio between the film thickness and the interval of the thin film structure 2a and the value obtained by dividing the film thickness by the interval) of the interval between the pair of thin film structures 2a is about 0.78.
Although not shown, the photoresist pattern 3 is removed thereafter.

[Description of Insulating Film Forming Step P20: FIGS. 2, 4, and 10]
Next, the insulating film forming step P20 will be described with reference to FIGS. This manufacturing process is a process of covering the thin film structure and forming an insulating film so as to provide a gap between the pair of thin film structures.

As shown in FIG. 4, the insulating film 4 which is a silicon oxide film is covered with a film thickness of 300 nm so as to cover the thin film structure 2a by a CVD method using monosilane (SiH ₄ ) and oxygen (O ₂ ) as reaction gases. To form. At this time, gaps 5 are formed at intervals between the pair of thin film structures 2a.
According to the inventors, when the film thickness of the thin film structure 2a is 350 nm, it has been confirmed that voids are formed with an aspect ratio of 0.7 or more.

The process of forming the gap 5 will be described in detail with reference to FIG.
FIG. 10 is a cross-sectional view showing in detail the process of forming a gap in the space between the pair of thin film structures 2a while simultaneously covering the pair of thin film structures 2a with the insulating film 4. FIG. It is illustrated in the order from (a) to FIG. 10 (e).

  As shown in FIG. 10A, a set of thin film structures 2 a are formed on the surface of the semiconductor substrate 1 so as to face each other. The film thickness is about 350 nm, and the distance between the distances is about 450 nm.

  FIG. 10B shows an initial process of forming the insulating film 4 in a state where a film thickness of about 50 nm is formed. Since the distance between the thin film structures 2a facing each other is narrow, it is difficult for a precursor for forming the insulating film 4 to enter, and the insulating film 4 can be uniformly formed on the surface of the semiconductor substrate 1 that is positioned in a plane. First, more insulating films 4 are formed at the upper end (upper corner) of the thin film structure 2a.

  FIG. 10C shows a state in which the insulating film 4 is formed with a film thickness of about 150 nm. In the opposing space of the thin film structure 2a, the film thickness difference between the vertical end surface of the thin film structure 2a, the surface of the semiconductor substrate 1, and the upper end portion gradually increases. At the upper end portion of the thin film structure 2a, the insulating film 4 starts to protrude in the interval direction of the thin film structure 2a like a ridge.

  FIG. 10D shows a state in which the insulating film 4 is formed with a film thickness of about 250 nm. It shows a state in which the insulating films 4 at the upper end portions of the thin film structure 2a that are opposed to each other grow and are in contact with each other. Since it is such a shape, the precursor for forming the insulating film 4 does not enter the space between the thin film structures 2a. Therefore, the increase in film thickness due to the deposition of the insulating film 4 on the vertical end surface of the thin film structure 2a and the surface of the semiconductor substrate 1 is stopped.

FIG. 10E shows a final state in which the insulating film 4 is formed with a film thickness of about 300 nm. After the gap 5 is formed in the opposing space of the thin film structure 2a, the insulating film 4 is deposited thicker above the gap. In the region where the thin film structures 2a face each other, as shown in FIG. 10 (d), the film deposition almost stops when the film thickness of the insulating film 4 exceeds 250 nm. The film thickness of the insulating film 4 deposited on the vertical end face 2a is asymmetric between the opposite side and the opposite side.

  As described above, following this process, the gap 5 without the insulating film 4 is formed in the interval between the thin film structures 2a. The gap 5 can be formed with high accuracy if the distance between the pair of thin film structures 2a is determined. Although it is an example, the width | variety (drawing left-right direction) of this space | gap 5 is 150 nm.

[Description of Etchback Process P30: FIGS. 2 and 5]
Next, the etch-back process P30 will be described with reference to FIGS. In this manufacturing process, the insulating film 4 is etched away in the direction of the semiconductor substrate 1 to expose the gap 5, and the insulating film 4 is left as the side walls 4a and 4b on the vertical end surface of the thin film structure 2a facing the space and the thin film structure is formed. This is a step of exposing the surface of the semiconductor substrate 1 positioned in a plane at the interval between the bodies 2a.

The insulating film 4 is etched in the vertical direction until the surface of the semiconductor substrate 1 is exposed by dry etching using trifluoride methane (CHF ₃ ) and tetrafluoromethane (CF ₄ ) as reaction gases.
The thickness of the insulating film 4 in the vertical direction differs between the surface of the semiconductor substrate 1 and the upper surface of the thin film structure 2a and the vertical end surface of the thin film structure 2a. It becomes thicker by the film thickness. Therefore, when the insulating film 4 is etched in the vertical direction by dry etching, the insulating film 4 remains on the vertical end surface of the thin film structure 2a, and the sidewalls 4a and 4b are formed.

Since the film thickness deposited on the vertical end surface of the pair of thin film structures 2a of the insulating film 4 formed in the insulating film forming step P20 is asymmetric on the opposite side and the opposite side, The thickness of the sidewall made of the insulating film 4 formed on the vertical end surface of the thin film structure 2a is asymmetric between the opposite side and the opposite side. Reference numeral 4a indicates the opposite side wall, and reference numeral 4b indicates the opposite side wall.
As an example, the approximate film thickness of the sidewall 4a is 150 nm, and the approximate film thickness of the sidewall 4b is 250 nm.

The semiconductor substrate 1 that is positioned in a plane at an interval between the pair of thin film structures 2a is exposed with a width of about 150 nm. This exposed region is an element region, and a channel region 6 is a region where a memory insulating film and a memory gate electrode, which will be formed in a later step, are planarly located. The exposed width of about 150 nm of the semiconductor substrate 1 that is positioned in a plane at a distance between the pair of thin film structures 2a is the channel width of the MONOS memory transistor. The width of 150 nm is a size smaller than the pattern resolution limit of the photolithography technique using vacuum ultraviolet light as an exposure light source.
That is, the exposed width of the surface of the semiconductor substrate 1 positioned in a plane at the interval between the pair of thin film structures 2 a coincides with the width of the gap 5. Since the gap 5 is not formed by patterning using the photolithography technique, the surface of the semiconductor substrate 1 can be exposed with such a minimum dimension.

[Description of Memory Insulating Film Forming Step P40: FIGS. 2 and 6]
Next, the memory insulating film formation process P40 will be described with reference to FIGS. This manufacturing process is a process of forming a memory insulating film on the surface of the semiconductor substrate 1 exposed by the etch-back process P30.

First, as shown in FIG. 6A, a first insulating film 7a made of a silicon oxide film is formed to a thickness of 2 nm on the entire surface of the semiconductor substrate 1 by performing a treatment at 900 ° C. in an oxygen atmosphere.
Next, a silicon nitride film as a charge storage layer is formed as a second insulating film 7b on the first insulating film 7a by a CVD method using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reaction gases. It is formed with a film thickness of 10 nm.
Thereafter, the second insulating film 7b is oxidized by processing at 1000 ° C. in a water vapor atmosphere, and a third insulating film 7c, which is a silicon oxide film, is formed to a thickness of 3 nm.
The memory insulating film 7 of the MONOS memory transistor is a film having a structure in which the first insulating film 7a, the second insulating film 7b, and the third insulating film 7c are sequentially stacked.

  Thereafter, a photoresist is coated on the memory insulating film 7 by a known spin coating method. Thereafter, a photoresist pattern 3 is formed on a predetermined portion of the upper portion of the memory insulating film 7 by exposing and developing the photoresist into a predetermined shape using a known photolithography technique using a predetermined photomask.

Next, as shown in FIG. 6B, using the photoresist pattern 3 as an etching resistant mask, the third insulating film 7c is removed with a hydrogen fluoride (HF) solution, and then the second insulating film 7b is removed. Removal is performed by dry etching using sulfur hexafluoride (SF ₆ ) as a reaction gas. Further, the first insulating film 7a is removed with a hydrogen fluoride (HF) solution. Thereafter, although not shown, the photoresist pattern 3 is removed.

[Description of Memory Gate Electrode Formation Step P50: FIGS. 2 and 7]
Next, the memory gate electrode formation step P50 will be described with reference to FIGS. This manufacturing process is a process of forming a memory gate electrode on the memory insulating film formed in the memory insulating film forming process.

First, as shown in FIG. 7A, a second polycrystalline silicon film 8 is formed on the semiconductor substrate 1. The second polycrystalline silicon film 8 is formed with a thickness of 350 nm by a CVD method using monosilane (SiH ₄ ) as a reaction gas.
Next, a photoresist is coated on the second polycrystalline silicon film 8 by a known spin coating method. Thereafter, a photoresist pattern 3 is formed on a predetermined portion of the second polycrystalline silicon film 8 by exposing and developing the photoresist into a predetermined shape using a known photolithography technique using a predetermined photomask. To do.

Next, as shown in FIG. 7B, the second polycrystalline silicon film is formed by dry etching using the photoresist pattern 3 as an etching resistant mask and using chlorine (Cl ₂ ) and hydrogen bromide (HBr) as reaction gases. 8 is processed to form a memory gate electrode 8a. Thereafter, although not shown, the photoresist pattern 3 is removed.

[Description of Region Formation Step P60: FIGS. 2 and 8]
Next, the region forming step P60 will be described with reference to FIGS. This manufacturing process is a process in which predetermined impurity ions are implanted into the semiconductor substrate to form diffusion regions which are a source region and a drain region.

  First, as shown in FIG. 8A, arsenic (As) as an N-type impurity 9 is added to the entire surface of the semiconductor substrate 1 exposed by ion implantation, as shown in FIG. By the way, in this ion implantation, the impurity 9 is also added to the memory gate electrode 8a.

  Next, as shown in FIG. 8 (b), arsenic (As), which is an impurity 9 implanted, is electrically activated by performing an annealing process at a temperature of 900 ° C. in a nitrogen atmosphere, so that the MONOS memory transistor is activated. A diffusion region 9a which is a source region and a drain region is formed. At this time, the impurity 9 added to the memory gate electrode 8a is also electrically activated, and the memory gate electrode 8a can function as an N-type electrode.

[Description of Wiring Formation Step P01: FIGS. 2 and 9]
Next, the wiring formation process P01 will be described with reference to FIGS. This manufacturing process is a process of forming a metal wiring for applying a voltage to an arbitrary portion of the MONOS type memory transistor.

First, as shown in FIG. 9, an interlayer insulating film 10 made of a silicon oxide film is formed on the entire upper surface of the semiconductor substrate 1 by a CVD method using monosilane (SiH ₄ ) and oxygen (O ₂ ) as reaction gases, for example. It is formed with a film thickness of 600 nm.

  Next, a contact hole 11 for connecting the memory gate electrode 8a to the metal wiring is formed in a predetermined region of the interlayer insulating film 10 by using a known photolithography process and etching process. Thereafter, a metal wiring 12 made of an aluminum material connected to the memory gate electrode 8a is formed through the contact hole 11, thereby completing a MONOS type memory transistor which is a semiconductor nonvolatile memory device of the present invention.

  Since such a metal wiring forming process is already known, detailed description thereof is omitted. Furthermore, although the metal wiring 12 is connected to the diffusion region 9a which is the source region and the drain region, the metal wiring 12 is manufactured in the same manner as the metal wiring 12 connected to the memory gate electrode 8a.

  As shown in FIG. 9, the distance W1 is a distance at which the thin film structures 2a face each other. The distance is equal to or close to the pattern resolution limit of the photolithography process using vacuum ultraviolet light. In this example, it is about 450 nm. The distance W2 is a distance where the sidewalls 4a face each other, and is the width of the gap 5 already described. In this example, it is about 150 nm as already described, and corresponds to the channel width of the MONOS type memory transistor which is the semiconductor nonvolatile memory device of the present invention.

  As described above, in the manufacturing method of the first embodiment described above, the channel region 6 is the semiconductor substrate 1 having the conductivity type of P type. However, even if an impurity for controlling the threshold voltage is added to the channel region 6, the same applies. An effect is obtained.

[Detailed Description of Second Embodiment of Manufacturing Method: FIGS. 11 and 12]
Next, a second embodiment of the semiconductor device manufacturing method will be described.
In the second embodiment, a set of thin film structures 2a is formed on an element isolation film. In the first embodiment already described, the thin film structure 2a is provided directly on the semiconductor substrate 1, but the point is different.

  That is, in the manufacturing method of the first embodiment, an element isolation step for forming an element isolation film before the structure forming step P10, and an etch back step P30, after which the thin film structure 2a and the sidewalls 4a and 4b are used as masks. This is a manufacturing method in which an element isolation film having an interval between the thin film structures 2a is removed by etching to expose the surface of the semiconductor substrate 1. By adopting such a manufacturing method, a semiconductor nonvolatile memory device having a channel width smaller than the pattern resolution limit of the photolithography technique using vacuum ultraviolet light can be formed even in the element isolation film 13 region.

Hereinafter, the manufacturing method of 2nd Embodiment is demonstrated using FIG. 11 and FIG.
FIG. 11 is a flowchart of the manufacturing method shown in the order of steps constituting the outline of the second embodiment of the present invention. The flowchart of the manufacturing method shown in FIG. 11 is obtained by adding an element isolation step P100 and an exposure step 200 to the flowchart showing the manufacturing method of the first embodiment shown in FIG. The same number is assigned to the same configuration as that of the first embodiment already described.

  FIG. 12 is a cross-sectional view showing the manufacturing method of the second embodiment, and is a cross-sectional view for explaining the exposure step 200 in more detail than the steps constituting the flowchart shown in FIG. Reference numerals 13 indicate an element isolation film, and 14 indicates a groove. Further, in FIG. 12, portions not related to the description such as the interlayer insulating film 10 are omitted for easy understanding of the drawing.

  In the second embodiment shown in FIG. 11, first, an element isolation film 13 is formed in a predetermined region of the semiconductor substrate 1 in an element isolation step P100. In the element isolation process P100, a region surrounded by the element isolation film 13 is formed as an element region. In the second embodiment, a semiconductor nonvolatile memory device is formed in the area where the element isolation film 13 is formed. Therefore, the element region is not particularly described in FIG. Thereafter, in the structure forming step P <b> 10, the thin film structure 2 a is formed on the element isolation film 13.

  Further, the details of the steps relating to the insulating film forming step P20, the etch back step P30, the memory insulating film forming step P40, the memory gate electrode forming step P50, and the region forming step P60 are the same, but the place where the thin film structure 2a is provided Is the upper part of the element isolation film 13, and therefore the exposure process P200 is performed.

As shown in FIG. 12, the element isolation film 13 that is positioned in a plane at an opposing interval between a pair of thin film structures 2 a provided on the element isolation film 13 formed in the element isolation process 100 is connected to the thin film structure 2 a. Until the surface of the semiconductor substrate 1 is exposed in the vertical direction by dry etching using the sidewall 4a as an etching resistant mask and using trifluoride methane (CHF ₃ ) and tetrafluoromethane (CF ₄ ) as reaction gases. Etch.
The element isolation film 13 is a silicon oxide film having a thickness of, for example, 500 nm, which is provided by oxidizing the semiconductor substrate 1 made of silicon at a temperature of about 1000 ° C. in a water vapor atmosphere.

  A vertical groove 14 in which the semiconductor substrate 1 is exposed with a width of about 150 nm is formed in the element isolation film 13 which is positioned in a plane at a distance between the pair of thin film structures 2a. The width of the vertical groove 14 is the channel width of the MONOS type memory transistor, and the width of 150 nm is smaller than the pattern resolution limit of the photolithography technique using vacuum ultraviolet light as an exposure light source.

  By the way, as already explained, an example of the width of the gap 5 is 150 nm, and an example of the width of the sidewall 4a is also 150 nm. Then, in FIG. 12, it seems that there is a difference between the width of the groove 14 generated by the gap 5 and the width of the sidewall 4a, but this is a result expressed in order to make the drawing easier to see. The same applies to other drawings.

  Thereafter, although not shown, the semiconductor device is completed through a memory insulating film formation step P40, a memory gate electrode formation step P50, a region formation step P60, and a wiring formation step P01.

  Even in the manufacturing method of the second embodiment described above, the thin film structure 2a and the sidewalls 4a and 4b can be removed by a known method if unnecessary, as in the manufacturing method of the first embodiment. Good.

  As described above, also in the manufacturing method of the second embodiment described above, the channel region 6 is the semiconductor substrate 1 having a conductivity type of P type, but the threshold voltage is controlled in the channel region 6 as in the manufacturing method of the first embodiment. The same effect can be obtained even if an impurity is added.

  Hereinafter, the structure of the semiconductor nonvolatile memory device of the present invention will be described in detail as a second embodiment with reference to the drawings. The same numbers are assigned to the configurations already described.

[Semiconductor Nonvolatile Memory Device Formed by Manufacturing Method of First Embodiment: FIGS. 9 and 13]
Details of the structure of the semiconductor nonvolatile memory device formed by the manufacturing method of the first embodiment described above will be described with reference to FIGS. The manufacturing method of the first embodiment is a manufacturing method for forming a set of thin film structures on a semiconductor substrate.

The structure to be described is an example in which one of the thin film structures 2a is used as a gate electrode of an address transistor constituting a memory cell, and a memory cell and a MONOS memory transistor sharing a drain region are constituted.
The address transistor is an N-type (so-called N-channel type) MOS transistor (hereinafter referred to as an N-type MOS transistor).

FIG. 13 is a plan view of the semiconductor nonvolatile memory device formed by the manufacturing method described above, and the cross-sectional view located at the broken line AA ′ shows the method for manufacturing the semiconductor nonvolatile memory device of the first embodiment. 9 corresponds to FIG. 9, which is a cross-sectional view of the semiconductor nonvolatile memory device completed by.
In FIG. 13, reference numeral 2aa is one of a set of thin film structures 2a shown in FIG. 9, and functions as a gate electrode of an N-channel transistor. Reference numerals 9a1 and 9a2 denote diffusion regions shown in FIG. 9, and 9a1 denotes a drain region shared by the MONOS type memory transistor and the address transistor. Reference numeral 9a2 denotes a source region.

As shown in FIG. 9 and FIG. 13, the formed memory cell has a pair of thin film structures 2a provided on the semiconductor substrate 1 apart from each other, and vacuum ultraviolet light as an exposure light source provided at an opposing interval between the thin film structures 2a. The MONOS type memory transistor has a channel width finer than the pattern resolution limit, and an address transistor provided in common with a diffusion region which is a drain region of the MONOS type memory transistor.
In particular, the thin film structure 2aa is made of polycrystalline silicon having an N conductivity type, and functions as a gate electrode of the address transistor. In this case, although not shown in FIG. 9, a silicon oxide film functioning as a gate insulating film exists between the semiconductor substrate 1 and the thin film structure 2a.

  By the manufacturing method already described, the diffusion region 9a is implanted with arsenic (As), which is an N-type impurity in the ion implantation process, so that the conductivity type is N-type. At this time, since impurities are also ion-implanted into the thin film structure 2a, the thin film structure 2a also has an N conductivity type and can function as a gate electrode of an N type MOS transistor that is an address transistor.

  As shown in FIG. 13, the contact hole 11 is provided on the surface of the memory gate electrode 8a, the thin film structure 2aa functioning as the gate electrode of the address transistor, the diffusion region 9a2 which is the source region of each of the MONOS type memory transistor and the address transistor, The structure is connected to the metal wiring 12 for applying a voltage to each location via the contact hole 11.

  In the MONOS type memory transistor that is the semiconductor nonvolatile memory device described above, the channel width is smaller than the pattern resolution limit of the photolithography technique using vacuum ultraviolet light as the exposure light source. Further, structurally, the beak-like insulating film portion described in the prior art does not exist at the end of the channel region. Therefore, stable characteristics can be realized.

[Semiconductor Nonvolatile Memory Device Formed by Manufacturing Method of Second Embodiment: FIG. 14]
Details of the structure of the semiconductor nonvolatile memory device formed by the manufacturing method of the second embodiment already described will be described with reference to FIG. The manufacturing method of the second embodiment is a manufacturing method in which a set of thin film structures is formed on an element isolation film.
The structure is an example in which one of the thin film structures 2a is used as a load resistance of a MONOS type memory transistor and is connected to a diffusion region which is a source region, thereby improving the charge injection efficiency at the time of memory writing. It is.

FIG. 14 is a plan view of a semiconductor nonvolatile memory device formed by the manufacturing method already described, and a cross-sectional view located at a broken line BB ′ is a semiconductor nonvolatile memory completed by the manufacturing method of the second embodiment. This corresponds to the cross section of the sexual memory device. Therefore, the configuration shown in FIG. 14 is provided on the element isolation film 13.
In FIG. 14, reference numeral 2ab is one of a set of thin film structures 2a and functions as a load resistance. Reference numerals 9a3 and 9a4 are diffusion regions, 9a3 is a diffusion region which is a source region of the MONOS type memory transistor, and 9a4 is a diffusion region which is a drain region.

  As shown in FIG. 14, the formed semiconductor nonvolatile memory device is a vacuum ultraviolet ray as an exposure light source provided at a distance between a pair of thin film structures 2a provided on the element isolation film 13 and the thin film structures 2a facing each other. This is a structure comprising a MONOS memory transistor having a channel width finer than the light pattern resolution limit and a load resistor connected to the source region of the MONOS memory transistor. In particular, the thin film structure 2ab is characterized in that it is used as a load resistance by being formed of polycrystalline silicon whose conductivity type is P type.

  In the manufacturing method already described, in order to set the conductivity type of the thin film structure to P type, polycrystalline silicon having the conductivity type of P type is used as the material of the thin film structure in the thin film structure forming step. Since arsenic (As), which is an N-type impurity, is implanted in the ion implantation process, the arsenic (As) impurity concentration is canceled in order for the thin film structure to function as a P-type load resistor. It is important to have a P-type impurity concentration sufficient.

  As shown in FIG. 14, the contact hole 11 is provided on the surface of the memory gate electrode 8a, the thin film structure 2ab functioning as a load resistance, and the diffusion regions 9a3 and 9a4 which are the source region and the drain region of the MONOS type memory transistor. 11 is connected to a metal wiring 12 for applying a voltage to each location via 11.

  The present invention can form a semiconductor non-volatile memory device that is fine and has stable electric characteristics, and is therefore suitable for a memory device for electronic equipment that is required to have high integration and low power consumption.

DESCRIPTION OF SYMBOLS 1,101 Semiconductor substrate 2,104 Element isolation film 2 1st polycrystalline silicon film 2a Thin film structure
3 Photoresist pattern 4 Insulating film 4a, 4b Side wall
5 Gaps 6 Channel region 7, 106 Memory insulating film 7a First insulating film 7b Second insulating film 7c Third insulating film 8 Second polycrystalline silicon film 8a, 107 Memory gate electrode 9 Impurity 9a Diffusion region 10 Interlayer Insulating film 11 Contact hole 12 Metal wiring
13 Device isolation film 14 Groove 102 Pad oxide film 103 Anti-oxidation mask 105 Device region

Claims (5)

A method for manufacturing a semiconductor nonvolatile memory device, wherein a source region, a channel region, and a drain region are provided on a semiconductor substrate, a memory insulating film is provided on the semiconductor substrate above the channel region, and a memory gate electrode is provided on the memory insulating film Because
A structure forming step of forming a set of thin film structures at a predetermined interval on the semiconductor substrate above the portion for forming the channel region;
An insulating film forming step of covering the set of thin film structures and forming an insulating film so as to form a gap in the gap;
Etching back the insulating film in the direction of the semiconductor substrate to expose the air gap, and leaving the insulating film as a sidewall on the vertical end surface of the thin film structure facing the interval; and
Forming a memory insulating film on the semiconductor substrate at the interval;
A memory gate electrode forming step of forming a memory gate electrode on the memory insulating film;
A region forming step of implanting predetermined impurity ions into the semiconductor substrate using the thin film structure and the sidewalls and the memory gate electrode as a mask, thereby forming the source region, the channel region, and the drain region, respectively. ,
A method for manufacturing a semiconductor nonvolatile memory device, comprising: A method for manufacturing a semiconductor nonvolatile memory device, wherein a source region, a channel region, and a drain region are provided on a semiconductor substrate, a memory insulating film is provided on the semiconductor substrate above the channel region, and a memory gate electrode is provided on the memory insulating film Because
An element isolation step of forming an element isolation film on the surface of the semiconductor substrate;
A structure forming step of forming a set of thin film structures at a predetermined interval on the element isolation film above the portion forming the channel region;
An insulating film forming step of covering the set of thin film structures and forming an insulating film so as to form a gap in the gap;
Etching back the insulating film in the direction of the semiconductor substrate to expose the air gap, and leaving the insulating film as a sidewall on the vertical end surface of the thin film structure facing the interval; and
An exposure step of exposing the surface of the semiconductor substrate by etching away the element isolation film at the interval using the thin film structure and the sidewall as a mask;
Forming a memory insulating film on the semiconductor substrate at the interval;
A memory gate electrode forming step of forming a memory gate electrode on the memory insulating film;
A region forming step of implanting predetermined impurity ions into the semiconductor substrate using the thin film structure and the sidewalls and the memory gate electrode as a mask, thereby forming the source region, the channel region, and the drain region, respectively. ,
A method for manufacturing a semiconductor nonvolatile memory device, comprising:   3. The semiconductor nonvolatile semiconductor device according to claim 1, further comprising an impurity concentration changing step of changing the impurity concentration of the channel region by implanting predetermined impurity ions into the channel region after the region forming step. A method for manufacturing a storage device. A semiconductor nonvolatile memory device having a source region, a channel region, and a drain region on a semiconductor substrate, a memory insulating film on the semiconductor substrate above the channel region, and a memory gate electrode on the memory insulating film. ,
A set of thin film structures having sidewalls on the longitudinal end surfaces of the semiconductor substrate above the channel region are provided at predetermined intervals.
In the set of thin film structures, a facing direction thereof matches a channel width direction of the channel region,
2. The semiconductor nonvolatile memory device according to claim 1, wherein the channel width is narrower than the interval and equal to or wider than a distance between the sidewalls facing the interval. An element isolation film is provided on the surface of the semiconductor substrate,
5. The semiconductor nonvolatile memory device according to claim 4, wherein the thin film structure is provided above the element isolation film, and the channel region is provided below the element isolation film.

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