KR20040045099A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A TFT(Thin Film Transistor) substrate and a manufacturing method thereof are provided to be capable of simplifying the manufacturing process and reducing fabrication cost. CONSTITUTION: A TFT substrate is provided with an insulation substrate(110), a polycrystalline silicon layer(150) on the insulation substrate, a gate isolating layer(140) for enclosing the polycrystalline silicon layer, a gate electrode(123) on the gate isolating layer, an interlayer dielectric(601) for enclosing the gate electrode and an organic layer(602) on the interlayer dielectric. At this time, the polycrystalline silicon layer is made of a source and drain region(153,155), and a channel region(154) between the source and drain region. The TFT substrate further includes a pixel electrode(80) on the organic layer, and a source and drain electrode(173,175) on the organic layer and the pixel electrode for being connected with the source and drain region through the first and second contact hole(161,162). The pixel electrode is connected with the drain electrode.

Description

Thin film transistor substrate and manufacturing method thereof

The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and more particularly to a polycrystalline silicon thin film transistor substrate and a method for manufacturing the same.

A thin film transistor substrate (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor substrate includes a scan signal wire or a gate wire for transmitting a scan signal, an image signal line or a data wire for transmitting an image signal, and a thin film transistor and a thin film transistor connected to the gate wire and the data wire. And a pixel electrode, a gate insulating film covering and insulating the gate wiring, and an interlayer insulating film covering and insulating the thin film transistor and the data wiring.

The thin film transistor includes a semiconductor layer forming a gate electrode and a channel which are part of a gate wiring, a source electrode and a drain electrode which are part of a data wiring, a gate insulating film and an interlayer insulating film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

Such a thin film transistor has an amorphous silicon layer or a polycrystalline silicon layer as a semiconductor layer, and may be classified into a top gate method and a bottom gate method according to a relative position of the gate electrode and the semiconductor layer. In the case of a polycrystalline silicon thin film transistor substrate, a top gate method in which a gate electrode is located above the semiconductor layer is mainly used. In the top gate method, a polycrystalline silicon layer is formed on an insulating substrate, a gate insulating film is formed on the polycrystalline silicon layer, and a gate wiring and a sustain electrode line are formed on the gate insulating film.

In general, amorphous silicon (a-Si) or polycrystalline silicon (poly-Si) is used for the semiconductor layer. Amorphous silicon has relatively low electrical properties due to lack of regularity, whereas polycrystalline silicon has a fully ordered atomic structure, which has an advantage of more than 100 times faster than amorphous silicon.

However, such a polysilicon thin film transistor substrate and its manufacturing method have a more complicated process number than the amorphous silicon thin film transistor substrate and its manufacturing method, and therefore are not preferable in terms of yield and cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a thin film transistor substrate and a method of manufacturing the same.

1 is a layout view of a thin film transistor substrate for a transflective liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II 'and II'-II "of FIG. 1;

3A is a cross-sectional view illustrating the formation of a blocking layer and an amorphous silicon layer on an insulating substrate;

FIG. 3B is a sectional view showing the step of patterning an amorphous silicon layer as a next step of FIG. 3A;

FIG. 3C is a sectional view showing a step of forming a chromium layer pattern simultaneously with the gate electrode as a next step of FIG. 3B;

FIG. 3D is a sectional view showing the next step of FIG. 3C, further etching the sidewalls of the gate electrode; FIG.

3E is a sectional view showing a step of forming a lightly doped region as a next step of FIG. 3D;

FIG. 3F is a sectional view showing a step of forming an interlayer insulating film as a next step of FIG. 3E;

FIG. 3G is a sectional view showing a step of forming an organic film as a next step of FIG. 3F;

FIG. 3H is a sectional view showing a step of forming a transparent electrode as a next step of FIG. 3G.

<Description of the symbols for the main parts of the drawings>

121; Gate line 123; Gate electrode

140; A gate insulating film 150; Polycrystalline silicon layer

152; Lightly doped region 153; Source area

154; Channel region 155; Drain area

601; Interlayer insulating film 602; Organic membrane

The present invention to achieve the above object, the insulating substrate; A polycrystalline silicon layer formed on the insulating substrate and including a source region and a drain region and a channel region disposed between the source region and the drain region; A gate insulating film covering the polycrystalline silicon layer; A gate electrode formed on the gate insulating film; An interlayer insulating film covering the gate electrode; An organic film formed on the interlayer insulating film; A pixel electrode formed on the organic layer; A source electrode formed on the organic film and the pixel electrode and connected to the source region and the drain region through first and second contact holes penetrating the organic film, the interlayer insulating film, and the gate insulating film, respectively; And a drain electrode, wherein the drain electrode is connected to the pixel electrode.

In addition, the pixel electrode preferably comprises a reflective electrode having a transmission window and a transmission electrode.

In addition, the gate electrode is preferably formed of a double layer of a lower layer of AlNd and an upper layer of MoW.

The source electrode and the drain electrode are preferably formed of a double layer of a lower layer of MoW and an upper layer of AlNd.

Moreover, it is preferable that embossing is formed in the said organic film upper surface.

In addition, it is preferable that a gate external circuit portion pad for connecting an external signal to the gate driving circuit portion is formed on the gate insulating film.

In addition, a gate pad connecting the scan signal applied from the gate driving circuit unit to the gate electrode is preferably formed on the gate insulating film.

The gate pad and the gate external circuit pad may be formed of a double layer of a lower layer of AlNd and an upper layer of MoW.

In addition, it is preferable that a lightly doped region is further formed between the source region and the channel region and between the drain region and the channel region.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, the method comprising: forming an amorphous silicon layer on an insulating substrate; after crystallizing the amorphous silicon layer, patterning to form a polycrystalline silicon layer; Forming a gate insulating film on the polycrystalline silicon layer; Forming a gate electrode and a sustain electrode wiring on the gate insulating film; Forming a source region, a drain region, and a channel region not doped with impurities in the polycrystalline silicon layer; Forming an interlayer insulating film on the gate electrode and sustain electrode wiring; Forming a first contact hole exposing the source region and a second contact hole exposing the drain region in the interlayer insulating film and the gate insulating film; Forming an organic layer on the interlayer insulating layer to expose the first and second contact holes; Forming a pixel electrode on the organic layer; And forming a data line on the organic layer including a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole. Do.

The method may further include forming a transmissive electrode in the forming of the pixel electrode and simultaneously forming a reflective electrode in the forming of the data line. The forming of the channel region may further include forming a lightly doped region between the source region and the channel region and between the drain region and the channel region.

The forming of the lightly doped region may include forming a chromium layer pattern that matches the gate electrode; etching only a portion of a sidewall of the gate electrode so that the width of the gate electrode is smaller than the width of the chromium layer pattern. Doing; Doping n-type or p-type impurities using the chromium layer as a mask; Removing the chromium layer pattern; doping a low concentration of n-type or p-type impurities in a region blocked by the chromium layer pattern.

In addition, it is preferable to form a gate pad and a gate external circuit portion pattern on the gate insulating film while forming a gate electrode.

In addition, the gate electrode, the gate pad, and the gate external circuit pad may be formed as a double layer of a lower layer of AlNd and an upper layer of MoW.

In addition, the source electrode and the drain electrode may be formed of a double layer of a lower layer of MoW and an upper layer of AlNd.

In addition, the step of forming an organic film exposing the first contact hole and the second contact hole on the interlayer insulating film is preferably embossed on the upper surface of the organic film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor substrate for a reflective liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ and II′-II ″ of FIG. 1.

1 and 2, a blocking layer 111 made of silicon oxide or silicon nitride is formed on an upper surface of the transparent insulating substrate 110, and a source region 153 and a drain are formed on the blocking layer 111. The polycrystalline silicon layer 150 including the region 155 and the channel region 154 is formed. A lightly doped drain (LDD) region 152 is formed in the polycrystalline silicon layer 150. The LDD region 152 is a lightly doped region formed between the source region 153 and the channel region 154 and formed between the drain region 155 and the channel region 154. In the LDD region 152, the source region 153 and the channel region 154 or the drain region 155 and the channel region 154 are clearly separated from each other so that leakage current or punch-through occurs. Prevent it.

The gate insulating layer 140 is formed on the upper surface of the insulating substrate 110 while covering the polysilicon layer 150. A gate line 121 extending in the horizontal direction is formed on the upper surface of the gate insulating layer 140, and a part of the gate line 121 extends in the vertical direction to partially overlap the polycrystalline silicon layer 150, and the polycrystalline silicon layer The gate line 121 partially overlapping the 150 becomes the gate electrode 123.

In addition, the storage electrode line 131 is formed to be parallel to the gate line 121, and is formed on the same layer using the same material. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and a corresponding portion of the polycrystalline silicon layer 150 becomes the storage electrode region 156. The gate pad 125 and the gate driver circuit pad 420 are formed simultaneously with the formation of the gate line 121 and the storage electrode line 131. The gate driving circuit unit pad 420 connects the gate driving circuit unit 410 with an external circuit such as a timing controller or a voltage supply unit, and the gate pad 125 connects the gate driving circuit unit 410 and the gate line 171 to a gate. The scan signal generated to drive the gate electrode 121 in the driving circuit unit 410 is transferred to the gate line 171.

Hereinafter, the gate line 121, the gate electrode 123, and the gate pad 125 are referred to as gate wirings, and the sustain electrode 133 and the sustain electrode line 131 are referred to as sustain electrode wirings.

The gate wirings 121, 123, and 125 and the gate driving circuit pad 420 are formed of a double layer in which aluminum neodymium (AlNd) is formed on a lower layer and molybdenum tungsten (MoW) is formed on an upper layer. That is, the gate electrode 123 is formed of a double layer of the AlNd gate electrode 231 and the MoW gate electrode 232, and the gate pad 125 is a double layer of the AlNd gate pad 251 and the MoW gate pad 252. Formed. The gate driver circuit pad 420 is formed of a double layer of the AlNd gate driver circuit pad 421 and the MoW gate driver circuit pad 422.

In order to prevent poor contact characteristics due to contact between aluminum neodymium (AlNd) and ITO when the gate pad 123 and the gate driving circuit pad 420 are in direct contact with indium tin oxide (ITO), which will be described later, aluminum neodymium ( Molybdenum tungsten (MoW) is formed on the upper layer of AlNd).

An interlayer insulating film 601 is formed on the gate insulating film 140 on which the gate wirings 121, 123, and 125, the gate driving circuit pad 420, and the storage electrode wirings 131 and 133 are formed. The gate insulating layer 140 and the interlayer insulating layer 601 include a first contact hole 161 and a second contact hole 162 exposing the source region 153 and the drain region 155, respectively. In addition, the interlayer insulating layer 601 has a third contact hole 163 and a fourth contact hole 164 exposing the gate pad 125 and the gate driving circuit part pad 420, respectively.

The organic layer 602 is formed on the upper surface of the interlayer insulating layer 601 except for the gate driving circuit pad 420. Embossing 50 can be formed on the surface of the organic film 602. The embossing 50 allows reflection to occur well in the transflective liquid crystal display.

The organic layer 602 is formed while exposing the first, second, third and fourth contact holes 161, 162, 163 and 164 formed in the interlayer insulating layer 601. A transmissive electrode 90 made of ITO is formed on the top surface of the organic layer 602, and a reflective electrode 80 made of metal such as aluminum neodymium (AlNd) is formed on the transmissive electrode 90. The reflection electrode 80 and the transmission electrode 90 are referred to as pixel electrodes. The transmission electrode 82 is formed in the reflective electrode 80, and only the transmission electrode 90 exists in the transmission window 82. Thus, the transmission window 82 is used as a passage through which light from the backlight can pass when used in the transmission type. An auxiliary gate pad 95 is formed of ITO in the third contact hole 163 to which the gate pad 163 is exposed. In addition, an auxiliary gate driving circuit pad 415 is formed of ITO in the fourth contact hole 164 where the gate driving circuit pad 420 is exposed.

The data line 171 is formed long on the upper surface of the organic layer 602 to vertically cross the gate line 121, and the source electrode 173 of the data line 171 has the first contact hole 161. It is connected to the source region 153 through the (). In addition, the drain electrode 175 is connected to the drain region 155 through the second contact hole 162. The source electrode 173 and the drain electrode 175 are formed of a double layer in which molybdenum tungsten (MoW) is formed in the lower layer and aluminum neodymium (AlNd) is formed in the upper layer.

The auxiliary gate pad connecting line 53 and the auxiliary gate driving circuit pad connecting line 416 are formed on the auxiliary gate pad 95 and the auxiliary gate driving circuit pad 415 as double layers of MoW and AlNd, respectively. That is, the source electrode 173 is formed of a double layer of the MoW source electrode 731 and the AlNd source electrode 732, and the drain electrode 175 is a double layer of the MoW drain electrode 751 and the AlNd drain electrode 752. Formed. In addition, the auxiliary gate pad connecting line 53 is formed of a double layer of the MoW auxiliary gate pad connecting line 54 and the AlNd auxiliary gate pad connecting line 55. In addition, the auxiliary gate driving circuit part connecting line 416 is formed of a double layer of the MoW auxiliary gate driving circuit part connecting line 417 and the AlNd auxiliary gate driving circuit part connecting line 418.

The transmissive electrode 90, the auxiliary gate pad 95, and the auxiliary gate driving circuit pad 415 formed of ITO are respectively connected to the drain electrode 175, the auxiliary gate pad connecting line 53, and the auxiliary gate driving circuit pad connecting line ( In the case of direct contact with 416, in order to prevent poor contact characteristics between AlNd and ITO, MoW is formed on the upper layer of ITO, and AlNd is formed thereon.

A method of manufacturing a thin film transistor substrate according to one embodiment described will be described in detail.

3A to 3G are views for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 3A, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. An amorphous silicon layer 150A is formed on the top surface of the blocking layer 111. The amorphous silicon layer 150A is formed by depositing amorphous silicon with a chemical vapor deposition (CVD) method to a thickness of about 500 GPa.

Next, as shown in FIG. 3B, the amorphous silicon layer 150A is crystallized by laser annealing or furnace annealing and then patterned by photolithography to form a polycrystalline silicon layer 150. .

Next, as shown in FIG. 3C, after forming the gate insulating layer 140 on the polysilicon layer 150, the gate electrode 123, the gate pad 125, and the gate line 121 are formed and simultaneously maintained. The electrode 133 and the storage electrode line 131 are formed. At the same time, the gate driving circuit portion pad 125 is formed.

The gate insulating layer 140 is formed by depositing an insulating material such as silicon nitride or silicon oxide to a thickness of 500 to 3000 kPa by a chemical vapor deposition method.

The gate electrode 123 and the gate line 121 are formed of a double layer including an aluminum-containing metal layer, such as aluminum or aluminum neodymium (AlNd), and a chromium (Cr) or molybdenum tungsten (MoW) alloy layer on the upper surface of the gate insulating layer 140. The conductive material layer is deposited and patterned by photolithography. That is, the gate electrode 123 is formed of a double layer of the AlNd gate electrode 231 and the MoW gate electrode 232, and the gate pad 125 is formed of a double layer of the AlNd gate pad 251 and the MoW gate pad 252. do. In addition, the gate driver circuit pad 420 is formed of a double layer of the AlNd gate driver circuit pad 421 and the MoW gate driver circuit pad 422. In order to prevent poor contact characteristics due to contact between aluminum neodymium (AlNd) and ITO when the gate pad 123 and the gate driving circuit pad 420 are in direct contact with indium tin oxide (ITO), which will be described later, aluminum neodymium ( Molybdenum tungsten (MoW) is formed on the upper layer of AlNd). In this case, in order to form a lightly doped region to be described later, a chromium (Cr) layer pattern is formed in the same pattern as the gate electrode 123, the gate pad 125, and the gate driving circuit pad 420 simultaneously.

As shown in FIG. 3D, the sidewall of the gate electrode 123 is etched more by the difference in the etching rate between the chromium layer pattern 58 and the gate electrode 123. The source region 153, the drain region 155, and the channel region 154 are formed by implanting a p-type or n-type conductive impurity onto the polysilicon layer 150 using the chromium layer pattern 58 as a mask. do. The channel region 154 is a region that is not doped with impurities and is positioned under the gate electrode 123 and separates the source region 153 and the drain region 155.

As shown in FIG. 3E, after the chromium layer pattern 58 is removed, a low concentration doped region 152 is formed by implanting a low concentration of p-type or n-type conductive impurities using the gate electrode 123 as a mask. do. That is, the lightly doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 153 and the channel region 154.

Next, as shown in FIG. 3F, an insulating material is stacked on the entire surface of the insulating substrate 110 on which the source region 153, the drain region 155, and the channel region 154 are formed to form an interlayer insulating layer 601. . A first contact hole 161 and a second contact hole 162 exposing the source region 153 and the drain region 155 are formed in the interlayer insulating layer 601 by a photolithography method. In this case, a third contact hole 163 exposing the gate pad 125 and a fourth contact hole 164 exposing the gate driving circuit part pad 420 are formed.

Next, as shown in FIG. 3G, the organic layer 602 is formed on the remaining interlayer insulating layer 601 except for the interlayer insulating layer 601 on the gate driving circuit pad 420. In this case, the organic layer 602 is patterned to expose the first contact hole 161, the second contact hole 162, and the third contact hole 163. In this case, embossing 50 is formed on the surface of the organic film 602 at the same time. This is to cause a lot of diffuse reflection in the transflective liquid crystal display. Since the depths of the first to third contact holes 161, 162, and 163 and the depth of the embossing 50 are different, a halftone mask is used. Half tone mask is a lattice layer formed on the mask, and the lattice layer is formed by a slit or a lattice-like fine pattern having a size smaller than the resolution of the light source, and has a light transmittance higher than the opening of the mask. low. Therefore, since the light transmittance of the light passing through the lattice layer is low, the organic film 602 is slightly etched, and the light transmittance of the light passing through the opening is high, so that the organic film 602 is etched a lot. Accordingly, the pattern formed on the organic layer 602 may be formed to have a difference in depth.

Next, as shown in FIG. 3H, ITO is deposited on the organic layer 602 and patterned to form a transmissive electrode 90, an auxiliary gate pad 95, and an auxiliary gate driving circuit pad 415. In the periphery of the transmission electrode 90, a reflective electrode 80 is formed of a metal of aluminum neodymium (AlNd). The auxiliary gate pad 95 is formed in the third contact hole 163 to which the gate pad 125 is exposed, and the auxiliary gate driver circuit pad 415 is a fourth contact to which the gate driver circuit pad 95 is exposed. It is formed in the sphere 164.

Next, as shown in FIG. 2, the source electrode 173 and the drain electrode 175, which are part of the data line 171, are formed in the first and second contact holes 161 and 162. The data line 171 is connected to the source region 153 through the first contact hole 161, and one end of the drain electrode 175 is connected to the drain region 155 through the second contact hole 162. The other end of the drain electrode 175 is connected to the reflective electrode 80. The data line 171 is formed to vertically intersect the gate line 121, and a pixel region in which the reflective electrode 80 and the transmission electrode 90 are formed by the data line 171 and the gate line 121 is defined. .

The auxiliary gate pad connecting line 53 and the auxiliary gate driving circuit pad connecting line 416 are formed on the auxiliary gate pad 95 and the auxiliary gate driving circuit pad 415 as double layers of MoW and AlNd, respectively. That is, the source electrode 173 is formed of a double layer of the MoW source electrode 731 and the AlNd source electrode 732, and the drain electrode 175 is formed of a double layer of the MoW drain electrode 751 and the AlNd drain electrode 752. do. In addition, the auxiliary gate pad connecting line 53 is formed of a double layer of the MoW auxiliary gate pad connecting line 54 and the AlNd auxiliary gate pad connecting line 55. In addition, the auxiliary gate driving circuit part connecting line 416 is formed of a double layer of the MoW auxiliary gate driving circuit part connecting line 417 and the AlNd auxiliary gate driving circuit part connecting line 418.

This is because between the AlNd and the ITO when the auxiliary gate pad 95 and the auxiliary gate driving circuit pad 415 formed of ITO are in direct contact with the auxiliary gate pad connecting line 53 and the auxiliary gate driving circuit pad connecting line 416, respectively. In order to prevent poor contact properties, MoW is formed on the upper layer of ITO, and AlNd is formed thereon.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

The thin film transistor substrate and the manufacturing method thereof according to the present invention reduce the number of processes, simplify the process to lower the manufacturing cost and increase the yield.

Claims (17)

Insulating substrate; A polycrystalline silicon layer formed on the insulating substrate and including a source region and a drain region and a channel region disposed between the source region and the drain region; A gate insulating film covering the polycrystalline silicon layer; A gate electrode formed on the gate insulating film; An interlayer insulating film covering the gate electrode; An organic film formed on the interlayer insulating film; A pixel electrode formed on the organic layer; A source electrode formed on the organic film and the pixel electrode and connected to the source region and the drain region through first and second contact holes penetrating the organic film, the interlayer insulating film, and the gate insulating film, respectively; Drain electrode; The thin film transistor substrate of claim 1, wherein the drain electrode is connected to the pixel electrode. In claim 1, The pixel electrode is a thin film transistor substrate consisting of a reflective electrode and a transmission electrode having a transmission window. In claim 2, The gate electrode is a thin film transistor substrate formed of a double layer of an AlNd lower layer and a MoW upper layer. The method of claim 2 or 3, The source electrode and the drain electrode are formed of a double layer of a lower layer of MoW and an upper layer of AlNd. In claim 2, A thin film transistor substrate having embossing formed on an upper surface of the organic film. In claim 2, A thin film transistor substrate having a gate external circuit portion pad for connecting an external signal to a gate driving circuit portion on the gate insulating film. In claim 6, And a gate pad connecting the scan signal applied from the gate driving circuit to the gate electrode is formed on the gate insulating film. In claim 6 or 7, The gate pad and the gate external circuit pad are formed of a double layer of a lower layer of AlNd and an upper layer of MoW. In claim 2, And a lightly doped region between the source region and the channel region and between the drain region and the channel region. Forming an amorphous silicon layer on the insulating substrate; Crystallizing the amorphous silicon layer, followed by patterning to form a polycrystalline silicon layer; Forming a gate insulating film on the polycrystalline silicon layer; Forming a gate electrode and a sustain electrode wiring on the gate insulating film; Forming a source region, a drain region, and a channel region not doped with impurities in the polycrystalline silicon layer; Forming an interlayer insulating film on the gate electrode and sustain electrode wiring; Forming a first contact hole exposing the source region and a second contact hole exposing the drain region in the interlayer insulating film and the gate insulating film; Forming an organic layer on the interlayer insulating layer to expose the first and second contact holes; Forming a pixel electrode on the organic layer; Forming a data line on the organic layer including a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole; Method of manufacturing a thin film transistor substrate comprising a. In claim 10, And forming a transparent electrode in the forming of the pixel electrode and simultaneously forming a reflective electrode in the forming of the data line. In claim 11, The forming of the channel region may further include forming a lightly doped region between the source region and the channel region and between the drain region and the channel region. In claim 12, The forming of the lightly doped region may include forming a chromium layer pattern coincident with the gate electrode; Etching only a part of the sidewall of the gate electrode such that the width of the gate electrode is smaller than the width of the chromium layer pattern; Doping n-type or p-type impurities using the chromium layer as a mask; Removing the chromium layer pattern; Doping a low concentration of n-type or p-type impurities in the region that was blocked by the chromium layer pattern; Method of manufacturing a thin film transistor substrate comprising a. In claim 11, And forming a gate pad and a gate external circuit portion pattern on the gate insulating film while forming a gate electrode. The method of claim 14, The gate electrode, the gate pad, and the gate external circuit pad are formed of a double layer of a lower layer of AlNd and an upper layer of MoW. The method of claim 14, And the source electrode and the drain electrode formed of a double layer of a lower layer of MoW and an upper layer of AlNd. The method of claim 14, And forming embossing on the upper surface of the organic layer simultaneously with forming the organic layer exposing the first contact hole and the second contact hole on the interlayer insulating film.