KR20040042401A - Method for driving plasma display panel - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel is provided to remove the sustain discharge of previous subfields and form uniform wall charges within cells by micro discharging repeatedly within the cells during a reset period. CONSTITUTION: The sustain discharge of previous subfields are erased by applying a rising voltage or a falling voltage to a couple of sustain electrodes during a reset period corresponding to one or more subfields of plural subfields within one frame. A wall charge is generated simultaneously when the sustain discharge of previous subfields are erased. The falling voltage is applied a scan electrode of the sustain electrode couple and the rising voltage is applied to a sustain electrode of the sustain electrode couple.

Description

Driving Method of Plasma Display Panel {METHOD FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to improve dark contrast.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y, 13Z).

The transparent electrodes 12Y and 12Y are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in a stripe or lattice shape to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, a rising ramp waveform Ramp-up that rises to the peak voltage Vp is simultaneously applied to all the scan electrodes Y. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

In the reset period of the conventional PDP driven as described above, the wall charge necessary for the address discharge must be uniformly retained. In addition, since the address discharge is easily generated when the negative wall charges (approximately intermediate voltages between the scan electrode Y and the address electrode X) remain on the sustain electrode Z experimentally, the sustain electrode Z is easily generated. Negative wall charges must remain. However, in the driving waveform of the conventional PDP shown in FIG. 3, sufficient negative wall charges do not remain in the sustain electrode Z since the ramp ramp down to the ground potential GND.

In order to solve this problem, a method of lowering the ramp ramp down to the negative voltage (-Vr) as shown in FIG. 4 has been proposed. When the ramp ramp down is lowered to the negative voltage (-Vr), sufficient erasing is performed in the discharge cell, thereby easily generating an address discharge. That is, sufficient negative wall charges can remain in the sustain electrode Z.

However, in the conventional method of supplying the driving waveform, a large number of fine discharges are generated when the ramp-up supply is applied, and the dark-room contrast ratio is reduced by the fine discharge. have. In detail, when the rising ramp waveform Ramp-up is supplied, surface discharge occurs between the scan electrode Y and the sustain electrode Z, and a counter discharge occurs between the scan electrode Y and the address electrode X in the discharge cells. do. Among them, most of the light generated in the surface discharge between the scan electrode Y and the sustain electrode Z is emitted toward the observer located in the front of the screen, thereby reducing the darkroom contrast ratio.

Accordingly, it is an object of the present invention to provide a method of driving a plasma display panel that can improve darkroom contrast.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 illustrates a frame of a plasma display panel divided into a plurality of subfields.

3 is a waveform diagram showing a driving method of a conventional plasma display panel.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to another conventional embodiment.

5 is a waveform diagram illustrating a method of driving a plasma display panel according to an embodiment of the present invention.

FIG. 6 is a diagram showing an address discharge current flowing by the driving waveform shown in FIG. 5; FIG.

FIG. 7 is a diagram showing wall charges formed on electrodes by the address discharge current shown in FIG. 6; FIG.

FIG. 8 is a diagram showing a reset current flowing by the driving waveform shown in FIG. 5; FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrodes 14, 22: dielectric layer

16: protective film 18: lower substrate

24: partition 26: phosphor layer

In order to achieve the above object, the driving method of the plasma display panel according to the present invention includes one of a rising voltage and a falling voltage for each of the sustain electrode pairs during the initialization period of at least one subfield among a plurality of subfields included in one frame. Applying a voltage to erase the sustain discharge of the previous subfield and simultaneously forming the wall charge.

A falling voltage is applied to the scan electrodes of the sustain electrode pairs, and a rising voltage is applied to the sustain electrodes of the sustain electrode pairs.

After the reset voltage is supplied to the sustain electrode, a rising voltage gradually rising from the reset voltage is applied.

The voltage value of the reset voltage is set to 60 V or more.

The voltage value of the reset voltage is set to less than half of the voltage value of the sustain pulse supplied to the sustain electrode in the sustain period.

After the sustain period, an erase pulse for erasing the sustain discharge is not supplied to the sustain electrode pair.

The falling voltage and rising voltage are simultaneously supplied.

The falling voltage is supplied after a certain time after the rising voltage is supplied.

The constant time is set between 1 ms and 100 ms.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 8.

5 is a waveform diagram showing a driving waveform according to an embodiment of the present invention.

5 shows driving waveforms supplied to the n (n is a natural number) th subfield.

Referring to FIG. 5, the driving waveform of the PDP of the present invention is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. Here, the erase pulses are not supplied to the sustain electrodes Z after the sustain period. In other words, as shown in FIG. 5, the erase pulses are not supplied to the sustain electrodes Z after the sustain period of the n−1 subfield.

During the initialization period, the rising ramp waveform Ramp-up, which rises from the reset voltage Vr to the peak voltage Vp1, is supplied to the sustain electrodes Z. Here, the peak voltage Vp1 may be determined at the sustain voltage Vs level. In addition, during the initialization period, a falling ramp waveform (Ramp-down) falling from the base potential is supplied to the scan electrodes (Y). Here, the ramp ramp down may be lowered to the negative voltage (−Vr) shown in FIG. 4. On the other hand, the ramp ramp down (Ramp-down) is supplied after a predetermined time (T1) after the ramp ramp (Ramp-up) is supplied (wherein the constant time (T1) is set between 1㎲ to 100㎲. .. Here, the falling ramp-down and rising ramp waveform (Ramp-up) can be supplied at the same time.

During the initialization period, when the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down are supplied to the sustain electrodes Z and the scan electrodes Y, the sustain electrodes Z and the scan electrodes Y A large number of microdischarges are generated by the voltage difference between them. This microdischarge eliminates the sustain discharge of the previous subfield and simultaneously forms wall charges in the cells. On the other hand, when the reset voltage Vr is too small, erase discharge is insufficiently generated, and when the reset voltage Vr is too high, an unnecessary strong discharge is generated. Therefore, in the present invention, the reset voltage Vr is set to 60 V or less than half of the sustain voltage Vs so that a stable erase discharge is generated in the discharge cell.

In detail, the setup period is first supplied with the last sustain pulse in the previous subfield to the scan electrode (Y). Therefore, negative charges (-) are formed on the scan electrodes (Y) and positive charges (+) are formed on the sustain electrodes (Z) at the start of the setup period. Subsequently, when the rising ramp waveform Ramp-up is supplied to the sustain electrode Z during the initialization period, the voltage values of the positive wall charges previously formed on the sustain electrodes Z and the rising ramp waveform Ramp− up) voltage values are added together. In addition, when the ramp ramp down is supplied to the scan electrode Y during the initialization period, the voltage values of the negative wall charges previously formed on the scan electrodes and the ramp ramp waveform are lower. down) is added together.

Therefore, a predetermined voltage difference is generated between the scan electrodes Y and the sustain electrodes Z during the initialization period, and thus a plurality of fine discharges are generated between the scan electrodes Y and the sustain electrodes Z. . Such microdischarge eliminates the sustain discharge of the previous subfield and forms uniform wall charges in the cells. Meanwhile, negative wall charges are formed in the sustain electrodes Z by a plurality of micro discharges. In addition, negative charges and positive wall charges are formed in the scan electrodes Y by a plurality of micro discharges.

In detail, the rising ramp waveform Ramp-up rising from the reset voltage Vr is supplied to the sustain electrodes Z. In other words, since high voltage values are supplied during the initialization period, negative wall charges are formed in the sustain electrodes Z. FIG. However, the falling ramp waveform Ramp-down, which falls from the base potential, is supplied to the scan electrodes Y. In other words, since the low negative voltage is supplied to the scan electrodes Y during the initialization period, all of the negative wall charges formed in the previous subfield period are not erased. In fact, positive wall charges are formed on one side of the scan electrode Y positioned adjacent to the sustain electrode Z during the initialization period, and the other side of the scan electrode Y not adjacent to the sustain electrode Z. During the initialization period, negative wall charges are maintained. Such negative wall charges are used as the wall voltage causing the address discharge during the address period.

Meanwhile, in the n subfield according to another embodiment of the present invention, microdischarge is caused by using wall charges previously formed in the sustain discharge. Therefore, the driving waveform supplied in the first subfield located at the first of the frame can be set in the same manner as the conventional driving waveform shown in FIG.

In the initialization period of the present invention, since the wall charges are formed in the cells through the erasing discharge, a lower peak voltage Vp1 is applied than in the prior art, and thus darkroom contrast can be improved. In other words, by applying a peak voltage Vp1 lower than that of the conventional PDP, the darkroom contrast can be improved by reducing the number and intensity of surface discharges. In addition, the voltage value of the peak voltage Vp1 supplied in the initialization period can be lowered, thereby enabling low voltage driving. In addition, since a time less than a conventional initialization period driven by being divided into a setup and a set-down period can be allocated to the initialization period, more time can be allocated to the sustain period.

On the other hand, the PDP proposed through Japanese Patent Application Laid-Open No. 2001-135238 increases the density of Xe components in the discharge gas encapsulated in the PDP, so that the driving voltage is higher than that of the conventional low density Xe panel. Higher, but higher brightness. Applying the present invention to such a high density Xe panel, it is possible to lower the driving voltage of the high voltage level required by increasing the Xe component in the discharge gas (the peak voltage value (Vp1) is lowered) is applied to a high density Xe panel and high brightness Low voltage driving can be satisfied at the same time.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs.

FIG. 6 is a diagram illustrating an address discharge current in a panel to which a driving waveform according to an exemplary embodiment of the present invention shown in FIG. 5 is applied.

Referring to FIG. 6, it can be seen that a stable address discharge current flows for a short address period in a panel according to an exemplary embodiment of the present invention. In other words, in the panel to which the present invention is applied, the address discharge is shortened by about 0.2 [mu] s than that of the conventional panel. Therefore, in the present invention, the address period can be shortened. After the address discharge is generated as shown in FIG. 6, positive wall charges are formed on the scan electrode Y and negative wall charges are formed on the sustain electrode Z as shown in FIG. 7. At this time, sufficient wall charges are formed in the scan electrode Y and the sustain electrode Z, which can cause a stable sustain discharge in the sustain period.

In addition, in the present invention, as shown in FIG. 8, the initialization period is narrower than that of the conventional PDP. In practice, as shown in FIG. 8, the conventional PDP includes an initialization period of approximately 300 ms, while the PDP of the present invention includes an initialization period of approximately 160 ms. In addition, the PDP of the present invention flows a lower discharge current than the conventional PDP as shown. That is, the PDP of the present invention can provide an improved dark room contrast ratio compared to the conventional PDP.

As described above, according to the driving method of the plasma display panel according to the present invention, a plurality of micro discharges are generated in the cell during the initialization period, thereby erasing the sustain discharge of the previous subfield and forming uniform wall charges in the cell. . To this end, a falling voltage is supplied to the scan electrode and a rising voltage is supplied to the sustain electrode. At this time, the number of discharges and the intensity of the discharges generated during the initialization period can be minimized to improve the dark room contrast. In addition, the reset period is shortened to about half of the conventional one, and more time can be allocated to the sustain period. In addition, the plasma display panel of the present invention can be applied to a high-density Xe panel due to low voltage driving.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

In the plasma display panel having a plurality of sustain electrode pairs formed in pairs with each other, During the initialization period of at least one of the plurality of subfields included in one frame, one of the rising voltage and the falling voltage is applied to each of the sustain electrode pairs to erase the sustain discharge of the previous subfield. Forming a wall charge; and driving the plasma display panel. The method of claim 1, And the falling voltage is applied to a scan electrode of the sustain electrode pairs, and the rising voltage is applied to a sustain electrode of the sustain electrode pairs. The method of claim 2, And the rising voltage gradually rising from the reset voltage after the reset voltage is supplied to the sustain electrode. The method of claim 3, And the voltage value of the reset voltage is set to 60 V or more. The method of claim 4, wherein And the voltage value of the reset voltage is set to less than half the voltage value of the sustain pulse supplied to the sustain electrode in the sustain period. The method of claim 5, And an erase pulse for erasing sustain discharge is not supplied to said sustain electrode pair after said sustain period. The method of claim 2, And the falling voltage and the rising voltage are simultaneously supplied. The method of claim 2, And the falling voltage is supplied after a predetermined time after the rising voltage is supplied. The method of claim 8, And the predetermined time period is set between 1 kHz and 100 kHz.