KR20040042050A - In plane switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: An in-plane switching mode liquid crystal display is provided to generate a sufficient quantity of capacitance and improve aperture ratio. CONSTITUTION: An in-plane switching mode liquid crystal display(101) includes a gate line(103) and a data line(104). The gate line and the data line define a pixel. A thin film transistor(110) consisting of a gate electrode(111), a semiconductor layer(112), source and drain electrodes(113,114) is formed in the pixel. A common electrode(105) and a pixel electrode(107) are arranged in parallel with the data line in the pixel. The common electrode and the pixel electrode are respectively connected to a common line(116) and a pixel electrode line(118). The common line and the pixel electrode line are arranged in parallel with the gate line such that the common line and the pixel electrode line are not located in the pixel.

Description

Transverse electric field mode liquid crystal display device {IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field mode liquid crystal display device, and more particularly, to a transverse electric field mode liquid crystal display device capable of securing sufficient storage capacity and improving aperture ratio by arranging common lines and pixel electrode lines along a gate line. .

Recently, with the development of various portable electronic devices such as mobile phones, PDAs, and notebook computers, there is a growing demand for flat panel display devices for light and thin applications. Such flat panel displays are being actively researched, such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), VFD (Vacuum Fluorescent Display), but mass production technology, ease of driving means, Liquid crystal display devices (LCDs) are in the spotlight for reasons of implementation.

Such liquid crystal display devices have various display modes according to the arrangement of liquid crystal molecules. However, TN mode liquid crystal display devices are mainly used because of the advantages of easy monochrome display, fast response speed, and low driving voltage. In such a TN mode liquid crystal display device, liquid crystal molecules aligned horizontally with the substrate are almost perpendicular to the substrate when a voltage is applied. Therefore, there is a problem that the viewing angle is narrowed upon application of voltage due to refractive anisotropy of the liquid crystal molecules.

In order to solve this viewing angle problem, liquid crystal display devices of various modes having wide viewing angle characteristics have recently been proposed, but among them, the liquid crystal display device of the lateral field mode (In Plane Switching Mode) is applied to actual production. It is produced. The IPS mode liquid crystal display device aligns liquid crystal molecules in a plane by forming at least one pair of electrodes arranged in parallel in a pixel to form a transverse electric field substantially parallel to the substrate.

The structure of the IPS mode liquid crystal display device described above is shown in FIG. As shown in the figure, the pixels of the liquid crystal panel 1 are defined by gate lines 3 and data lines 4 arranged vertically and horizontally. Although only the (n, m) th pixels are shown in the drawing, the actual liquid crystal panel 1 has N (≥n) and M (≥m) gate lines 3 and data lines 4, respectively. Are arranged so as to form N × M pixels over the entire liquid crystal panel 1. The thin film transistor 10 is formed at the intersection of the gate line 3 and the data line 4 in the pixel. The thin film transistor 10 includes a gate electrode 11 to which a scan signal is applied from the gate line 3, and a semiconductor layer formed on the gate electrode 11 and activated as a scan signal is applied to form a channel layer. 12 and a source electrode 13 and a drain electrode 14 formed on the semiconductor layer 12 and to which an image signal is applied through the data line 4. The image signal input from the outside is applied to the liquid crystal layer. do.

In the pixel, a plurality of common electrodes 5 and a pixel electrode 7 are arranged substantially parallel to the data line 4. In addition, a common line 16 connected to the common electrode 5 is disposed in the middle of the pixel, and a pixel electrode line 18 connected to the pixel electrode 7 is disposed on the common line 16. It overlaps with the common line 16.

As described above, in the configured IPS mode liquid crystal display device, the liquid crystal molecules are oriented substantially in parallel with the common electrode 5 and the pixel electrode 7. When the thin film transistor 10 is operated to apply a signal to the pixel electrode 7, a transverse electric field substantially parallel to the liquid crystal panel 1 is generated between the common electrode 5 and the pixel electrode 7. Since the liquid crystal molecules rotate on the same plane along the transverse electric field, gray level inversion due to the refractive anisotropy of the liquid crystal molecules can be prevented.

FIG. 2 is a cross-sectional view of a conventional IPS mode liquid crystal display device. FIG. 2 (a) is a cross-sectional view taken along the line II ′ and FIG. 2 (b) is a cross-sectional view taken along the line II-II ′. As shown in FIG. 2A, a gate electrode 11 is formed on the first substrate 20, and a gate insulating layer 22 is stacked over the entire first substrate 20. The semiconductor layer 12 is formed on the gate insulating layer 22, and the source electrode 13 and the drain electrode 14 are formed thereon. In addition, a passivation layer 24 is formed on the entire first substrate 20.

The black matrix 32 and the color filter layer 34 are formed on the second substrate 30. The black matrix 32 is to prevent light leakage into a region in which the liquid crystal molecules do not operate. As shown in the drawing, the black matrix 32 is between the thin film transistor 10 region and the pixel and the pixel (that is, the gate line and the data line). Area). The color filter layer 34 is composed of R (Red), B (Blue), and G (Green) to realize actual colors.

The liquid crystal layer 40 is formed between the first substrate 20 and the second substrate 30 to complete the liquid crystal panel 1.

Meanwhile, as shown in FIG. 2B, the common electrode 5 is formed on the first substrate 20, and the pixel electrode 7 is formed on the gate insulating layer 22 to form the common electrode 5. ) And the pixel electrode 7 generate a transverse electric field. Initially, the liquid crystal molecules arranged along the alignment direction of the alignment layer (usually oriented at a predetermined angle with the common electrode and the pixel electrode) are rotated along the transverse electric field formed between the common electrode 5 and the pixel electrode 7. Display an image on the screen.

In the IPS mode liquid crystal display of the above structure, the common line 16 and the pixel electrode line 18 overlap each other in the pixel with the gate insulating layer 22 therebetween to form storage capacitance. The storage capacitor improves the holding characteristic of the voltage applied to the liquid crystal, improves the stability of the gray scale display, and reduces flicker and residual images. Therefore, securing the set storage capacity is a very important factor in manufacturing the liquid crystal display device.

In general, an IPS mode liquid crystal display device is classified into a storage on common (SOC) method and a storage on gate (SOG) method according to a method of forming a storage capacitor. In the SOC type liquid crystal display device, a common line is formed in a pixel to arrange pixel electrode lines so as to overlap the common line, thereby forming a storage capacitor by the pixel electrode line and the common line, as shown in FIGS. 1 and 2. The IPS mode liquid crystal display device is a liquid crystal display device of such SOC type. However, the SOC liquid crystal display device has the following problems. In other words, in order to obtain a sufficient amount of storage capacity, the width of the common line and the pixel electrode line must be increased to increase the overlap area of the common line and the pixel electrode line. In this case, the liquid crystal display is performed by the wide common line and the pixel electrode line. There was a problem that the aperture ratio of the device was lowered.

On the other hand, in the SOG type liquid crystal display device, since the pixel electrode lines are arranged to overlap the gate line to form a storage capacitor by the pixel electrode line and the gate line, the aperture ratio of the liquid crystal display device is lowered because no common line is disposed in the pixel. There is an advantage that can be prevented. However, in the SOG type liquid crystal display device, since the gate lines are formed to have a set width, the overlap area between the gate lines and the pixel electrode lines is inevitably limited, and as a result, a sufficient amount of storage capacitance cannot be formed. There was.

SUMMARY OF THE INVENTION The present invention solves the above problem, and generates a storage capacitance between the gate line and the pixel electrode line and between the pixel electrode line and the common line by overlapping the gate line, the pixel electrode line and the common line with the insulating layer interposed therebetween. It is therefore an object of the present invention to provide a transverse electric field mode liquid crystal display device capable of generating a desired sufficient storage capacity.

Another object of the present invention is to provide a transverse electric field mode liquid crystal display device having an improved aperture ratio by arranging pixel electrode lines and common lines along a gate line rather than inside the pixel.

In order to achieve the above object, a transverse electric field mode liquid crystal display device according to an aspect of the present invention comprises a plurality of gate lines and data lines defining a plurality of pixels, a driving element disposed in each pixel, and substantially within the pixels. At least one first electrode and second electrode arranged in parallel to each other to generate a transverse electric field, and connected to the first electrode and arranged along the data line to form a data line and a first storage capacitor. And a second line connected to the second electrode and arranged along the data line to form the first line and a second storage capacitor.

The first electrode and the first line are formed on the gate insulating layer as the pixel electrode and the pixel electrode line, respectively, and the second electrode and the second line are formed on the protective layer as the common electrode and the common electrode line, respectively, to form a storage capacitor. .

In addition, a transverse electric field mode liquid crystal display device according to another aspect of the present invention includes a driving element disposed in each pixel, and at least one first electrode and a second disposed in the pixel to be substantially parallel to generate a transverse electric field. A first line connected to an electrode, the first electrode and overlapping the gate line with a first insulating layer interposed therebetween, and a first line connected to the second electrode and having a second insulating layer interposed therebetween And a second line overlapped with each other.

1 is a plan view of a conventional transverse electric field mode liquid crystal display device.

2A is a cross-sectional view taken along the line II ′ of FIG. 1.

(B) is sectional drawing along the II-II 'line | wire of FIG.

3 is a plan view of a transverse electric field mode liquid crystal display device according to the present invention.

(A) is sectional drawing along the III-III 'line | wire of FIG.

(B) is sectional drawing in the IV-IV 'line | wire of FIG.

5 is a view showing a transverse electric field mode liquid crystal display device manufacturing method according to the present invention.

Explanation of symbols on the main parts of the drawings

103: gate line 104: data line

105: common electrode 107: pixel electrode

110: thin film transistor 111: gate electrode

112: semiconductor layer 112: source electrode

113: drain electrode 116: common line

118: pixel electrode line 120,130: substrate

122: gate insulating layer 124: protective layer

132: black matrix 134: color filter layer

140: liquid crystal layer

The present invention provides an IPS mode liquid crystal display device capable of providing a sufficient amount of storage capacity and improving the aperture ratio. To this end, the present invention provides an IPS mode liquid crystal display device having a structure different from that of the SOC method or the SOG method.

In recent years, a hybrid IPS mode liquid crystal display device has been proposed in order to secure a sufficient storage capacity and solve the aperture ratio problem. The hybrid IPS mode liquid crystal display device combines the advantages of both SOC and SOG methods. Two small pixel electrode lines are formed so that one pixel electrode line overlaps the common line and the other pixel electrode line is gated. By overlapping with the line, the storage capacity of the IPS mode liquid crystal display device is sufficiently secured and the aperture ratio is improved.

However, even in the hybrid IPS mode liquid crystal display device as described above, the width of the common line and the pixel electrode line must be formed to be greater than or equal to each of the set widths in order to ensure a sufficient amount of storage capacitance. .

The IPS mode liquid crystal display device of the present invention has a structure different from that of the hybrid type IPS mode liquid crystal display device. That is, in the IPS mode liquid crystal display device of the present invention, instead of arranging the common line and the pixel electrode line in the pixel, both the common line and the pixel electrode line overlap the gate line. That is, the gate line and the pixel electrode line overlap with the gate insulating layer interposed therebetween, and the pixel electrode line and the common line overlap with the protective layer therebetween. Thus, by overlapping three lines with an insulating layer interposed therebetween, a desired amount of storage capacity can be obtained and the aperture ratio can also be improved.

Hereinafter, an IPS mode liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view showing the structure of the IPS mode liquid crystal display device 101 according to the present invention. As shown in the figure, each pixel defined by the gate line 103 and the data line 104 includes a gate electrode 111, a semiconductor layer 112, a source electrode 113, and a drain electrode 114. The thin film transistor 110 is formed, and the common electrode 105 and the pixel electrode 107 are arranged in parallel with the data line in the pixel.

The common electrode 105 and the pixel electrode 107 are connected to the common line 116 and the pixel electrode line 118, respectively, and the common line 116 and the pixel electrode line 118 are connected to the gate line 103. Are arranged along. Therefore, the common line 116 and the pixel electrode line 118 are not disposed in the pixel, and as a result, the aperture ratio is improved by the width of the common line (or the pixel electrode line). In the drawing, reference numeral 117 denotes a connection line for connecting the common electrode 116 of the pixel to the common electrode of an adjacent pixel.

4 is a cross-sectional view showing the structure of the IPS mode liquid crystal display device shown in FIG. 3 in more detail. FIG. 4 (a) is a cross-sectional view taken along the line III-III 'of FIG. 3 and FIG. IV 'line cross section.

As shown in the figure, a gate line 103 is formed on the first substrate 120, and a gate insulating layer 122 is stacked on the entire first substrate 120. In addition, a pixel electrode 107, a data line 104, and a pixel electrode line 118 are formed on the gate insulating layer 122. Although not shown in the drawing, a gate electrode 111 of the thin film transistor 110 is formed on the first substrate 120, and a semiconductor layer 112 is formed on the gate insulating layer 122. In addition, a source electrode 113 and a drain electrode 114 are formed on the semiconductor layer 112 to apply a signal input from the outside to the pixel electrode 107.

The gate electrode 111 and the gate line 103 are formed by the same process, and mainly sputtering or evaporation of metals such as Cu, Cr, Ti, Mo, Ta, Al, and Al alloys. It consists of a single layer or a plurality of layers laminated and etched. In addition, the source electrode 113, the drain electrode 114 and the pixel electrode line 118 are formed by the same process, and mainly sputtering metals such as Cr, Ti, Mo, Ta, Cu, Al, and Al alloys It consists of a single layer or a plurality of layers laminated by a deposition method and etched by an etchant. The protective layer 124 is stacked on the gate insulating layer 122, and the common electrode 105 and the common line 116 are formed on the protective layer 124.

The second substrate 130 is provided with a black matrix 132 for preventing light from leaking into the non-display area and a color filter layer 134 for realizing colors. In addition, although not shown in the drawing, an overcoat layer for planarization of the second substrate 130 may be formed on the color filter layer 134.

As described above, the liquid crystal layer 140 is formed between the configured first substrate 120 and the second substrate 130 to complete the IPS mode liquid crystal display device. In this case, the liquid crystal layer 140 may be formed by a vacuum injection method in which the first substrate 120 and the second substrate 130 are bonded by a sealing material, and then the liquid crystal is vacuum injected therebetween. The liquid crystal may be formed by a liquid crystal dropping method in which the liquid crystal is uniformly distributed by the bonding force of the substrate after directly dispensing the liquid crystal onto the substrate.

As shown in FIG. 4B, the gate line 122, the pixel electrode line 118, and the common line 116 overlap each other. In this case, a gate insulating layer 122 is disposed between the gate line 122 and the pixel electrode line 118, and a passivation layer 124 is positioned between the pixel electrode line 118 and the common line 116. The first storage capacitor Cst1 is generated by the gate line 122 and the pixel electrode line 118, and the second storage capacitor Cst2 is generated by the pixel electrode line 118 and the common line 116.

The sum of the first storage capacitor Cst1 and the second storage capacitor Cst2 is the total storage capacitor applied to the pixel. This total storage capacitance is the same as the storage capacitance generated in the SOC or SOG IPS mode liquid crystal display device. In other words, even when the pixel electrode line 118 and the common line 116 are overlapped and arranged along the gate line 103, a sufficient amount of storage capacitance can be formed. Furthermore, since the common line 116 and the pixel electrode line 118 are not disposed in the pixel, the aperture ratio can be improved by the width of the common line (or the pixel electrode line).

5 (a) to 5 (c) are diagrams showing a manufacturing method of the IPS mode liquid crystal display device having the above structure. For convenience of description, the drawing is divided into a pixel area and a gate line area. The IPS mode liquid crystal display device of the present invention is basically manufactured by a five mask process, which will be briefly described as follows.

First, as shown in FIG. 5 (a), the gate line 103 is formed by stacking and etching a metal on the first substrate 120 (first mask). The gate electrode of the thin film transistor is formed at the same time as the gate line 103 is formed.

Subsequently, although not shown in the drawing, the gate insulating layer 122 is stacked over the entire first substrate 120 to form a semiconductor layer on the gate electrode (second mask), and the metal is stacked and etched to form the pixel electrode 107. The data line 104 and the pixel electrode line 118 are formed (third mask). At this time, the source / drain electrodes of the thin film transistor are formed on the semiconductor layer.

After the protective layer 124 is stacked over the first substrate 120, a contact hole (not shown) for connecting the pixel electrode 107 with an external driving element is formed (fourth mask). The common electrode 105 and the common electrode line 116 are formed by stacking and etching a metal on the protective layer 124 (a fifth mask). In this case, although not shown in the drawing, a pad contact electrode is formed at an outer portion of the liquid crystal panel during the fifth mask process.

As described above, the IPS mode liquid crystal display device according to the present invention is a 4-block liquid crystal display device. In general, a block means a region in which light passes through a liquid crystal layer to display an image in a pixel. This block depends on the number of formation of the common electrode and the pixel electrode. In the four-block IPS mode liquid crystal display device, two pixel electrodes and three common electrodes are arranged in a pixel to form four light transmitting regions. However, the IPS mode liquid crystal display device according to the present invention is not limited to the specific block structure. The number of blocks of the liquid crystal display varies depending on various factors such as the area of the liquid crystal display, the number of pixels, and the pitch between the pixels. It can be applied nicely to the invention.

As described above, the IPS mode liquid crystal display device according to the present invention may be applied to an IPS mode liquid crystal display device having any structure as long as the common line and the pixel electrode line are arranged along the gate line.

As described above, in the IPS mode liquid crystal display of the present invention, the common line and the pixel electrode line to which the common electrode and the pixel electrode arranged in parallel to each other are respectively overlapped with the gate line with the insulating layer interposed therebetween. Therefore, the following advantages can be obtained. First, it is possible to ensure a desired sufficient storage capacity by the storage capacitance generated between the gate line and the pixel electrode line and the storage capacitance generated between the pixel electrode line and the common electrode. Second, since the common line and the pixel electrode line are arranged along the gate line, the aperture ratio is improved by the width of the common line (or the pixel electrode line).

Claims (12)

A plurality of gate lines and data lines defining a plurality of pixels; A drive element disposed in each pixel; At least one first electrode and a second electrode disposed substantially parallel in the pixel to generate a transverse electric field; A first line connected to the first electrode and arranged along the gate line to form a data line and a first storage capacitor; And And a second line connected to the second electrode and arranged along the gate line to form the first line and a second storage capacitor. The transverse electric field mode liquid crystal display device of claim 1, wherein the driving device is a thin film transistor. The method of claim 2, wherein the thin film transistor, A gate electrode formed on the substrate; An insulating layer stacked over the entire substrate on which the gate electrode is formed; A semiconductor layer formed on the insulating layer; A source electrode and a drain electrode formed on the semiconductor layer; And And a protective layer stacked over the entire substrate on which the source and drain electrodes are formed. The transverse electric field mode liquid crystal display device of claim 3, wherein the first electrode is formed on an insulating layer. The transverse electric field mode liquid crystal display device of claim 3, wherein the first line is formed on an insulating layer. The transverse electric field mode liquid crystal display device of claim 3, wherein the second electrode is formed on a protective layer. The transverse electric field mode liquid crystal display device of claim 3, wherein the second line is formed on a protective layer. A plurality of gate lines and data lines defining a plurality of pixels; A drive element disposed in each pixel; At least one first electrode and a second electrode disposed in the pixel to be disposed substantially parallel to generate a transverse electric field; A first line connected to the first electrode and at least partially overlapping the gate line with a first insulating layer interposed therebetween; And And a second line connected to the second electrode, the second line overlapping the first line with at least a portion of the second insulating layer interposed therebetween. The transverse electric field mode liquid crystal display device according to claim 8, wherein the driving device is a thin film transistor. 10. The method of claim 9, wherein the thin film transistor, A gate electrode formed on the substrate; A gate insulating layer stacked over the entire substrate on which the gate electrode is formed; A semiconductor layer formed on the insulating layer; A source electrode and a drain electrode formed on the semiconductor layer; And A transverse electric field mode liquid crystal display device comprising a protective layer stacked over the entire substrate on which the source and drain electrodes are formed. The transverse electric field mode liquid crystal display device of claim 10, wherein the first insulating layer is a gate insulating layer. The transverse electric field mode liquid crystal display device of claim 10, wherein the second insulating layer is a protective layer.