KR20040035409A - Electroluminescent display panel wherein capacitance is increased - Google Patents

Abstract

PURPOSE: An electroluminescence display panel is provided to achieve improved operating speeds of transistors and electroluminescence display panel by increasing capacitance. CONSTITUTION: An electroluminescence display panel comprises a substrate(SB); a silicon layer(TR2) formed along a pattern on the substrate; a lower insulating layer(INL) formed on the silicon layer; lower metal layers(GE1,VE1) formed along a pattern on the lower insulating layer; an intermediate insulating layer(INM) formed on the lower metal layers; upper metal layers(CL1(M-1),CN1(M-1)) formed along a pattern on the intermediate insulating layer; an upper insulating layer(INT) formed on the upper metal layers; and a protruded pattern(PR) of the silicon layer disposed in the position acting as capacitors between the lower metal layers and the upper metal layers.

Description

Electroluminescent display panel where capacitance is increased}

TECHNICAL FIELD The present invention relates to an electroluminescent display panel, and more particularly, to an electroluminescent display panel in which an organic light emitting layer generates light by a strong electric field.

The electroluminescent display panel is driven by applying a strong electric field to the organic light emitting layer of the selected cell. Here, the organic light emitting layer is in an electrical breakdown state, where light is generated from the excited light emitting material while the breakdown current flows.

Referring to FIG. 1, a conventional electroluminescent display device includes an electroluminescent display panel 4 and a control logic circuit 1, a biasing circuit 2, and a switching circuit 3 for driving the electroluminescent display panel 4.

In the conventional electroluminescent display panel 4, scan lines GE ₁ , ..., GE _N and data lines DE ₁ , ..., DE _M are formed to intersect, and bias lines (VE ₁ , ..., VE _N ) are formed side by side with respect to scan lines GE ₁ , ..., GE _N. Here, each scan line GE ₁ ,..., GE _N and each bias line VE ₁ ,..., VE _N correspond to one-to-one (1: 1). Reference signs CE ₁₁ , ..., CE _NM indicate respective cell electrodes. The structure and operation of this conventional electroluminescent display panel 4 will be described in more detail with reference to FIGS. 2 and 3.

Control logic circuit (1), the process receives the display data signal (S _D) and a clock signal (S _T) from the outside, and applies a display pattern signal (S _DD), the biasing circuit 2, the switching The synchronization signal S _DT is applied to the circuit 3. Accordingly, the biasing circuit 2 drives the data lines DE ₁ ,..., And DE _M , and the switching circuit 3 drives the scan lines GE ₁ ,..., GE _N. do. A voltage Vdd to be supplied to the selected cell electrodes CE ₁₁ ,..., And CE _NM is applied to the bias lines VE ₁ ,..., And VE _N.

FIG. 2 shows the structure of the electroluminescent display panel 4 of the device of FIG. 1. FIG. 3 shows the structure of two adjacent cells up and down of the panel of FIG. 2. In Figs. 2 and 3, the same reference numerals as those in Fig. 1 indicate the objects of the same function. In FIG. 2, reference numerals DC ₁₁ ,..., DC _NM indicate cell regions. In FIG. 2, reference numeral C denotes capacitors connected between the gates and the drains of the second transistors TR2. The capacitors C may include lines connecting the sources of the first transistors TR2 and the gates of the second transistors TR2 to each other (CL _{1 (M-1)} and CL _{2 (M in} FIG. 3 ₎ . _-1) ) and the bias lines VE ₁ ,..., VE _N to operate the second transistors TR2. In FIG. 3, reference numerals CN _{1 (M-1} and CN _{2 (M-1))} are lines connecting the drains of the second transistors TR2 and the bias lines VE ₁ ,..., VE _N to each other. admit.

2 and 3, the drains of the first field effect transistors TR1 are connected to the data lines DE ₁ ,..., And DE _M , respectively. Gates Gates of the first field effect transistors TR1 are connected to the scan lines GE ₁ ,..., GE _N , respectively. Sources of the first field effect transistors TR1 are connected to gates of the second field effect transistors TR2, respectively. Drains of the second field effect transistors TR2 are respectively connected to the bias lines VE ₁ ,..., VE _N. Sources of the second field effect transistors TR2 are respectively connected to the cell electrodes CE ₁₁ ,..., CE _NM . Here, n (n is an integer of 2 or more) scan lines GE ₁ , ..., GE _N and n (n is an integer of 2 or more) and bias lines VE ₁ , ..., VE _N Respond one-to-one (1: 1).

The first field effect transistors TR1 are driven by the scan lines GE ₁ ,..., GE _N and the data lines DE ₁ ,..., DE _M. The second field effect transistors TR2 apply the voltage Vdd applied to the bias lines VE ₁ ,..., And VE _N according to an operating state of each of the first field effect transistors TR1. Optionally supplied to (CE ₁₁ , ..., CE _NM ).

In FIG. 4, the same reference numerals as used in FIG. 3 indicate objects of the same function. Referring to FIG. 4, the laminated structure of a conventional electroluminescent display panel is as follows.

The silicon layer TR2 for forming the transistor is formed in a pattern on the substrate SB. The lower insulating layer IN _L is formed on the silicon layer TR2. The lower metal layers GE ₁ and VE ₁ are formed in a pattern on the lower insulating layer IN _L. The intermediate insulating layer IN _{M is} formed on the lower metal layers GE ₁ and VE ₁ . The upper metal layers CL _{1 (M-1)} and CN _{1 (M-1} ) are formed in a pattern on the intermediate insulating layer IN _M. An upper insulating layer IN _T called passivation is formed on the upper metal layers CL _{1 (M-1)} and CN _{1 (M-1)} .

According to the stack structure of a conventional light emitting display panel described above, the bottom metal layer (VE ₁₎ and the top metal layer lower portion in a position to act as the kaepesiteo between _{(CL 1 (M-1)} ) the metal layer (VE ₁₎ and the upper As the area of the region where the metal layers CL _{1 (M-1)} face each other is limited, the capacitance is limited. Accordingly, there is a limit to the operation speed of the transistors TR2 and the improvement of the operation speed of the electroluminescent display panel.

It is an object of the present invention to provide an electroluminescent display panel whose operation speed can be further improved.

1 is a block diagram illustrating a conventional electroluminescent display device.

2 is a view showing the structure of a display panel of the device of FIG.

FIG. 3 is a plan view illustrating a structure of two adjacent cells up and down of the panel of FIG. 2.

4 is a cross-sectional view illustrating a laminated structure of a conventional electroluminescent display panel.

5 is a cross-sectional view illustrating a laminated structure of an electroluminescent display panel according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

S _D ... display data signal, S _T ... clock signal,

S _DD ... display pattern signal, S _DT ... synchronous signal,

Control logic circuit, biasing circuit,

3 ... switching circuit, 4 ... electroluminescent display panel,

GE ₁ , ..., GE _N ... scanning lines, DE ₁ , ..., DE _M ... data lines,

VE ₁ , ..., VE _N ... bias lines, CE ₁₁ , ..., CE _NM ... cell electrodes,

Vdd ... bias voltage, DC ₁₁ , ..., DC _NM ... cell regions,

TR1 ... first transistors, C ... capacitors,

TR2 ... second transistors, silicon layer,

SB ... substrate, PR ... silicon extrusion pattern,

IN _L ... bottom insulating layer, GE ₁ , VE ₁ ... bottom metal layer,

IN _M ... intermediate insulation layer, CL _{1 (M-1)} , CN _{1 (M-1)} ... upper metal layer,

IN _T ... upper insulation layer.

The electroluminescent display panel of the present invention for achieving the above object includes a substrate, a silicon layer, a lower insulating layer, a lower metal layer, an intermediate insulating layer, an upper metal layer, and an upper insulating layer. The silicon layer is formed in a pattern on the substrate. The lower insulating layer is formed on the silicon layer. The lower metal layer is formed in a pattern on the lower insulating layer. The intermediate insulating layer is formed on the lower metal layer. The upper metal layer is formed in a pattern on the intermediate insulating layer. The upper insulating layer is formed on the upper metal layer. Here, there is a protruding pattern of the silicon layer which is electrically floating at positions serving as capacitors between the lower metal layer and the upper metal layer.

According to the electroluminescent display panel of the present invention, due to the protruding pattern of the electrically floating silicon layer, all layers on the silicon layer are bent at positions serving as capacitors between the lower and upper metal layers. Becomes Accordingly, since the capacitance increases as the electrode facing area of the capacitors increases, the operating speed of the transistors and thus the operating speed of the electroluminescent display panel can be improved.

Hereinafter, preferred embodiments of the present invention will be described in detail. 1, 2, and 3 are equally applicable to embodiments of the present invention. In FIG. 5, the same symbols as in FIG. 3 indicate the objects of the same function.

2, 3, and 5, the silicon layer TR2 for forming the transistor is formed in a pattern on the substrate SB. The lower insulating layer IN _L is formed on the silicon layer TR2. The lower metal layers GE ₁ and VE ₁ are formed in a pattern on the lower insulating layer IN _L. The intermediate insulating layer IN _{M is} formed on the lower metal layers GE ₁ and VE ₁ . The upper metal layers CL _{1 (M-1)} and CN _{1 (M-1} ) are formed in a pattern on the intermediate insulating layer IN _M. An upper insulating layer IN _T called passivation is formed on the upper metal layers CL _{1 (M-1)} and CN _{1 (M-1)} . Here, the silicon layer electrically floated at positions serving as the capacitors C between the lower metal layers VE ₁ and VE ₂ and the upper metal layers CL _{1 (M-1)} and CL _{2 (M-1)} . The protruding pattern PR is present.

The capacitors C may include lines connecting the sources of the first transistors TR2 and the gates of the second transistors TR2 to each other (CL _{1 (M-1)} and CL _{2 (M− in} FIG. 3 ₎ . ₁₎ ) and the bias lines VE ₁ ,..., VE _N to increase the operating speed of the second transistors TR2. In FIG. 3, reference numerals CN _{1 (M-1} and CN _{2 (M-1))} are lines connecting the drains of the second transistors TR2 and the bias lines VE ₁ ,..., VE _N to each other. admit.

The silicon layers TR2 and PR including the protruding pattern PR may include p-doped p-type impurities when the first and second transistors TR1 and TR2 are P-channel type. as the source and drain are formed, are a number of doping when the N- channel type (n-channel type) n-type ^{impurity-type} semiconductor (p ⁺⁾ or p-type impurities are less-doped p-type semiconductor (p) Sources and drains are formed with an n-type semiconductor (n ⁺ ) or an n-type semiconductor (n ⁻ ) doped with less n-type impurities.

In all the layers above the silicon layer, the lower metal layers VE ₁ , VE ₂ and the upper metal layers CL _{1 (M-1)} and CL _{2 (M− )} due to the projected pattern PR of the electrically floating silicon layer. ₁₎ bent shape, for example, uneven shape at the positions acting as the capacitors C between). Accordingly, since the capacitance increases as the electrode opposing areas of the capacitors C increase, the operating speed of the transistors TR1 and TR2 and thus the operating speed of the electroluminescent display panel can be improved.

As described with reference to FIGS. 1, 2, and 3, scan lines GE ₁ , ..., GE _N included in the lower metal layer and data lines DE ₁ , ... included in the upper metal layer. , DE _M ) are formed to cross each other. In addition, the bias lines VE ₁ ,..., VE _N included in the lower metal layer are formed side by side with respect to the scan lines GE ₁ ,..., GE _N. The first field effect transistors TR1 including the silicon layer are driven by the scan lines GE ₁ ,..., GE _N and the data lines DE ₁ ,..., DE _M. The second field effect transistors TR2 including the silicon layer may have a voltage Vdd applied to the bias lines VE ₁ ,..., And VE _N according to an operating state of each of the first field effect transistors TR1. ) Is selectively supplied to the cell electrodes CE ₁₁ ,..., CE _NM included in the lower metal layer.

Drains of the first field effect transistors TR1 are respectively connected to the data lines DE ₁ ,..., DE _M included in the upper metal layer. Gates of the first field effect transistors TR1 are respectively connected to scan lines GE ₁ ,..., GE _N included in the lower metal layer. Sources of the first field effect transistors TR1 are connected to gates of the second field effect transistors TR2, respectively. Drains of the second field effect transistors TR2 are respectively connected to the bias lines VE ₁ ,..., VE _N included in the lower metal layer. Sources of the second field effect transistors TR2 are connected to the cell electrodes CE ₁₁ ,..., CE _NM included in the lower metal layer, respectively.

As described above, according to the electroluminescent display panel according to the present invention, in all the layers on the silicon layer, the lower metal layer (VE ₁ , VE ₂ ) due to the protrusion pattern PR of the electrically floating silicon layer. And a bent shape, for example, an uneven shape, at positions serving as the capacitors C between the upper metal layers CL _{1 (M-1)} and CL _{2 (M-1)} . Accordingly, since the capacitance increases as the electrode opposing areas of the capacitors C increase, the operating speed of the transistors TR1 and TR2 and thus the operating speed of the electroluminescent display panel can be improved.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the appended claims.

Claims (2)

A substrate, a silicon layer formed according to a pattern on the substrate, a lower insulating layer formed on the silicon layer, a lower metal layer formed according to a pattern on the lower insulating layer, an intermediate insulating layer formed on the lower metal layer, and a pattern on the intermediate insulating layer An electroluminescent display panel comprising an upper metal layer formed and an upper insulating layer formed on the upper metal layer. And a protruding pattern of the silicon layer electrically floating at positions serving as capacitors between the lower metal layer and the upper metal layer. The method of claim 1, wherein in all layers above the silicon layer: And a bent shape at positions acting as capacitors between the lower metal layer and the upper metal layer due to the protruding pattern of the electrically floating silicon layer.