KR100581853B1 - Electroluminescent display panel wherein bias lines are common - Google Patents

Abstract

In the electroluminescent display panel according to the present invention, scan lines and data lines are formed to cross, bias lines are formed parallel to the scan lines, and the first transistors are driven by the scan lines and the data lines. The second transistors are electroluminescent display panels for selectively supplying voltages applied to the bias lines to the cell electrodes according to operating states of the first transistors. Here, each of the bias lines is positioned between the pair of scan lines to apply a bias voltage to the second transistors corresponding to the pair of scan lines.

Description

Electroluminescent display panel where bias lines are common}

1 is a block diagram illustrating a conventional electroluminescent display device.

2 is a view showing the structure of a display panel of the device of FIG.

FIG. 3 is a plan view illustrating a structure of two adjacent cells up and down of the panel of FIG. 2.

4 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a structure of a display panel of the apparatus of FIG. 4.

FIG. 6 is a plan view illustrating a structure of two up and down adjacent cells of the panel of FIG. 5.

<Explanation of symbols for the main parts of the drawings>

S _D ... display data signal, S _T ... clock signal,

S _DD ... display pattern signal, S _DT ... synchronous signal,

1, 5 ... control logic circuit, 2, 6 ... biasing circuit,

3, 7 ... switching circuit, 4, 8 ... electroluminescent display panel,

GE ₁ , ..., GE _N ... scanning lines, DE ₁ , ..., DE _M ... data lines,

VE ₁ , ..., VE _N ... bias lines, CE ₁₁ , ..., CE _NM ... cell electrodes,

Vdd ... bias voltage, DC ₁₁ , ..., DC _NM ... cell regions,

TR1 ... first transistors, TR2 ... second transistors,

C ... capacitors.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroluminescent display panel, and more particularly, to an electroluminescent display panel that generates light by applying an electric field to an organic light-emitting body.

The electroluminescent display panel is driven by an electric field applied to the organic light emitting body of the selected cell. Herein, the organic light emitter is in an electrical breakdown state, where light is generated from the excited light emitting material while the breakdown current flows.

Referring to FIG. 1, a conventional electroluminescent display device includes an electroluminescent display panel 4 and a control logic circuit 1, a biasing circuit 2, and a switching circuit 3 for driving the electroluminescent display panel 4.

In the conventional electroluminescent display panel 4, scan lines GE ₁ , ..., GE _N and data lines DE ₁ , ..., DE _M are formed to intersect, and bias lines (VE ₁ , ..., VE _N ) are formed side by side with respect to scan lines GE ₁ , ..., GE _N. Here, each scan line GE ₁ ,..., GE _N and each bias line VE ₁ ,..., VE _N correspond to one-to-one (1: 1). Reference signs CE ₁₁ , ..., CE _NM indicate respective cell electrodes. The structure and operation of this conventional electroluminescent display panel 4 will be described in more detail with reference to FIGS. 2 and 3.

Control logic circuit (1), the process receives the display data signal (S _D) and a clock signal (S _T) from the outside, and applies a display pattern signal (S _DD), the biasing circuit 2, the switching The synchronization signal S _DT is applied to the circuit 3. Accordingly, the biasing circuit 2 drives the data lines DE ₁ ,..., And DE _M , and the switching circuit 3 drives the scan lines GE ₁ ,..., GE _N. do. A voltage Vdd to be supplied to the selected cell electrodes CE ₁₁ ,..., And CE _NM is applied to the bias lines VE ₁ ,..., And VE _N.

FIG. 2 shows the structure of the electroluminescent display panel 4 of the device of FIG. 1. FIG. 3 shows the structure of two adjacent cells up and down of the panel of FIG. 2. In Figs. 2 and 3, the same reference numerals as those in Fig. 1 indicate the objects of the same function. In FIG. 2, reference numerals DC ₁₁ , ..., DC _NM indicate cell regions. In FIG. 2, reference numeral C denotes capacitors connected between the gates and the drains of the second transistors TR2. The capacitors C include the gate lines CL _{1 (M-1)} and CL _{2 (M-1) of} the second transistors TR2 and the bias lines VE ₁ ,... , VE _N , to drive the second transistors TR2. In FIG. 3, the reference sign W indicates the width of each bias line VE ₁ ,..., VE _N as a lower metal line. In FIG. 3, reference numeral D denotes a gap between each bias line VE ₁ ,..., VE _N and each cell electrode CE ₁₁ ,..., CE _NM .

2 and 3, the drains of the first field effect transistors TR1 are connected to the data lines DE ₁ ,..., And DE _M , respectively. Gates Gates of the first field effect transistors TR1 are connected to the scan lines GE ₁ ,..., GE _N , respectively. Sources of the first field effect transistors TR1 are connected to gates of the second field effect transistors TR2, respectively. Drains of the second field effect transistors TR2 are respectively connected to the bias lines VE ₁ ,..., VE _N. Sources of the second field effect transistors TR2 are respectively connected to the cell electrodes CE ₁₁ ,..., CE _NM . Here, n (n is an integer of 2 or more) scan lines GE ₁ , ..., GE _N and n (n is an integer of 2 or more) and bias lines VE ₁ , ..., VE _N Respond one-to-one (1: 1).

The first field effect transistors TR1 are driven by the scan lines GE ₁ ,..., GE _N and the data lines DE ₁ ,..., DE _M. The second field effect transistors TR2 apply the voltage Vdd applied to the bias lines VE ₁ ,..., And VE _N according to an operating state of each of the first field effect transistors TR1. Optionally supplied to (CE ₁₁ , ..., CE _NM ).

According to the conventional electroluminescent display panel 4 as described above, n (n is an integer of 2 or more) scan lines GE ₁ , ..., GE _N and n (n is an integer of 2 or more) bias lines Since VE ₁ ,..., VE _N correspond one-to-one (1: 1), there are the following problems.

First, many gaps D between each bias line VE ₁ ,..., VE _N and each cell electrode CE ₁₁ ,..., CE _NM are required. Because, when n (n is an integer of 2 or more) scan lines GE ₁ ,..., GE _N , each bias line VE ₁ ,..., VE _N and each cell electrode This is because the intervals D between (CE ₁₁ ,..., CE _NM ) are needed n−1. Accordingly, the area occupied by the cell electrodes CE ₁₁ ,..., CE _NM is relatively narrowed, resulting in a deterioration in luminance performance according to the aperture ratio.

Second, each of the bias line width (W) of _{(VE 1, ..., VE N} ) is therefore relatively narrow, each bias line resistance deterioration is large, the image quality of the _{(VE 1, ..., VE N} ) Has a problem.

An object of the present invention is to provide an electroluminescent display panel capable of improving luminance performance and image quality.

In the electroluminescent display panel of the present invention for achieving the above object, the scan lines and the data lines are formed to cross, the bias lines are formed side by side with respect to the scan lines, the first transistors and the data A display panel is driven by lines, and second transistors selectively supply voltages applied to the bias lines to cell electrodes according to operating states of the first transistors. Here, each of the bias lines is positioned between a pair of scan lines to apply a bias voltage to the second transistors corresponding to the pair of scan lines. Accordingly, the following effects can be obtained.

First, since the number of bias lines is cut in half, the number of gaps between patterns can be reduced. As a result, the area occupied by the cell electrodes is relatively widened, thereby improving luminance performance according to the aperture ratio.

Second, since the width of each bias line can be relatively wide, the resistance of each bias line can be reduced to improve image quality.

Hereinafter, preferred embodiments of the present invention will be described in detail.

Referring to FIG. 4, an electroluminescent display device according to an embodiment of the present invention includes an electroluminescent display panel 8 and a control logic circuit 5, a biasing circuit 6, and a switching circuit 7 for driving the electroluminescent display panel 8. Include.

In the electroluminescent display panel 8 according to the present invention, the scan lines GE ₁ , ..., GE _N and the data lines DE ₁ , ..., DE _M are formed to cross each other, and a bias is provided. Lines VE ₁ ,..., VE _{N / 2} are formed side by side with respect to scan lines GE ₁ ,..., GE _N. Here, each of the bias lines VE ₁ ,..., VE _{N / 2} is positioned between a pair of scan lines GE _1- GE ₂ ,..., GE _N-1 -GE _N. A bias voltage is applied to the second transistors TR2 corresponding to the pair of scan lines. That is, n (n is an integer of 2 or more) scan lines GE ₁ , ..., GE _N and n / 2 (n is an integer of 2 or more) and bias lines VE ₁ , ..., VE _N ) Corresponds one-to-one (2: 1). Reference signs CE ₁₁ , ..., CE _NM indicate respective cell electrodes. The structure and operation of this electroluminescent display panel 8 will be described in more detail with reference to FIGS. 5 and 6.

Control logic circuit 5, the processing receives the display data signal (S _D) and a clock signal (S _T) from the outside, and applies a display pattern signal (S _DD), a biasing circuit 6, switching The synchronization signal S _DT is applied to the circuit 7. Accordingly, the biasing circuit 6 drives the data lines DE ₁ ,..., And DE _M , and the switching circuit 7 drives the scan lines GE ₁ ,..., GE _N. do. A voltage Vdd to be supplied to the selected cell electrodes CE ₁₁ ,..., And CE _NM is applied to the bias lines VE ₁ ,..., And VE _{N / 2} .

5 shows the structure of the display panel 8 of the device of FIG. 4. FIG. 6 shows the structure of two up and down adjacent cells of panel 8 of FIG. 5. In Figs. 5 and 6, the same reference numerals as in Fig. 4 indicate the objects of the same function. In FIG. 5, reference numerals DC ₁₁ , ..., DC _NM indicate cell regions. In FIG. 5, reference numeral C denotes capacitors connected between the gates and the drains of the second transistors TR2. The capacitors C include the gate lines CL _{1 (M-1)} and CL _{2 (M-1) of} the second transistors TR2 and the bias lines VE ₁ ,... , VE _{N / 2} ) to drive the second transistors TR2. In FIG. 6, reference numeral 2W indicates the width of each bias line VE ₁ ,..., VE _{N / 2} as a lower metal line.

5 and 6, the drains of the first field effect transistors TR1 are connected to the data lines DE ₁ ,..., And DE _M , respectively. Gates Gates of the first field effect transistors TR1 are connected to the scan lines GE ₁ ,..., GE _N , respectively. Sources of the first field effect transistors TR1 are connected to gates of the second field effect transistors TR2, respectively. Drains of the second field effect transistors TR2 are respectively connected to the bias lines VE ₁ ,..., VE _{N / 2} . Sources of the second field effect transistors TR2 are respectively connected to the cell electrodes CE ₁₁ ,..., CE _NM . Here, n (n is an integer of 2 or more) scan lines GE ₁ , ..., GE _N and n / 2 (n is an integer of 2 or more) and bias lines VE ₁ , ..., VE _N ) Corresponds to Lee Dae-il (2: 1).

The first field effect transistors TR1 are driven by the scan lines GE ₁ ,..., GE _N and the data lines DE ₁ ,..., DE _M. The second field effect transistors TR2 may store a voltage Vdd applied to the bias lines VE ₁ ,..., And VE _{N / 2} according to an operating state of each of the first field effect transistors TR1. It selectively supplies to the electrodes CE ₁₁ ,..., CE _NM .

As described above, according to the electroluminescent display panel 8 according to the present invention, each of the bias lines VE ₁ ,..., VE _{N / 2} has a pair of scanning lines GE ₁ -GE _2. , ..., a pair of scanning lines disposed between _{GE N-1 -GE N) (} GE 1 -GE 2, ..., the second transistor corresponding to _N-1 GE -GE _N) ( The bias voltage Vdd is applied to TR2). Accordingly, the following effects can be obtained.

First, since the number of bias lines VE ₁ ,..., VE _{N / 2} is reduced by half, the number of gaps between patterns can be reduced. Accordingly, the area occupied by the cell electrodes CE ₁₁ ,..., And CE _NM is relatively widened, thereby improving luminance performance according to the aperture ratio.

Second, each of the bias lines _{(VE 1, ..., VE N} / 2) wide and may be relatively wide, each of the bias lines _{(VE 1, ..., VE N} / 2) reducing the resistance of the The picture quality can be improved.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the appended claims.

Claims (3)

Scan lines and data lines are formed to cross, bias lines are formed parallel to the scan lines, first transistors are driven by the scan lines and data lines, and second transistors are formed on the first line. An electroluminescent display panel for selectively supplying voltages applied to the bias lines to cell electrodes according to operating states of transistors, And each of the bias lines are positioned between a pair of scan lines to apply a bias voltage to the second transistors corresponding to the pair of scan lines. The method of claim 1, And said first and second transistors are field effect transistors. The method of claim 2, Drains of the first transistors are respectively connected to the data lines, gates of the first transistors are respectively connected to the scan lines, sources of the first transistors are respectively connected to gates of the second transistors, and And drains of the second transistors are respectively connected to the bias lines, and sources of the second transistors are respectively connected to the cell electrodes.

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