KR20040024363A - Plasma Display Panel And Apparatus and Method For Driving Thereof - Google Patents

Abstract

PURPOSE: A plasma display panel, an apparatus and a method for driving the same are provided to prevent the undesired light during the reset period by controlling the divided ferroelectric liquid crystal(FLC) during the reset period and the address period as well as to improve the contrast thereof. CONSTITUTION: A plasma display panel includes a plurality of scan electrodes(44), a plurality of sustain electrodes(46), a plurality of address electrodes(52) and a liquid panel(60). The liquid panel(60) includes a top electrode(60a), a ferroelectric liquid crystal(FLC) and at least one bottom electrode(60c). The liquid panel(60) is capable of blocking the light from the plasma display panel by controlling the orientation of the FLC. The plasma display panel is characterized in that the bottom electrode(60c) is formed a predetermined region of the plurality of the scan electrodes(44) so as to drive the FLC by the voltage difference between the top electrode(60a) and the bottom electrode(60c).

Description

Plasma Display Panel And Apparatus and Method For Driving Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel, a driving apparatus, and a method thereof, by employing ferroelectric liquid crystals to improve contrast.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. The PDP normally displays an image by adjusting the discharge period of each pixel in accordance with digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 is a perspective view illustrating a discharge cell structure typically arranged in an alternating-type PDP in a matrix form, and FIG. 2 is a cross-sectional view of the discharge cell shown in FIG. 1.

1 and 2, a PDP cell includes an upper plate having sustain electrode pairs 14 and 16, an upper dielectric layer 18, and a passivation layer 20 sequentially formed on an upper substrate 10, and a lower substrate 12. ), A lower plate having an address electrode 22, a lower dielectric layer 24, a partition wall 26, and a phosphor layer 28 formed sequentially. The upper substrate 10 and the lower substrate 12 are spaced in parallel by the partition wall 26. Each of the sustain electrode pairs 14 and 16 has a relatively wide width and a relatively narrow transparent electrode 14A and 16A made of a transparent electrode material (ITO) having a light transmittance of 90% or more, as shown in FIG. Made of metal electrodes 14B and 16B having a width. Here, the transparent electrode material (ITO) has a large resistance value and thus does not transmit power efficiently. Therefore, the resistive components of the transparent electrodes 14A and 16A are formed on the transparent electrodes 14A and 16A by forming metals 14B and 16B having a good conductivity, for example, silver (Ag) or copper (Cu). To compensate. The sustain electrode pairs 14 and 16 are composed of a scan electrode and a sustain electrode. The scan signal for the panel scan and the sustain signal for maintaining the discharge are mainly supplied to the scan electrode 14, and the sustain signal is mainly supplied to the sustain electrode 16. Charges accumulate in the upper dielectric layer 18 and the lower dielectric layer 24. The protective film 20 prevents damage to the upper dielectric layer 18 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 20, magnesium oxide (MgO) is usually used. The address electrode 22 is formed to cross the sustain electrode pairs 14 and 16. The address electrode 22 is supplied with a data signal for selecting cells to be displayed. The partition wall 26 is formed in parallel with the address electrode 22 to prevent ultraviolet rays generated by the discharge from leaking to adjacent cells. The phosphor layer 28 is applied to the surfaces of the lower dielectric layer 24 and the partition wall 26 to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

The PDP discharge cell is selected by the counter discharge between the address electrode 22 and the scan electrode 14, and then sustains the discharge by the surface discharge between the sustain electrode pairs 14 and 16. In the discharge cell, the fluorescent substance 28 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted to the outside of the cell. As a result, the PDP having the discharge cells displays an image. In this case, the PDP implements a gray scale required for displaying an image by adjusting the discharge sustain period of the discharge cell, that is, the number of sustain discharges according to the video data.

The AC surface discharge type PDP is driven by being divided into a plurality of subfields in order to express gray scale of an image, and in each subfield period, gradation display is performed by performing light emission in proportion to the weight of video data. do. For example, as shown in FIG. 3, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell is It is divided into eight subfields SF1 to SF8. Each of the subfields SF1 to SF8 is further divided into a reset period, an address period and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is such that the discharge is maintained in the discharge cell in which the address discharge has occurred. It is a period. The reset period and the address period are equally allocated to each subfield period.

4 is a waveform diagram illustrating a method of driving a PDP according to the prior art.

Referring to FIG. 4, the reset pulse RP is supplied to the scan electrode Y in the reset period RPD of all the subfields SF1 to SF8. The reset pulse RP has a form of ramp wave in which the voltage increases when set up and the voltage decreases when set down. A reset discharge occurs during setup to form wall charges in the upper dielectric layer 14. Subsequently, the charged voltage is partially erased by the decreasing voltage during set down so that the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, a positive DC voltage is supplied to the sustain electrode Z when the reset pulse RP is set down. Since the reset pulse RP is supplied in a gradually decreasing form with respect to the positive DC voltage, the scan electrode Y becomes a negative polarity relative to the sustain electrode Z at the time of set down, that is, the polarity is reduced. This inversion reduces the wall charges generated during setup.

In the address period APD, the scan pulse SP having the negative scan voltage Vy is supplied to the scan electrode Y, and the data pulse DP corresponding to the address voltage Va is applied to the address electrode X. Is supplied to generate an address discharge. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

The triggering pulse TP is supplied to the scan electrode Y at the beginning of the sustain period SPD to start the sustain discharge in the discharge cells 1 in which wall charges are sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy corresponding to the sustain voltage Vs are alternately supplied to the sustain electrode Z and the scan electrode Y to maintain the sustain discharge during the sustain period SPD.

In the erase period EPD subsequent to the sustain period SPD, the discharge pulse EP is supplied to the sustain electrode Z to stop the discharge. The erasing pulse EP has a ramp wave shape so that the light emission size is small, or a short pulse width of about 1 ms for the discharge erasing. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

In the PDP driving in this manner, white light emission should occur over all the discharge cells in order to accumulate charges in the discharge cells during the reset period and the address period, resulting in the contrast of the image falling. . In addition, a problem arises in that contour noise, which is outlined by bit noise, is generated due to the difference in brightness between fields in gray scale expression.

Accordingly, it is an object of the present invention to provide a plasma display device and a driving method thereof that can improve contrast by employing ferroelectric liquid crystals.

Another object of the present invention is to provide a plasma display device and a driving method thereof for patterning ferroelectric liquid crystals corresponding to discharge cells of a plasma display panel.

It is still another object of the present invention to provide a plasma display device and a driving method thereof in which contrast can be improved by controlling on / off of a patterned ferroelectric liquid crystal.

1 is a perspective view showing a discharge cell of a conventional three-electrode AC surface discharge plasma display panel.

FIG. 2 is a cross-sectional view of the plasma display panel shown in FIG. 1. FIG.

3 is a view illustrating a method of driving the plasma display panel shown in FIG. 1;

4 is a driving waveform diagram of the plasma display panel shown in FIG. 1;

5 illustrates a plasma display panel employing a ferroelectric liquid crystal (FLC) according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a plan view of the PDP illustrated in FIG. 5.

7 is a view for explaining the driving of the liquid crystal panel 60 shown in FIG.

FIG. 8 is a diagram illustrating a driving method according to the PDP shown in FIG. 6.

9 is a view showing a driving device of a PDP according to an embodiment of the present invention.

10 is a diagram illustrating a method of driving a PDP according to a second embodiment of the present invention.

11 is a diagram showing a PDP structure according to the third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 40: upper substrate 12, 42: lower substrate

14, 44: scan electrode 16, 46: sustain electrode

18, 48: upper dielectric layer 20, 50: protective film

22, 52: address electrode 24, 54: lower dielectric layer

26, 56: partition wall 28, 58: phosphor layer

60: liquid crystal panel 71: input line

72: reverse gamma correction unit 74: gain adjustment unit

76: error diffusion unit 78: subfield mapping unit

80: data output circuit section 82: APL control section

84: memory 86: data alignment unit

88: data driver

In order to achieve the above objects, a plasma display panel employing a ferroelectric liquid crystal according to the present invention has a reset period for initializing a cell, an address period for selecting the cell, and a sustain for displaying the selected cell. A plasma display panel including a plurality of scan electrodes, sustain electrodes and address electrodes to display an image divided into a plurality of subfields each including a period, and a ferroelectric liquid crystal are injected to control an arrangement state of the ferroelectric liquid crystal. A liquid crystal panel which blocks light from the plasma display panel; The liquid crystal panel includes at least one lower electrode facing the upper electrode and patterned to cover a predetermined region of the plurality of scan electrodes to drive the ferroelectric liquid crystal by a voltage difference between the upper electrode and the upper electrode. It is characterized by including.

The lower electrodes of the present invention are characterized by dividing the entire screen of the plasma display panel into two regions.

The lower electrodes of the present invention may be patterned to be located in each discharge cell region including the scan electrodes.

In the method of driving a plasma display panel according to the present invention, a discharge cell is provided at each intersection of a plurality of scan electrodes, sustain electrodes, and address electrodes, and a reset period for initializing the discharge cells within one frame period is performed. A plasma having a ferroelectric liquid crystal panel patterned to correspond to at least one scan electrode area on a plasma display panel having a plurality of subfields including an address period for selection and a sustain period for causing display discharge for the cell. A method of driving a display panel, the method comprising: controlling the ferroelectric liquid crystal to be synchronized with a reset period for initializing a cell within one frame period, thereby blocking light from the plasma display panel due to a reset discharge. .

The present invention may further include controlling the ferroelectric liquid crystal in the address period to block light from the plasma display panel due to the address discharge.

The sustain period in the present invention is characterized in that it comprises the step of passing the light by the sustain discharge by controlling the ferroelectric liquid crystal.

The scan electrode regions corresponding to the patterned ferroelectric liquid crystal panel according to the present invention may have different subfield configurations.

One of the scan electrode regions of the present invention has a subfield structure arranged in order from a subfield having a minimum bit to a subfield having a highest bit.

The other one of the scan electrode regions of the present invention has a subfield configuration in which a subfield having the highest bit is arranged first, and then the subfield having the minimum bit is arranged from the subfield having the highest bit to the previous subfield. It is done.

The scan electrode region of the present invention is divided into the same channel as the scan electrodes in the plasma display panel.

The patterned ferroelectric liquid crystal panel according to the present invention is characterized in that it is linked to the driving of the scan electrodes in the scan electrode region.

A driving apparatus of a plasma display panel according to the present invention includes: a subfield mapping unit for reassigning video data supplied to the outside for each subfield; And a data output circuit unit for controlling the output order of the video data allocated for each subfield, and a data alignment unit for aligning and supplying the video data according to the controlled output order to the panel.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 and 11.

5 is a diagram illustrating a plasma display panel employing a ferroelectric liquid crystal (FLC) according to an embodiment of the present invention.

Referring to FIG. 5, a plasma display device employing a ferroelectric liquid crystal (FLC) according to an exemplary embodiment of the present invention may include a PDP, a top surface of the PDP, and a ferroelectric liquid crystal (hereinafter referred to as “FLC”, 60b). And a liquid crystal panel 60 to be driven.

The PDP includes a plurality of discharge cells arranged in a matrix form, and the plurality of discharge cells may include the pair of sustain electrodes 44 and 46, the upper dielectric layer 48, and the passivation layer 50 formed side by side on the upper substrate 40. And a lower plate having an address electrode 52, a lower dielectric layer 54, a partition wall (not shown), and a phosphor layer (not shown) sequentially formed on the lower substrate 56. Each of the sustain electrode pairs 44 and 46 has a relatively wide width and transparent electrodes 44A and 46A made of a transparent electrode material (ITO) having a light transmittance of 90% or more, and metal electrodes having a relatively narrow width. And 44B and 46B. Here, the transparent electrode material (ITO) has a large resistance value and thus does not transmit power efficiently. Accordingly, the resistance of the transparent electrodes 44A and 46A is formed on the transparent electrodes 44A and 46A by forming metal electrodes 44B and 46B made of a highly conductive material, for example, silver (Ag) or copper (Cu). Compensate for the ingredients. The sustain electrode pairs 44 and 46 are composed of a scan electrode and a sustain electrode. The scan signal for scanning the panel and the sustain signal for maintaining the discharge are mainly supplied to the scan electrode 44, and the sustain signal is mainly supplied to the sustain electrode 46. Charges are accumulated in the upper dielectric layer 48 and the lower dielectric layer 54. The passivation layer 50 prevents damage to the upper dielectric layer 48 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 50, magnesium oxide (MgO) is usually used. The address electrode 52 is formed to cross the sustain electrode pairs 44 and 46. The address electrode 52 is supplied with a data signal for selecting cells to be displayed. The partition wall is formed in parallel with the address electrode 52 to prevent the ultraviolet rays generated by the discharge from leaking to the adjacent cells. The phosphor layer is applied to the surface of the lower dielectric layer 54 and the partition wall to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

The liquid crystal panel 60 includes an upper electrode 60a supplied with a common voltage, a lower electrode 60c supplied with the pixel voltage, and an FLC 60b injected between the upper electrode 60a and the lower electrode 60c. It is composed of In this case, the upper electrode 60a forms a single substrate to correspond to the front panel of the PDP. In the present invention, the lower electrode 60c corresponds to groups formed by gathering a plurality of scan electrodes, unlike the upper electrode 60a. Is patterned. The liquid crystal panel 60 controls the amount of light according to the arrangement state of the FLC 60b to display a desired image on the screen. To this end, the FLC 60b changes the liquid crystal arrangement state according to the voltage difference between the upper electrode 60a and the lower electrode 60c and serves to block or transmit light. According to the light transmission and blocking of the liquid crystal panel 60, the amount of light generated between the upper and lower plates can be controlled. At this time, the FLC 60b used in the liquid crystal panel 60 rotates along the smectic layer forming the layer structure of the region having the same electrical and magnetic properties, that is, drawing the outline of the virtual cone. FLC (60b) is a liquid crystal that has a spontaneous polarization characteristic regardless of an external electric field. Its response speed is considerably faster than that of other modes, and a wide viewing angle can be achieved without using a special electrode structure or compensation film. Has

The PDP maintains the discharge by the surface discharge between the sustain electrode pairs 44 and 46 after the cell is selected by the opposite discharge between the address electrode 52 and the scan electrode 44. In the PDP cell, the fluorescent material 58 emits light by ultraviolet rays generated during sustain discharge, and visible light is emitted to the outside of the cell. The emitted visible light is controlled by the FLC 60b of the liquid crystal panel 60. In other words, an image is displayed by blocking and controlling the light generated by the plasma discharge. In this case, the PDP adjusts the number of discharge sustain periods of the cell according to the video data and implements gray scale by using on / off characteristics of the FLC 60c.

FIG. 6 is a plan view of the PDP shown in FIG. 5, and FIG. 7 is a view for explaining driving of the liquid crystal panel 60 shown in FIG. 5.

6 and 7, the PDP employing the ferroelectric liquid crystal according to the present invention divides and groups a plurality of scan electrodes arranged in the PDP and then groups the lower electrodes of the liquid crystal panel 60 to correspond to the scan electrode group region. It characterized by patterning 60c.

In the configuration as described above, the PDP according to the present invention may apply an independent voltage in accordance with the driving of the scan electrodes. Therefore, when driving the upper scan electrodes, the driving voltage Y _FLC1 is applied to the lower substrate 60c of the liquid crystal panel 60 corresponding to the upper scan electrodes to transmit light to the upper surface to display an image, and the lower scan. When driving the electrodes, the driving voltage Y _FLC2 is applied to the lower substrate 60c of the liquid crystal panel 60 corresponding to the lower scan electrodes to transmit light to the upper surface to display an image. Accordingly, the lower substrate 60c of the liquid crystal panel 60 patterned in the PDP according to the present invention may be driven in conjunction with the respective scan electrodes Y. FIG. In FIG. 7, Vtop represents a voltage capable of driving the ferroelectric liquid crystal FLC with respect to the scan electrodes Y. In FIG.

FIG. 8 is a diagram illustrating a driving method according to the PDP shown in FIG. 6.

Referring to FIG. 8, in order to drive the PDP driving method according to the present invention, first, the PDP is divided into two or more groups according to the grouping of scan electrodes, and in the case of FIG. 8, the PDP is divided into two groups. Has These groups are divided into eight subfields in one frame display period in each discharge cell in order to display an image in 256 gray scales using 8-bit video data as shown in FIG.

First, the PDP in the group A has the general subfield arrangement as shown in FIG. 3, and the PDP in the group B includes the first to n-1th subfields SF1 to SFn-1 after the nth subfield is first arranged. ) Are placed. As described above, when the group A operates with low gray level subfields arranged in the group A and drives the group B with high gray level subfields synchronized with the low gray level subfields in the group A, this occurs when there are many bit conversions. Contour noise can be prevented. In the liquid crystal panel employing ferroelectric liquid crystal in conjunction with the PDP driving, the gray scale from the PDP is displayed by controlling the FLC on / off.

In the lower substrate 60c of the liquid crystal panel, the FLC 60b is turned off by applying a high signal to be synchronized with the reset period RPD of each subfield, and the base signal in the address period APD and the sustain period SPD. The gray level is displayed by turning on the FLC 60b by applying. At this time, the reset period and the address period are equally allocated to each subfield period. Among these, in the reset period, light generated by reset discharge is generated in the entire panel irrespective of the address discharge, and this light is a main factor for lowering the contrast. Accordingly, the light generated in the PDP is blocked by turning off the FLC of the liquid crystal panel during the reset period. In addition, in the address period and the sustain period, the FLC is turned on to transmit light from the PDP. Accordingly, the PDP according to the present invention can block the unnecessary light during the reset period and can improve the contrast since the light during the reset period does not affect the address and the sustain period. In the present invention, the FLC 60b may be turned off by applying a high signal in synchronization with the reset period RPD and the address period APD of each subfield.

However, in order to use a different subfield map for each group, a PDP driving apparatus as shown in FIG. 9 is required.

Referring to FIG. 9, the driving apparatus of the PDP according to the present invention includes a first reverse gamma correction unit 72A and a gain adjusting unit connected between the input line 71 and the data driver 88 of a panel (not shown). 74, an error diffusion unit 76, a subfield mapping unit 78, a data output circuit unit 80, and a data alignment unit 86; A second inverse gamma correction unit 72B and an APL control unit 82 connected in parallel with the first inverse gamma correction unit 72A between the input line 71 and the gain adjustment unit 74; A memory 84 connected to the data alignment unit 86 is provided.

The first and second inverse gamma adjustment units 72A and 72B may inversely gamma correct video data from the input line 71 to linearly convert luminance values according to grayscale values of the image signal.

The APL control unit 82 detects an average brightness per frame of the image data input from the second inverse gamma adjustment unit 72B. On the other hand, the APL detected by the APL control unit 82 is input to a timing controller (not shown). The timing controller adjusts the number of sustain pulses by controlling a circuit for generating sustain pulses according to the APL.

The gain adjusting unit 74 adjusts gain by amplifying the red, green, and blue image data corrected by the first inverse gamma adjusting unit 72A by an effective gain. In addition, the gain adjusting unit 74 adjusts gain with respect to the red, green, and blue video data input from the first inverse gamma adjusting unit 72A in accordance with the APL detected by the APL control unit 82.

The error diffusion unit 76 finely adjusts the luminance value by diffusing an error component to adjacent cells with respect to the data from the gain adjustment unit 74. To this end, the error diffusion unit 76 divides the data into integer and fractional parts and multiplies the fractional part by a Floyd-Steinberg coefficient to spread error components in adjacent cells.

The subfield mapping unit 78 reassigns data input from the error diffusion unit 76 for each subfield, that is, maps the data according to a preset subfield pattern.

The data output circuit unit 80 controls the output of the input data so that each of the subfields of the data input from the subfield mapping unit 78 is first disposed among the subfields having the minimum and maximum bits. At this time, the video data controlled from the data output circuit unit 80 is supplied to the data alignment unit 86.

The data aligning unit 86 stores the video data input from the data output circuit unit 80 in the memory 84 and reads out the data stored in the memory 84 and supplies it to the data driver 88 of the PDP (not shown). . The data driver 88 of the PDP is implemented as an integrated circuit (IC) connected to each of the plurality of address electrode lines formed in the PDP, so that data input from the data alignment unit 44 is transferred to the address electrode lines of the PDP. Will be supplied.

The driving apparatus of the PDP having the configuration as described above can prevent the controller noise or the like by controlling the data output to the address electrode lines X corresponding to the scan electrode lines Y group.

FIG. 10 is a diagram illustrating a method of driving a PDP according to a second embodiment of the present invention, in which the entire screen is divided into four sections each at the top and bottom. Thus, when the total number of scan electrode lines of the PDP is 480 lines, the PDP using the liquid crystal panel employing ferroelectric liquid crystals (FLC) corresponding to 60 scan electrode lines may be driven by different subfield maps. In addition, each scan electrode group is arranged to alternate grays having the highest bit MSB and grays having the least bit LSB to prevent the controller noise.

FIG. 11 is a diagram illustrating a PDP structure according to a third embodiment of the present invention, in which the scan electrode lines of the front panel and the lower substrate of the ferroelectric liquid crystal panel are patterned one-to-one (1: 1). In such a configuration, since the driving voltages for these components are also connected to the scan electrodes Y, the voltage by the scan pulse SP can be used as it is. In addition, the PDP driving method by the selective erasing method may be employed. In the PDP driving method using the selective erasing method, since the light due to the address discharge is unnecessary, the contrast can be improved by turning off the FLC by the corresponding scan pulse voltage during the address discharge in each scan electrode line (Y). Can be.

As described above, the plasma display panel according to the present invention and its driving apparatus and method are reset by patterning and dividing the FLC formed on the upper surface of the PDP into two or more, and then controlling and turning off the divided FLC during the reset period and the address period, respectively. Contrast can be improved while blocking unnecessary light such as periods.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A plurality of scan electrodes to display an image by dividing one frame period into a plurality of subfields each including a reset period for initializing a cell, an address period for selecting the cell, and a sustain period for displaying the selected cell; A plasma display panel including sustain electrodes and address electrodes; A liquid crystal panel injecting ferroelectric liquid crystal and controlling the arrangement of the ferroelectric liquid crystal to block light from the plasma display panel; The liquid crystal panel, Upper electrode, And at least one lower electrode facing the upper electrode and patterned to cover a predetermined region of the plurality of scan electrodes to drive the ferroelectric liquid crystal by a voltage difference with the upper electrode. . The method of claim 1, The lower electrodes divide the entire screen of the plasma display panel into two regions. The method of claim 1, And the lower electrodes are patterned to be positioned at each discharge cell region including the scan electrodes, respectively. A discharge cell is provided for each of the crossing regions of the plurality of scan electrodes, the sustain electrodes, and the address electrodes, and a reset period for initializing the discharge cell within one frame period, an address period for selecting the cell, and a display for the cell A method of driving a plasma display panel having a ferroelectric liquid crystal panel patterned to correspond to at least one or more scan electrode regions on a plasma display panel having a plurality of subfields including a sustain period for causing a discharge, the method comprising: And controlling the ferroelectric liquid crystal to block light from the plasma display panel by a reset discharge so as to be synchronized with a reset period for initializing a cell within the one frame period. The method of claim 4, wherein And controlling the ferroelectric liquid crystal to block light from the plasma display panel due to the address discharge even in the address period. The method of claim 5, wherein And controlling the ferroelectric liquid crystal to pass the light by the sustain discharge in the sustain period. The method of claim 4, wherein And the scan electrode regions corresponding to the patterned ferroelectric liquid crystal panel have different subfield configurations. The method of claim 7, wherein Wherein one of the scan electrode regions has a subfield configuration arranged in order from a subfield having a minimum bit to a subfield having a highest bit. The method of claim 8, The other one of the scan electrode regions has a subfield configuration in which a subfield having the highest bit is disposed first and then arranged from a subfield having the minimum bit to a subfield before the subfield having the highest bit. How to drive the panel. The method of claim 9, And the subfield configurations are alternately applied to each of the scan electrode regions. The method of claim 5, wherein And the scan electrode area is divided into the same channel as the scan electrodes in the plasma display panel. The method of claim 11, And the patterned ferroelectric liquid crystal panel is linked to driving of scan electrodes in the corresponding scan electrodes region. A subfield mapping unit for reassigning video data supplied to the outside for each subfield; A data output circuit unit for controlling an output order of video data allocated for each subfield; And a data alignment unit for arranging and supplying video data according to the controlled output order to the panel.