KR100487001B1 - Driving Method of Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that can correct white balance and reduce discharge delay.

According to an exemplary embodiment of the present invention, a method of driving a plasma display panel includes supplying a first sustain pulse to a scan electrode during a sustain period, and pulse widths at address electrodes of blue, green, and red discharge cells immediately before a first sustain pulse rises. Supplying the different bias voltages, supplying and overlapping the second sustain pulses to the sustain electrodes in the period where the first sustain pulses maintain the high level, and immediately before the first sustain pulses are polled. And supplying bias voltages having different pulse widths to the address electrodes of the blue, green, and red discharge cells.

Description

Driving method of plasma display panel {Driving Method of Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel capable of correcting white balance and reducing discharge delay.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. The PDP normally displays an image by adjusting the discharge period of each pixel according to the digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 is a perspective view illustrating a cell structure typically arranged in an alternating current PDP in a matrix form, and FIG. 2 is a cross-sectional view of the PDP shown in FIG. 1. Here, the lower plate of the PDP shown in FIG. 2 shows a sectional view rotated by 90 degrees.

1 and 2, a PDP cell includes an upper plate having sustain electrode pairs 14 and 16, an upper dielectric layer 18, and a passivation layer 20 sequentially formed on an upper substrate 10, and a lower substrate 12. ), A lower plate having an address electrode 22, a lower dielectric layer 24, a partition wall 26, and a phosphor layer 28 formed sequentially.

Each of the sustain electrode pairs 14 and 16 has a relatively wide width and a transparent electrode 14A and 16A made of a transparent electrode material (ITO) having a light transmittance of 90% or more, and a metal electrode 14B having a relatively narrow width. , 16B). Here, the transparent electrode material (ITO) has a large resistance value and thus does not transmit power efficiently. Therefore, the resistive components of the transparent electrodes 14A and 16A are formed on the transparent electrodes 14A and 16A by forming metals 14B and 16B having a good conductivity, for example, silver (Ag) or copper (Cu). To compensate. The sustain electrode pairs 14 and 16 are composed of a scan electrode and a sustain electrode. The scan signal for the panel scan and the sustain signal for maintaining the discharge are mainly supplied to the scan electrode 14, and the sustain signal is mainly supplied to the sustain electrode 16. Charges accumulate in the upper dielectric layer 18 and the lower dielectric layer 24. The protective film 20 prevents damage to the upper dielectric layer 18 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 20, magnesium oxide (MgO) is usually used. The address electrode 22 is formed to cross the sustain electrode pairs 14 and 16. The address electrode 22 is supplied with a data signal for selecting cells to be displayed. The partition wall 26 is formed in parallel with the address electrode 22 to prevent ultraviolet rays generated by the discharge from leaking to adjacent cells. The phosphor layer 28 is applied to the surfaces of the lower dielectric layer 24 and the partition wall 26 to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

The PDP cell is selected by the counter discharge between the address electrode 22 and the scan electrode 14, and then sustains the discharge by the surface discharge between the sustain electrode pairs 14 and 16. In the PDP cell, the fluorescent substance 28 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted outside the cell. As a result, the PDP having cells displays an image. In this case, the PDP implements a gray scale required for displaying an image by adjusting the discharge sustain period of the cell, that is, the number of sustain discharges, according to the video data.

The AC surface discharge type PDP is driven by being divided into a plurality of subfields in order to express gray scale of an image, and in each subfield period, gradation display is performed by performing light emission in proportion to the weight of video data. do. For example, as shown in FIG. 3, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell is It is divided into eight subfields SF1 to SF8. Each of the subfields SF1 to SF8 is further divided into a reset period, an address period and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is such that the discharge is maintained in the discharge cell in which the address discharge has occurred. It is a period. The reset period and the address period are equally allocated to each subfield period.

FIG. 3 is a driving waveform diagram for driving the PDP shown in FIG. 1 for one subfield period, wherein Y, Z, and X are respectively provided for the scan electrode 14, the sustain electrode 16, and the address electrode 22. FIG. The driving waveform supplied is shown.

In the reset period RPD, the reset pulse RP is supplied to the scan electrode 14. The reset pulse RP has a form of ramp wave in which the voltage increases when set-up and the voltage decreases when set-down. During setup, a reset discharge is generated between the scan electrode 14 and the sustain electrode 16 to form wall charges in the upper dielectric layer 18. Subsequently, unnecessary charged particles are partially erased by the decreasing voltage during set down, and the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, the positive DC voltage Vs is supplied to the sustain electrode 16 in the set down period of the reset pulse RP. The reset pulse RP is gradually supplied to the positive DC voltage Vs so that the scan electrode 14 becomes negative in relation to the sustain electrode 16 during set down. In other words, the polarity is reversed so that the wall charges generated in the setup period are reduced. In this way, the reset discharge is generated by the supply of the reset pulse RP, and the wall charges necessary for the address discharge are formed in the cells of all the screens.

In the address period APD, the scan pulse SP is supplied to the scan electrode 14 and the data pulse DP is supplied to the address electrode 22 to generate an address discharge. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

The triggering pulse TP is supplied to the scan electrode 14 at the beginning of the sustain period SPD to start sustain discharge in the discharge cells 11 in which wall charges are sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy are alternately supplied to the sustain electrode 16 and the scan electrode 14 to maintain the sustain discharge during the sustain period SPD.

The erase period EPD is supplied with the erase pulse EP to the sustain electrode 16 following the sustain period SPD so that the discharge that has been sustained is stopped. In this case, the erasing pulse EP has a lamp wave shape in which the light emission size is small, and has a short pulse width of about 1 ms for erasing the discharge. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

In the PDP driven by this method, white light is made of phosphors of red (R), green (G), and blue (B), and the purity of white light is determined according to the characteristics of R and B. And how to harmonize the phosphor characteristics of B has been actively researched.

In particular, research on white valance correction has been made in PDP. As the luminous efficiencies of the R, G, and B phosphors are different from each other, white balance is generated. Here, the light emission efficiency of the R discharge cells is higher than the light emission efficiency of the G and B discharge cells, and the light emission efficiency of the G discharge cells is higher than the light emission efficiency of the B discharge cells. Accordingly, in the conventional PDP, the white balance is adjusted by adjusting the adjustment point to B having the lowest luminous efficiency to achieve color balance as a whole. For example, in order to adjust the white balance, the light emission rate is adjusted at a ratio of R: G: B = 0.9: 0.8: 1. Since the luminous efficiency of R and G phosphors is considered based on the B phosphor having the lowest luminous efficiency, the luminance level of R and G is adjusted downward to achieve overall color balance. As such, the white balance is corrected by focusing on B having low luminous efficiency, so that the luminance levels of R and G are not properly utilized unless the luminance of B is increased, resulting in a decrease in luminance level of the entire PDP. .

In addition, another method of correcting the white balance of the PDP is to take the size of the discharge cell asymmetrically in order to control the luminance intensity of the R, G, and B phosphors differently. In other words, since the luminance intensity is in the order of G> R> B, the application area of the phosphor is changed in the order of B> R> G in order to match the luminance intensity. Accordingly, as shown in FIG. 4, the size of the B discharge cell having the lowest luminance is the largest, followed by the size of the R discharge cell, and finally the size of the G discharge cell. As the size of the discharge cells is different, the coating areas of the R, G, and B phosphors are different, and thus the white balance can be corrected by varying the R, G, and B luminance intensities.

However, the method of making the size of the discharge cell asymmetric is an undesired method in the PDP that is directed to the HD class according to the trend of miniaturization of the discharge cell.

In addition, as a method of correcting the white balance of the PDP, the luminance change according to the pulse width of the data pulse supplied to the address electrode is used. This is shown well in the drive waveform diagram shown in FIG.

Referring to FIG. 5, another conventional PDP driving waveform supplies the data pulse D to the address electrode X at the start of the sustain period SPD. Subsequently, the first sustain pulse S1 is supplied to the scan electrode Y in synchronization with the time when the data pulse D is switched to the address electrode X. FIG. After the data pulse D is supplied to the address electrode X, the first sustain voltage level of the scan electrode Y is maintained until the zero potential is maintained. Thereafter, the zero potential 0V is supplied to the scan electrode Y, and the second sustain pulse S2 is supplied to the sustain electrode Z while the zero potential is maintained. The data pulse D is supplied to the address electrode X in synchronization with the start point of the second sustain pulse S2 supplied to the sustain electrode Z. The data pulse D is supplied to the address electrode X at each starting point of supplying the sustain pulse to the scan electrode Y and the sustain electrode Z. Thus, the address electrode X and the sustain electrode pair Y, Minimize mis-discharge between Z).

However, although the current white balance can be corrected to some extent as a driving method of the PDP, there is an urgent need for a driving method capable of correcting color balance better than the present.

Accordingly, an object of the present invention is to provide a method of driving a plasma display panel that can correct white balance and reduce discharge delay.

In order to achieve the above object, the driving method of the plasma display panel according to the present invention comprises the steps of supplying a first sustain pulse to the scan electrode during the sustain period, and a blue, green, red discharge just before the time when the first sustain pulse rises; Supplying a bias voltage having a different pulse width to an address electrode of a cell, supplying and overlapping a second sustain pulse to the sustain electrode while the first sustain pulse maintains a high level, and the first sustain And supplying bias voltages having different pulse widths to address electrodes of the blue, green, and red discharge cells immediately before the pulse is polled.

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The pulse width of the bias voltage may be increased in order of blue> green> red discharge cells.

As the pulse width of the bias voltage is increased, the color temperature is the largest at the low voltage.

The second sustain pulse may be maintained at a high level even after the first sustain pulse is applied to the scan electrode while the scan electrode maintains the low level voltage.

The sustain electrode maintains a low level voltage at the rising point of the first sustain pulse.

The scan electrode and the address electrode maintain a low level voltage at the time when the second sustain pulse is polled.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 11.

6 is a diagram illustrating a method of driving a PDP according to an embodiment of the present invention.

Referring to FIG. 6, the PDP driving method according to the present invention overlaps the first sustain pulse supplied to the scan electrode Y and the second sustain pulse supplied to the sustain electrode Z during the sustain period. It is done.

At the beginning of the sustain period, the trigger pulse T is supplied to the scan electrode Y, and then the trigger pulse T is supplied to the sustain electrode Z to sustain discharge to discharge cells having sufficiently wall charges in the address period. To be initiated. At this time, immediately before the trigger pulse T supplied to the scan electrode Y and the sustain electrode Z rises, the data pulse D is supplied to the address electrode X to strengthen the sustain discharge.

After the trigger pulse T is supplied to the sustain electrode Z, the first sustain pulse S1 is supplied to the scan electrode Y. The data pulse D is supplied to the address electrode X immediately before the first sustain pulse S1 rises, and the address electrode X immediately before the first sustain pulse S1 falls. Supply the data pulse (D). The second sustain pulse S2 is supplied to the sustain electrode Z while the first sustain pulse S1 maintains a high level. The second sustain pulse S2 maintains a high level until the scan electrode Y maintains a low level. In other words, the second sustain pulse S2 overlaps the first sustain pulse S1 and is supplied to the sustain electrode Z. The first and second sustain pulses S1 and S2 overlap each other until the discharge current starts oscillation after the discharge is completed. When the first and second sustain pulses S1 and S2 overlap, the current generated by the immediately preceding sustain pulse is not affected.

On the other hand, let's look at the reaction time of the discharge current according to the drive waveform of the PDP according to the present invention.

FIG. 7 is driven by the driving method of the PDP shown in FIG. 5, and when the address electrode X is supplied with three states, that is, the zero potential (0V) to the address electrode X (a), the address electrode X Is a floating state, the state of the discharge current I according to the condition of supplying a bias voltage to the address electrode X (c) is shown. When the zero potential (0V) is supplied to the address electrode X (a) and the address electrode X is in the floating state (b), the address electrode X is in the floating state (b). It can be seen that the response speed of the discharge current I is faster. In the case of supplying a bias voltage, for example, a data pulse D of about 70 V to the address electrode X, the response speed of the discharge current I is much faster than the above two cases. In other words, it can be seen that the response speed of the discharge current I is larger in the order of the bias voltage (70V)> zero potential (0V)> floating state. Here, it can be seen that it varies greatly depending on how and under what conditions the bias voltage D supplied to the address electrode X is supplied.

8 shows the reaction time of the discharge current according to the PDP driving waveforms of the prior art (a) and the invention (b) when the address electrode X is at zero potential (0V).

Referring to FIG. 8, the PDP of the present invention overlaps the first sustain pulse S1 and the second sustain pulse S2 supplied to the scan electrode Y, as can be seen from the PDP driving waveform of the present invention. It can be seen that the response time is faster than the discharge current (I) response time. As a result, it can be seen that the discharge delay is reduced on the overlap sustain pulse of the PDP of the present invention rather than the conventional PDP driving waveform. In other words, the discharge delay indicates that it is advantageous to use the overlap sustain pulse of the present invention rather than the conventional one.

In addition, the reaction time of the discharge current (I) according to the pulse width of the data pulse (D) supplied to the address electrode (X). For example, as shown in FIG. 9, the reaction time of the discharge current I in the case where the width of the data pulse D is 1.4 ㎲ (a) and 1.6 ((b) in the address electrode X is shown. As can be seen, when the width of the data pulse (D) is 1.6 ㎲ (b) it can be seen that the reaction time is faster. That is, it can be seen that the discharge delay is alleviated as the pulse width of the data pulse D increases. This bias time for surface The more while maintaining a constant bias as long as the discharge time is generated in the discharge surface the greater the pulse width of the data pulse (D) decreases the pulse width of the data pulse (D) held in the discharge is much shorter This is because the effect as a bias is lost quickly. Accordingly, it can be seen that the overlap sustain drive waveform of the present invention, rather than the conventional drive waveform diagram, alleviates the discharge delay, and the discharge delay is alleviated as the bias width of the data pulse is larger. It can be seen that the discharge delay can be alleviated by adjusting the pulse width of the data pulse D in the driving waveform of the present invention.

10 is a view showing a change in color temperature of the present invention and the conventional PDP. Here, reference-1.4㎲ represents a change in color temperature of the prior art, and New-1.4㎲ and New-1.6㎲ are data pulses D, that is, the bias voltages are 1.4 전압 and 1.6㎲. Shows the change in the color temperature of the PDP according to the present invention.

Referring to FIG. 10, it can be seen that the color temperature characteristic of the present invention is better than 60V, whereas the present invention exhibits the best color temperature characteristic of the bias voltage of 60V or less. In addition, it can be seen that the color temperature is larger at a lower voltage when the pulse width of the supplied bias voltage is 1.6 kHz than when the pulse width is 1.4 kHz. In other words, as the pulse width of the bias voltage increases, the color temperature becomes larger at low voltage, which means that the luminance intensity of the B phosphor which is the focus of the white balance can be increased.

Therefore, based on the color temperature of the pulse width of the data pulse, that is, whether the bias pulse width is wide or narrow in the driving waveform of the present invention, the applied bias pulse width is in the order of B> R> G, respectively. In consideration of the light emission characteristics of each phosphor, the white balance can be achieved while improving the luminance characteristics of B.

In addition, improving the luminance characteristic of B has the advantage of using the luminance characteristic of G more, and thus has the advantage of improving luminance while maintaining the color purity of white.

11 is a diagram showing the luminance in the prior art and the present invention.

Referring to FIG. 11, the brightness of the conventional PDP is better at a bias voltage of 60V or higher, whereas when the PDP driving method of the present invention is applied, the brightness of the present invention is best at a bias voltage of 60V or lower. You can see that it appears good. In addition, it can be seen that as the bias pulse width supplied to the address electrode X increases, the luminance increases at a low bias voltage. Here, as the luminance increases, the color temperature increases, so it can be seen that the increase in the color temperature does not cause the decrease of the luminance as shown in FIG. 10.

As described above, in the driving method of the plasma display panel according to the present invention, the white balance can be adjusted by differently forming the pulse widths of the data pulses supplied to the address electrodes for R, G, and B. In addition, the driving method of the plasma display panel according to the present invention can reduce the discharge delay to reduce the discharge delay.

Furthermore, the driving method of the plasma display panel according to the present invention can improve the color temperature characteristics, which can greatly affect product visibility.

In addition, the present invention has the advantage that the G luminance region can be used more widely than before, resulting in greater luminance on real driving.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a conventional three-electrode AC surface discharge plasma display panel.

FIG. 2 is a cross-sectional view illustrating the plasma display panel shown in FIG. 1. FIG.

3 is a driving waveform diagram of the plasma display panel shown in FIG. 1;

4 is a plan view of a plasma display panel for correcting white balance;

5 is a drive waveform diagram of another conventional plasma display panel;

6 is a driving waveform diagram illustrating a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 7 is a graph showing a reaction time of a discharge current according to a condition of an address electrode in the driving waveform diagram shown in FIG. 3.

8 is a graph showing the reaction time of the discharge current according to the driving waveform of the prior art and the present invention.

9 is a graph showing a reaction time of a discharge current according to the data pulse width shown in FIG. 6.

10 is a graph illustrating a change in color temperature according to a method of driving a plasma display panel.

11 is a graph showing luminance according to a method of driving a plasma display panel.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12: lower substrate

14 scanning electrode 16 sustaining electrode

18: upper dielectric layer 20: protective film

22: address electrode 24: lower dielectric layer

26: partition 28: phosphor layer

Claims (7)

Supplying a first sustain pulse to the scan electrode during the sustain period; Supplying bias voltages having different pulse widths to address electrodes of the blue, green, and red discharge cells immediately before the first sustain pulse rises; Supplying and overlapping a second sustain pulse to a sustain electrode in a period in which the first sustain pulse maintains a high level; And supplying bias voltages having different pulse widths to address electrodes of the blue, green, and red discharge cells immediately before the first sustain pulse is polled. delete The method of claim 1, And the size of the data pulse width is increased in the order of blue> green> red discharge cells. The method of claim 1, And the second sustain pulse maintains a high level even after the first sustain pulse is applied to the scan electrode even when the scan electrode maintains a low level voltage. The method of claim 1, And the color temperature is increased at a low voltage as the bias voltage pulse width increases. The method of claim 1, And the sustain electrode maintains a low level voltage at the rising point of the first sustain pulse. The method of claim 1, And the scan electrode and the address electrode maintain a low level voltage at the time when the second sustain pulse is polled.