KR20040022565A - Transistor Of Semiconductor Device And Method Of Fabricating The Same - Google Patents

Abstract

PURPOSE: A method for fabricating a transistor of a semiconductor device is provided to prevent a punch-through phenomenon by recessing the upper surface of a semiconductor substrate having a channel so that the lower surface of a gate oxide layer becomes lower than the upper surface of a junction region. CONSTITUTION: A shallow trench having a recessed upper surface is formed in a predetermined region of the semiconductor substrate(100). A gate pattern is formed on the shallow trench. An impurity region is formed in the semiconductor substrate in the periphery of the gate pattern. The semiconductor substrate under the gate pattern is lower than the upper surface of the impurity region.

Description

Transistor of Semiconductor Device and Manufacturing Method Thereof {Transistor Of Semiconductor Device And Method Of Fabricating The Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a transistor of a semiconductor device and a method of manufacturing the same.

As semiconductor devices become highly integrated, it is required to reduce the area of a unit cell in which metal-oxide-silicon (MOS) transistors are formed. In order to reduce the area of the unit cell, it is required to form the MOS transistors minutely. Such miniaturization of the MOS transistor is typically achieved through a method of thinly forming a gate electrode constituting the MOS transistor. On the other hand, as is known, when the gate electrode is thinly formed, a short channel effect is likely to occur which adversely affects the characteristics of the semiconductor device. As a method for minimizing such short channel effects, a technique of forming a junction region of a transistor in a lightly doped drain (LDD) structure is commonly used.

1 to 3 are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the prior art.

Referring to FIG. 1, an isolation layer (not shown) defining an active region is formed in a predetermined region of the semiconductor substrate 10. The device isolation film is formed using conventional trench device isolation techniques. A thermal oxidation process is performed on the semiconductor substrate on which the device isolation film is formed to form a gate oxide film 20 on the active region. A gate conductive layer 30 is formed on the entire surface of the semiconductor substrate on which the gate oxide layer 20 is formed. The gate conductive layer 30 may be formed of polysilicon, and silicide materials may be further formed on the polycrystalline silicon.

Referring to FIG. 2, after forming the mask pattern 50 on the gate conductive layer 30, the gate conductive layer 30 is anisotropically etched using the mask pattern 50 as an etching mask. Accordingly, a gate conductive layer pattern 35 is formed under the mask pattern 50.

The gate conductive layer pattern 35 is used as a gate electrode of a transistor. Accordingly, in order to prevent problems such as gate electrodes and electrical bridges of neighboring transistors, the anisotropic etching of the gate conductive layer 30 may be performed by an overetch method. Although the etching of the gate conductive layer 30 uses an etching recipe having an etch selectivity with respect to the gate oxide layer 20, since the gate oxide layer 20 is formed to a thin thickness, the above-described transient etching As a result, the semiconductor substrate 10 may be recessed. In particular, when the gate conductive layer 30 is formed of polycrystalline silicon, the semiconductor substrate 10 made of single crystal silicon does not have etch selectivity in the etching process. Accordingly, the recess phenomenon due to the excessive etching is further intensified.

The gate oxide layer 20 forms a gate oxide layer pattern 25 by the transient etching, and the gate oxide layer pattern 25 forms a gate pattern 40 together with the gate conductive layer pattern 35. An ion implantation process using the mask pattern 50 or the gate pattern 40 as an ion implantation mask is performed to form a low concentration impurity region 60 in the recessed semiconductor substrate 10.

Referring to FIG. 3, after removing the mask pattern 50, a gate spacer 70 is formed on sidewalls of the gate pattern 40. A high concentration ion implantation process using the gate spacer 70 and the gate pattern 40 as an ion implantation mask is performed to form a high concentration impurity region 80 in the active region next to the gate pattern 40.

The high concentration impurity region 80 is spaced apart from the low concentration impurity region 60 by the thickness of the gate spacer 70 by using the gate spacer 70 as an ion implantation mask. The low and high concentration impurity regions 60 and 80 thus formed form a junction region of a lightly doped drain (LDD) structure. However, since the junction region is formed in the recessed active region described above, the bottom surface of the highly doped impurity region 80 is formed deeper from the bottom surface of the gate oxide pattern 25. When a high voltage is applied to the high and low concentration impurity regions 60 and 80 formed in such a shape, a punch through phenomenon occurs easily.

In order to minimize this punch-through phenomenon, a method of forming a shallow junction area has been proposed. As a method for forming the shallow junction region, there is a method of controlling the energy used in the ion implantation processes for forming the high concentration and low concentration impurity regions 60 and 80 low. However, even with this method, since the ion implantation process is performed for the recessed active region described above, the desired effect was not sufficiently obtained.

An object of the present invention is to provide a transistor of a semiconductor device that can minimize the punch-through phenomenon.

Another object of the present invention is to provide a method for manufacturing a transistor of a semiconductor device which can prevent the recess of the active region in which the junction region is formed.

1 to 3 are process cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the prior art.

4 through 9 are process cross-sectional views illustrating a method of manufacturing a transistor in a semiconductor device according to an embodiment of the present invention.

10 is a perspective view illustrating a transistor of a semiconductor device according to a preferred embodiment of the present invention.

In order to achieve the above technical problem, the present invention provides a transistor manufacturing method of a semiconductor device comprising the step of recessing the upper surface of the semiconductor substrate in the region where the channel is formed. The method includes forming a shallow trench having a top surface recessed in a predetermined region of the semiconductor substrate, forming a gate pattern on the shallow trench, and then forming an impurity region in the semiconductor substrate around the gate pattern. It includes. In this case, the semiconductor substrate under the gate pattern is formed lower than the upper surface of the impurity region.

The forming of the shallow trench may include forming a mold layer on the semiconductor substrate, patterning the same, and forming a mold layer pattern having an opening to expose the semiconductor substrate in a predetermined region, and then forming an upper surface of the exposed semiconductor substrate. It is preferred to include the step of recessing. In this case, the opening exposes the semiconductor substrate in a region where the gate pattern is to be formed. The mold film is preferably formed of a silicon nitride film or a silicon oxide film and a silicon nitride film laminated in this order. In addition, the step of recessing the upper surface of the semiconductor substrate is performed using an etch recipe having an etch selectivity with respect to the template film pattern.

In the forming of the gate pattern, a gate insulating film is formed on the semiconductor substrate on which the shallow trench is formed, and a gate conductive film is formed on the entire surface of the semiconductor substrate on which the gate insulating film is formed to fill the opening of the template film pattern. And etching the gate conductive layer until the top surface of the pattern is exposed. In this case, the gate insulating film is preferably a silicon oxide film formed by thermal oxidation of the exposed shallow trench. In addition, the gate conductive layer may be formed of at least one material selected from polycrystalline silicon, tungsten, cobalt, copper, aluminum, and silicide materials. Preferably, after forming the gate pattern, the method may further include removing the mold layer pattern by using an etching recipe having an etch selectivity with respect to the gate pattern.

The forming of the impurity region may include forming a low concentration impurity region in the semiconductor substrate around the gate pattern, forming a gate spacer on the sidewall of the gate pattern, and then forming a high concentration impurity region in the semiconductor substrate around the gate spacer. It is preferable to include the step of. In this case, the low concentration impurity region is formed through a low concentration ion implantation process using the gate pattern as a mask. In addition, the high concentration impurity region is formed through a high concentration ion implantation process using the gate spacer and the gate pattern as a mask.

In order to achieve the above technical problem, the present invention provides a transistor of a semiconductor device including a channel region in which an upper surface is recessed. The transistor includes a shallow trench disposed in a predetermined region of the semiconductor substrate, a gate pattern disposed on the shallow trench, and an impurity region formed in the semiconductor substrate around the shallow trench. At this time, the shallow trench has a recessed top surface. Accordingly, the bottom surface of the shallow trench is lower than the top surface of the impurity region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

4 through 9 are process cross-sectional views illustrating a method of manufacturing a transistor in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, an isolation layer 105 is formed in a predetermined region of the semiconductor substrate 100 to define an active region. The device isolation layer 105 may be formed using a conventional trench device isolation technique, and a detailed description thereof will be omitted.

The mold layer 122 is formed on the semiconductor substrate on which the device isolation layer 105 is formed. The mold film 122 includes a lower mold film 110 and an upper mold film 120 that are sequentially stacked, but may be formed of only the upper mold film 120. In addition, the mold layer 122 is formed of a material that can be selectively removed with respect to the gate conductive layer formed in a subsequent process. Preferably, the upper mold film 120 is formed of a silicon nitride film and the lower mold film 110 is formed of a material having an etch selectivity with respect to the upper mold film 120, preferably, a silicon oxide film.

Referring to FIG. 5, the mold film 122 is patterned to form a mold film pattern 127 including a lower mold film pattern 115 and an upper mold film pattern 125 that are sequentially stacked. The mold layer pattern 127 has an opening crossing the active region while exposing an upper surface of the semiconductor substrate 100. Meanwhile, as described with reference to FIG. 4, the mold layer pattern 127 may be formed of only the upper mold layer pattern 125 formed of a silicon nitride layer.

Thereafter, the exposed semiconductor substrate 100 is recessed using the upper mold layer pattern 125 as an etching mask. Accordingly, a shallow trench 130 is formed below the opening. The shallow trench 130 has a lower upper surface than the upper surface of the semiconductor substrate 100 covered with the mold layer pattern 127. At this time, the shallow trench 130 is formed to have a depth of approximately 10 to 300Å.

Referring to FIG. 6, after forming the shallow trench 130, a gate oxide layer 140 is formed on the surface of the shallow trench 130 exposed through the mold layer pattern 127. A gate conductive layer 150 is formed on the entire surface of the semiconductor substrate on which the gate oxide layer 140 is formed.

The gate oxide layer 140 is preferably a silicon oxide layer formed by thermally oxidizing a semiconductor substrate exposed in the shallow trench 130. As is known, the thermal oxidation process of silicon consumes the thickness of silicon. As a result, the gate oxide layer 140 has a lower surface lower than the lower surface of the mold layer pattern 127 by the depth of the shallow trench 130 plus the consumed silicon thickness.

The gate conductive layer 150 may be at least one selected from polycrystalline silicon, tungsten, cobalt, copper, aluminum, and silicide materials. Materials for convenience in a subsequent planarization etching process may be further formed on the gate conductive layer 150.

Referring to FIG. 7, the gate conductive layer 150 is planarized and etched until the mold layer pattern 127 is exposed. As a result, a gate conductive layer pattern 155 is formed to fill the opening of the mold layer pattern 127.

As a result, the gate oxide layer 140 and the gate conductive layer pattern 155 are sequentially stacked on the shallow trench 130. The gate conductive layer pattern 155 thus formed is used as a gate electrode of the transistor.

Referring to FIG. 8, the upper mold layer pattern 125 may be selectively removed by using an etching recipe having an etching selectivity with respect to the gate conductive layer pattern 155. Removing the upper mold layer pattern 125 may use an etching recipe having both etching selectivity with respect to the lower mold layer pattern 115. In addition, the removing of the upper mold layer pattern 125 may be performed by a wet etching method using phosphoric acid as an etching solution.

After removing the upper mold layer pattern 125, a low concentration ion implantation process using the gate conductive layer pattern 155 as an ion implantation mask is performed. Accordingly, the low concentration impurity region 160 is formed in the active region around the gate conductive layer pattern 155. In the low concentration ion implantation process, it is preferable to use an impurity of a conductivity type different from that contained in the semiconductor substrate (ie, the channel of the transistor) under the silicon oxide layer 140.

The remaining lower mold layer pattern 115 may be used as a buffer layer to prevent ion channeling in the low concentration ion implantation process. Thus, the ion channeling can be prevented to form a shallow junction region, the shallow junction region helps to prevent the punch-through phenomenon.

Referring to FIG. 9, a spacer film is formed on the entire surface of the semiconductor substrate including the low concentration impurity region 160. The spacer layer is anisotropically etched until the top surface of the gate conductive layer pattern 155 is exposed, thereby forming a gate spacer 170 on the sidewall of the gate conductive layer pattern 155.

A high concentration ion implantation process using the gate spacer 170 and the gate conductive layer pattern 155 as an ion implantation mask is performed. Accordingly, a high concentration impurity region 180 is formed in the active region around the gate conductive layer pattern 155. The high concentration ion implantation process is a step of implanting impurities of a conductive type such as impurities contained in the low concentration impurity region 160 at a higher concentration. The high concentration impurity region 180 and the low concentration impurity region 160 formed as described above constitute a junction region of the LDD structure of the semiconductor transistor.

A junction region according to the present invention is formed on the semiconductor substrate 100 next to the gate conductive layer pattern 155. Due to the silicon consumption in the shallow trench 130 and the silicon oxide layer 140, the semiconductor substrate next to the gate conductive layer pattern 155 has a higher top surface than the bottom surface of the gate oxide layer 140. Accordingly, the height difference between the lower surfaces of the junction regions and the lower surface of the silicon oxide layer 140 is significantly reduced compared to the prior art. The shallow junction area thus formed contributes to minimizing the punch through phenomenon.

10 is a perspective view illustrating a transistor of a semiconductor device according to a preferred embodiment of the present invention.

Referring to FIG. 10, a shallow trench 130 having a recessed upper surface is disposed in a predetermined region of the semiconductor substrate 100. A gate pattern is disposed on the shallow trench 130. The gate pattern includes a gate oxide layer 140 and a gate conductive layer pattern 155 that are sequentially stacked.

Gate spacers 170 are disposed on both sidewalls of the gate conductive layer pattern 155. Low concentration impurity regions 160 and high concentration impurity regions 180 may be disposed in active regions on both sides of the gate conductive layer pattern 155. The low and high concentration impurity regions 160 and 180 are the same in that they are disposed next to the gate conductive layer pattern 155. However, the high concentration impurity region 180 is disposed farther apart from the gate conductive layer pattern 155 than the low concentration impurity region 160. At this time, the difference between the distances from the gate conductive layer pattern 155 is approximately equal to the thickness of the gate spacer 170.

The high concentration impurity region 180 and the low concentration impurity region 160 include impurities of the same conductivity type, and those impurities are included in the semiconductor substrate 100 (ie, the channel) under the gate oxide layer 140. It is preferable that it is opposite to the conductivity type of. The high and low concentration impurity regions 180 and 160 form a junction region of an LDD structure serving as a source / drain in a semiconductor transistor.

Meanwhile, the shallow trench 130 has a bottom surface lower than the top surface of the semiconductor substrate 100 on which the gate pattern is not disposed. Accordingly, the lower surface of the gate oxide layer 140 is lower than the upper surfaces of the high concentration and low concentration impurity regions 180 and 160, and the difference between the depths of the gate oxide layer 140 and the lower surface of the high concentration impurity region 180 is different. Is reduced compared to the prior art.

According to the present invention, the upper surface of the semiconductor substrate on which the channel is formed is recessed. Accordingly, the bottom surface of the gate oxide film is formed lower than the top surface of the junction region. This makes it possible to form the junction region at a shallow depth. As a result, the transistor of the semiconductor device which is excellent in the characteristic which prevents a punch through phenomenon can be manufactured.

Claims (10)

Forming a shallow trench having an upper surface recessed in a predetermined region of the semiconductor substrate; Forming a gate pattern on the shallow trench; And Forming an impurity region in the semiconductor substrate around the gate pattern, wherein the semiconductor substrate under the gate pattern is lower than an upper surface of the impurity region. The method of claim 1, Forming the shallow trench Forming a mold film on the semiconductor substrate; Patterning the mold layer to form a mold layer pattern having an opening that exposes the semiconductor substrate in a region where the gate pattern is to be formed; And And recessing an upper surface of the semiconductor substrate exposed through the opening. The method of claim 2, And the template film is formed of a silicon nitride film or a silicon oxide film and a silicon nitride film stacked in this order. The method of claim 2, And recessing the upper surface of the semiconductor substrate is performed using an etch recipe having an etch selectivity with respect to the mold film pattern. The method of claim 2, Forming the gate pattern Forming a gate insulating layer on the semiconductor substrate on which the shallow trench is formed; Forming a gate conductive film on an entire surface of the semiconductor substrate on which the gate insulating film is formed, filling the opening of the mold film pattern; And And planarizing etching the gate conductive layer until the top surface of the mold layer pattern is exposed. The method of claim 5, wherein And the gate insulating film is a silicon oxide film formed by thermally oxidizing the exposed shallow trench. The method of claim 5, wherein And the gate conductive layer is formed of at least one material selected from polycrystalline silicon, tungsten, cobalt, copper, aluminum, and silicide materials. The method of claim 2, After forming the gate pattern, removing the mold layer pattern using an etch recipe having an etch selectivity with respect to the gate pattern. The method of claim 1, Forming the impurity region is Performing a low concentration ion implantation process using the gate pattern as a mask to form a low concentration impurity region in the semiconductor substrate around the gate pattern; And Forming a gate spacer on sidewalls of the gate pattern; And And forming a high concentration impurity region in the semiconductor substrate around the gate spacer by performing a high concentration ion implantation process using the gate spacer and the gate pattern as a mask. A shallow trench disposed in a predetermined region of the semiconductor substrate, the shallow trench having a recessed upper surface; A gate pattern disposed on the shallow trench; And And an impurity region formed in the semiconductor substrate around the shallow trench, wherein a bottom of the shallow trench is lower than an upper surface of the impurity region.