KR20040010327A - Electrode materials for ferroelectric semiconductor device and manufacturing method therefor - Google Patents

Abstract

PURPOSE: A method for obtaining a ferroelectric memory device is provided to reduce thermal budget of a resistant electrode. CONSTITUTION: A method for obtaining a ferroelectric memory device comprises a step(52) for forming smooth iridium of low-tension on a semiconductor structure, a step(54) for forming smooth iridium oxide of low-tension having a pure phase structure on the smooth iridium of low-tension, and a step(56) for forming a ferroelectric material on the iridium oxide.

Description

Ferroelectric semiconductor device and its method of formation {ELECTRODE MATERIALS FOR FERROELECTRIC SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR}

BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to ferroelectric semiconductor devices, and more particularly to electrodes in which ferroelectric materials are used.

While the electronics industry is developing, several trends are driving the development of new technologies. First, there has been a need for increasingly smaller products that require less frequent replacement of batteries, such as cell phones, personal acoustic systems, digital cameras, and the like. Second, in addition to being smaller and more portable, these products are required to have more computing power and more memory storage capacity. Third, these devices are required to maintain information, video, and the like even when the battery is exhausted.

Nonvolatile memory and flash EEPROMs, such as electrically erasable and programmable read only memory (EEPROM), are used in these products because they can retain data without power. These memories include arrays of memory cells, each memory cell including a memory cell capacitor and a memory cell access transistor.

Nonvolatile and flash memories, such as ferroelectric random access memory (FRAM) and electrically erasable and programmable read only memory (EEPROM), are used in these products because they can retain data without power. These memories include arrays of memory cells, each memory cell including a memory cell capacitor and a memory cell access transistor.

Basically, memory cells use capacitors that hold charge. The ability to retain charge is referred to as "capacitance" and the capacitance of a given capacitor is a function of the dielectric constant of the capacitor dielectric, the effective area of the capacitor electrode, and the thickness of the capacitor dielectric layer. In essence, decreasing the thickness of the fluid layer, increasing the effective area of the capacitor electrode, and increasing the dielectric constant of the capacitor dielectric can increase the capacitance. For smaller products, it is desirable to have a small thickness and high capacitance.

Reducing the thickness of the capacitor dielectric layer to less than 100 μs generally reduces the reliability of the capacitor because the FN (Fower-Nordheim) high energy electron injection can create holes through the thin dielectric layer. .

Increasing the effective area of a capacitor electrode generally results in more complex and expensive capacitor structures. For example, three-dimensional capacitor structures, such as stacked and trenched structures, have been applied to 4MB DRAMs, but these structures are difficult to apply to 16MB or 64MB DRAMs. Stacked capacitors can have relatively steep steps due to the height of stacked capacitors that outperform memory cells, and trenched capacitors can have leakage current between trenches when scaled down to the size required for 64 MB DRAM.

Increasing the dielectric constant of a capacitor dielectric requires the use of a relatively high dielectric constant material. Currently, silicon dioxide (SiO ₂ ) with a dielectric constant of about 10 is used. Higher dielectric constant materials have been tried, such as yttrium oxide (Y ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), and titanium oxide (TiO ₂ ).

Recently, perovskite oxides with much higher dielectric constants of one hundred to one thousand are being studied. Examples of perovskites include PZT (PbZr _x Ti _(1-x) O ₃ ), BST (Ba _x Sr _(1-x) TiO ₃ ) or STO (SrTiO ₃ ), which are ferroelectric random access memory (FRAM) It is used to provide a new memory family called). Ferroelectric materials exhibit spontaneous polarization, resulting in excellent charge retention and improved non-volatility. When using a ferroelectric material as the capacitor dielectric layer, a thickness of one hundred angstroms can provide dielectric properties equivalent to a 10 kO oxide layer.

Ferroelectric memory is not only non-volatile, but also has the advantage of combining with logic circuits much easier than existing memories such as flash, static random access memory (SRAM) or DRAM. Therefore, this technique combines the flash's nonvolatile with the ease of DRAM's cell size and scale.

Here, there are a number of different formulations of ferroelectric materials under study and a number of different ferroelectric materials under study. Many studies are in the dead end.

The two main contenders for ferroelectric memory are SBT (SrBi ₂ Ta ₂ O ₉ ) and PZT (PbZr _x Ti _(1-x) O ₃ ).

The use of SBT has the advantage that rare metal electrodes with high corrosion resistance, such as platinum, can be used. However, a disadvantage is that a high temperature deposition process above 650 ° C. is required. Since standard logic circuits associated with ferroelectric memories have a maximum limit or thermal budget of acceptable temperatures that can be applied during fabrication, the high temperature deposition process uses the SBT process as a standard silicon semiconductor even if the thermal budget is exhausted. It becomes difficult to integrate with the process.

Using PZT has the advantage that deposition can be performed at temperatures as low as 400 to 450 ° C. However, a disadvantage is that the platinum electrode cannot be used because of reliability issues such as imprint and fatigue.

Therefore, the main challenge is to have a ferroelectric memory with a low thermal budget and durable electrodes.

Another major challenge is that the ferroelectric material must be very thin to be compatible with the voltages used in current CMOS semiconductor technology, and the ferroelectric material must be very high quality, have a very smooth surface and have no pinhole defects. It's the key. To achieve this property, a durable electrode with a very smooth surface is needed during sequential deposition of ferroelectric materials.

The solution to this challenge has been pursued for a long time, but has long left the person skilled in the art.

The present invention provides a method of forming a ferroelectric semiconductor device. Low stress, smooth iridium is formed on the semiconductor structure. Low stress, smooth iridium oxide with phase pure structure is deposited on iridium and ferroelectric material is formed on iridium oxide. This method of forming semiconductor devices using iridium and iridium oxide provides a low thermal budget ferroelectric memory having durable electrodes and very high quality, constant thickness materials.

Certain embodiments of the present invention have further advantages in addition to those mentioned above. This advantage will become apparent to those skilled in the art upon reading the following detailed description with reference to the accompanying drawings.

1 is a cross-sectional view of a three-dimensional ferroelectric memory integrated circuit according to the present invention;

2 is a close-up cross-sectional view of a memory capacitor in an intermediate manufacturing step according to the present invention;

3 is a close-up cross-sectional view of a memory capacitor in an intermediate manufacturing stage according to the present invention;

4 is a close-up cross-sectional view of a memory capacitor in an intermediate manufacturing step according to the present invention;

5 is a close-up cross-sectional view of a memory capacitor according to the present invention;

6 is a simplified flow chart of a method according to the invention.

Explanation of symbols for the main parts of the drawings

20-22: Source / drain area 24: Bit line

32,34: lower electrode 36: ferroelectric layer

38: upper electrode 40, 42: memory capacitor

Referring to Figure 1, a three-dimensional ferroelectric memory integrated circuit 10 in accordance with the present invention is shown. It will be appreciated that the invention is equally applicable to two-dimensional ferroelectric memory integrated circuits (not shown).

The semiconductor substrate 12 has a shallow trench isolation oxide layer 14, gate and gate dielectrics 16 and 18, and source / drain regions 20-22. Bit line 24 is formed in the dielectric (ILD) layer 26 of the intercalation layer in contact with one source / drain region 21, and buried contacts 28 and 30 are formed across the ILD layer 26. And contact source / drain regions 20 and 22, respectively.

Lower electrodes 32 and 34 are formed in contact with respective buried contacts 28 and 30, respectively. A diffusion layer (not shown), typically aluminum nitride (TiAlN), is deposited prior to depositing the lower electrodes 32 and 34 to prevent any interaction between the buried contacts 28 and 30 and the ferroelectric capacitor. Ferroelectric layer 36 is deposited over buried contacts 28 and 30. The upper electrode 38 is also deposited over the ferroelectric layer 36. The lower electrode 32 and the upper electrode 38 will be described later in detail.

Basically, gate and gate dielectrics 16 and 18 and source / drain regions 20-22 form semiconductor transistors of ferroelectric memory integrated circuit 10 while lower electrodes 32 and 34, ferroelectric layer 36 And the upper electrode 38 forms memory capacitors 40 and 42.

Lower electrodes 32 and 34 and upper electrode 38 are formed from rare metals or iridium (Ir) compounds. The ferroelectric layer 36 may be made of a material such as strontium bismuth tantalite (SBT) having the formula SrBi ₂ Ta ₂ O ₉ and lead zirconium titanate (PZT ₎ having the formula PbZr _x Ti _(1-x) O ₃ .

Referring now to FIG. 2, there is shown a close-up cross-sectional view of a memory capacitor 40 in an intermediate stage of manufacture in accordance with the present invention. Lower electrode 32 is shown to be deposited in situ.

In the past, the lower electrode 32 and the upper electrode 38 have been made of platinum. During the experiment, platinum was found to allow oxygen to diffuse through its grain boundaries into semiconductor transistors (shown in FIG. 1), causing oxidation in undesirable regions of the semiconductor transistors.

Iridium has also been found to slow the diffusion rate of oxygen to the point where iridium can be used as the diffusion barrier and lower electrode 32.

Iridium may be deposited by physical vapor deposition (PVD), for example sputtering. However, stress plays an important role in the formation of functional devices with ferroelectric materials by integrating iridium and sputtering deposits high stress films.

The stress can be minimized while being kept low enough for the thermal budget in the integration of the semiconductor process, the heater temperature for sputtering ranges from 200 ° C. to 550 ° C. and preferably 550 ° C. I learned that it's temperature.

Using a heater temperature of 550 ° C. to sputter deposited iridium, a thin film of metal iridium is deposited at a tensile stress of 200 MPa to 1000 MPa, which is low stress deposition with an optimum tensile stress of approximately 700 MPa and smooth It is defined as an rms roughness of about 1 nm measured by atomic force microscopy that is smaller than the rms roughness of 3 nm defining the surface. This iridium is deposited with a resistance of about 14 micro ohm centimeters (μΩcm).

In addition, it has been found that optimizing the thickness of the iridium thickness on the wafer from 94% to 98.5% is improved by optimizing the process batch (distance between the heater and the wafer) in the range of 55mn to 80mm, more specifically about 65mm. Typical wafer resistance for 50 nm iridium film within wafer nonuniformity is approximately 1.5% and wafer-to-wafer non-uniformity is less than 1%. The deposition rate of iridium using 700 W DC power ranges from 670 kW / min to 770 kW / mim linearly scaled with increasing power and more specifically about 720 kW / min.

Referring now to FIG. 3, there is shown a close-up cross-sectional view of a memory capacitor 40 in an intermediate stage of manufacture in accordance with the present invention.

In the past, the use of platinum in ferroelectric materials has caused durability or reliability problems and the same problems have been encountered with iridium alone. It has been found that depositing the coating 33 as iridium oxide on the electrode 32, which is iridium, can improve the reliability of 1 million to 10 ¹² memory cycles or even 10 ¹⁴ memory cycles.

Iridium oxide (IrO ₂ ) can be grown in situ by sputtering 45 and its surface morphology, its phase purity and its texture can be controlled by the oxygen (O ₂ ) content during sputtering. As used herein, "surface morphology" relates to surface properties, including smoothness, and "phase pure" refers to only x at the peak in one crystal structure. Refers to a material in which line diffraction occurs, and the texture relates to particle orientation.

Through extensive experiments, various ranges of critical parameters for the deposition of iridium oxide have been determined.

For example, it has been found that iridium oxide grown at 550 ° C. and 350 W in an environment containing 60% or more oxygen exhibits a rough surface. In order to obtain a smooth surface, the oxygen content needs to be kept below about 50% oxygen.

It was also found that an IrO ₂ film grown at 35% oxygen using 350W had a smooth, roughly 1 nm rms roughness, while a film grown at 70% oxygen using 350W had a rms roughness of approximately 23 nm. In the latter case, there are facetings in some particles, which correlate with the microstructure observed in all films grown in excess oxygen and changing from a (200) crystal structure to a polycrystalline structure. Phase pure IrO ₂ has a columnar microstructure.

It was further found that the phase pure film of IrO ₂ was obtained using 350W only in an environment containing at least 30% oxygen (balanced with argon) at 400 ° C and at least 35% oxygen at 550 ° C. At 700 W, 50% or more oxygen was required to obtain a phase pure IrO ₂ film.

The highly textured 200 pure IrO ₂ film is 400 ° C to 450 ° C using magnetron reactive sputtering and 350W to 700W DC power in an oxygen environment containing 20% or more oxygen. It has further been found that it can be optimized by growing iridium oxide at temperature.

The above description allows for the formation of low stresses, smooth IrO ₂ films with tensile stresses from 500 MPa to 1500 MPa and rms roughness less than 3 nm.

Referring now to FIG. 4, there is shown a close-up cross-sectional view of a memory capacitor 40 in an intermediate stage of manufacture further in accordance with the present invention.

It has been found that ferroelectric layer 36 can be deposited onto an optimized IrO ₂ phase without oxide reduction by metal organic chemical vapor deposition (MOCVD) at relatively high wafer temperatures of 600 ° C. to 610 ° C. This process produces a uniform thickness layer without pinholes, even at high quality and very thin thicknesses.

Referring now to FIG. 5, there is shown a cross-sectional view of a memory capacitor 40 in accordance with the present invention.

Top coating 37 of IrO ₂ is deposited. It has been found that the top coating 37 can be grown using low power, ie 350W. IrO ₂ with an rms roughness of approximately 3 nm was obtained when deposited in an environment containing 30-40% oxygen. Note that IrO ₂ can be deposited on the PZT surface using only 30% oxygen while at least 35% oxygen was required to deposit on the Ir surface. The data shows the correlation between the texture of IrO ₂ and its roughness. For example, IrO ₂ grown at 50 W in 50% oxygen is (200) oriented and quite smooth. As the film polycrystallizes, the surface roughness increases.

The upper electrode 38 of iridium is deposited in the same manner as the lower electrode 32.

Because stress plays an increasingly important role in microelectronic devices with shrinking devices, the experiments were conducted to slow down the stress of equally grown iridium and iridium oxide. The stress of a film grown using 700 W at 550 ° C. can be reduced by approximately 33% when annealed at 450 ° C. to 600 ° C. nitrogen (N ₂ ) for approximately 2 minutes.

Referring now to FIG. 6, a simplified flow diagram of a method 50 according to the present invention is shown. The method 50 includes the steps 52 of forming a low stress, smooth iridium in a semiconductor structure, and a step 54 of forming a low stress, smooth iridium oxide with a phase pure structure on the low stress, smooth iridium. And forming 56 a ferroelectric material on the iridium oxide.

Although the present invention has been described in connection with specific best modes, it will be understood by those skilled in the art that numerous alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all alternatives, modifications and variations that fall within the scope of the included claims. All that is described herein and shown in the accompanying drawings is illustrative only and should not be understood in a limiting sense.

According to the present invention, there is provided a ferroelectric memory having a low thermal budget with an electrode having a durable and smooth surface.

Claims (10)

In the method of forming the ferroelectric semiconductor device 10, Forming 52 a low stress, smooth iridium on the semiconductor structure, Forming 54 a low stress, smooth iridium oxide having a phase pure structure on the low stress, smooth iridium; Forming a ferroelectric material on the iridium oxide (56) Ferroelectric semiconductor device (10) forming method comprising a. The method of claim 1, The step of forming (52) the low stress, smooth iridium comprises forming an iridium having a tensile stress of 200 MPa to 1000 MPa and an rms roughness of less than 3 nm. The method of claim 1, The step (54) of forming a low stress, smooth iridium oxide comprises (500) forming a iridium oxide having a tensile stress of 500 MPa to 1500 MPa and an rms roughness of less than 3 nm. The method of claim 1, Forming (54) said low stress, smooth iridium oxide using physical vapor deposition in an environment with 20% to 50% oxygen. The method of claim 1, The forming of low stress, smooth iridium oxide (54) is a method of using physical vapor deposition at 350W to 700W in an environment with 20% to 50% oxygen at a temperature of (600) 400 ° C to 450 ° C. . The method of claim 1, Annealing the iridium and iridium oxide in the range of 450 ° C. to 600 ° C., Annealing the iridium prior to depositing the iridium oxide or the combination of iridium and iridium oxide. Way. The semiconductor structure 12, Low stress, smooth iridium (32, 34, 38) on the semiconductor structure 12, Low stress, smooth iridium oxides 33, 37 having a phase pure structure on the low stress, smooth iridium 32, 34, 38, and Ferroelectric material 36 on the iridium oxide 33, 37 Ferroelectric semiconductor device 10 comprising a. The method of claim 7, wherein Said low stress, smooth iridium (32, 34, 38) has a tensile stress of 200 MPa to 1000 MPa and an rms roughness of less than 3 nm. The method of claim 7, wherein The low stress, smooth iridium oxide (32, 34, 38) has a tensile stress of 500 MPa to 1500 MPa and an rms roughness of less than 3 nm. The method of claim 7, wherein Said ferroelectric material (36) is a ferroelectric material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, and combinations thereof.