KR20040008720A - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of obtaining high capacitance. CONSTITUTION: A capacitor insulating layer(27) is formed on a semiconductor substrate(20) having a contact plug(26). A line-shaped hole is formed to expose the contact plug by selectively etching the capacitor insulating layer. A conductive layer is formed in the line-shaped hole. A plurality of lower electrode patterns(28) are formed by selectively removing the capacitor insulating layer and the conductive layer. Then, a dielectric film and an upper electrode are sequentially formed on the lower electrodes.

Description

Method for fabricating capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = ε · As / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, and multilayer fin structures, are all proposed to increase the effective surface area of electrodes in a limited layout area and are widely used in concave or cylindrical shapes. It is used.

On the other hand, silicon is mainly used as a lower electrode of the capacitor because a stack of silicon nitride and oxide or tantalum oxide is applied as a capacitor dielectric material.

Since maintaining a constant capacitance in a limited area of an increasingly integrated semiconductor device is technically difficult in the manufacturing method of a three-dimensional capacitor, the lower electrode is formed in a concave shape, and then a silicon seed forming process is performed. The surface area has been increased.

However, as more and more fine design rules are applied, there is a disadvantage in that space for applying an additional silicon seed forming process is not secured. To overcome this, cylindrical capacitors are now mainly applied instead of concave. Cylindrical capacitors have the effect of increasing the area by applying an additional seed process by removing the sacrificial film for the lower electrode formed as a formwork and using the area of the capacitor to the outer surface of the lower electrode.

1A and 1B are cross-sectional views showing a method for manufacturing a concave capacitor according to the prior art.

First, as shown in FIG. 1A, first and second interlayer insulating films 13 and 14 are formed on a semiconductor substrate 10 on which a word line 12 and an active region 11 are formed. Contact holes are formed through the two interlayer insulating films 13 and 14 to expose the active region 11 of the semiconductor substrate 10. The contact hole 16 is filled with a conductive material to form the contact plug 16. Reference numeral '15' denotes a bit line as a pattern.

Subsequently, the capacitor insulating film 17 is formed as large as the capacitor is formed.

Subsequently, the capacitor insulating film 17 is selectively removed to expose the contact plug 16 to form the capacitor hole 18.

Subsequently, the lower electrode 19 is formed on the sidewalls and the bottom of the capacitor hole 18 by a conductive film. Subsequently, a dielectric thin film (not shown) is formed on the lower electrode 19, and an upper electrode (not shown) is formed thereon.

As semiconductor devices are increasingly integrated, capacitors are manufactured in a three-dimensional concave type as described above in a flat plate type. In a semiconductor memory device, a bit line and a word line are formed in a lower structure of a capacitor, one active region of the word line is connected to the capacitor, and the other active region is connected to the bit line and the contact plug.

However, since the bit line forms the capacitor on the word line, even if it is formed three-dimensionally, the cross section of the capacitor has to be formed into an elliptical shape with a large eccentricity.

FIG. 1B is a plan view of the capacitor of FIG. 1A, which shows that the cross section of the capacitor is formed in an elliptical shape having a large eccentricity having a long axis in the bit line direction as described above.

Therefore, even if the capacitor is formed in three-dimensional concave form to increase the capacitance in a limited area, the portion shown in 'X' of FIG. The portion 'X' of FIG. 1B is a portion having a large radius of curvature, and it is difficult for the lower electrode to be formed uniformly in the capacitor hole, and it is very difficult to form a subsequent dielectric thin film and the upper electrode.

Therefore, it is necessary to develop a manufacturing method of a concave type capacitor to have a larger capacitance.

It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device that can provide a larger capacitance in a limited area.

1A to 1B are cross-sectional views showing a method of manufacturing a cylindrical capacitor according to the prior art.

2A through 5 are cross-sectional views illustrating a method of manufacturing a semiconductor capacitor in accordance with a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

20: substrate

21: active area

22: wordline

23: first interlayer insulating film

24: second interlayer insulating film

25: bit line

26: Contact Plug

27: capacitor insulating film

28: lower electrode

29: dielectric thin film

30: upper electrode

The present invention for achieving the above object comprises the steps of forming a capacitor insulating film on the substrate; Selectively removing the capacitor insulating film to form a line-shaped hole; Forming a conductive film for a lower electrode in the line-shaped hole; Selectively removing the capacitor insulating film and the conductive film for the lower electrode to form a plurality of lower electrode patterns; Forming a dielectric thin film on the lower electrode; And it provides a method of manufacturing a capacitor of a semiconductor device comprising the step of forming an upper electrode on the dielectric thin film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2a to 5 are views showing a cylindrical capacitor manufacturing method according to a preferred embodiment of the present invention.

First, as shown in FIG. 2A, first and second interlayer insulating films 23 and 24 are formed on a semiconductor substrate 20 on which a word line 22 and an active region 21 are formed. Contact holes are formed through the two interlayer insulating films 23 and 24 to expose the active region 21 of the semiconductor substrate 20. The contact hole 26 is filled with a conductive material to form the contact plug 26. Reference numeral 25 'represents a portion of the bit line and the substrate connected to the active region, and a contact plug connected to the active region is not shown.

Subsequently, the capacitor insulating film 27 is formed as large as the capacitor is formed. The capacitor insulating film 26 is formed by chemical vapor deposition by applying a silicon oxide film such as USG (Undoped-Silicate Glass), PSG (Phospho-Silicate Glass), or BPSG (Boro-Phospho-Silicate Glass).

Subsequently, the capacitor insulating layer 27 is selectively removed to expose the contact plug 16 to form a capacitor hole. The capacitor holes are connected in the bit line direction C-C 'and are disconnected in the word line direction B-B'. That is, the capacitor insulating film remains only on the bit line.

FIG. 2B shows a plan view after selectively etching the capacitor insulating film 27 so that the contact plug 26 is exposed. The capacitor insulating film 27 remains on the bit line 25, the contact plug 26 is exposed and is spatially connected in the bit line direction C-C '. In addition, the word line 22 vertically crosses the lower portion of the bit line 25. A more accurate shape is shown in the figure shown stereoscopically in Fig. 2C.

Subsequently, as shown in FIG. 3, a lower electrode 28 is formed in the capacitor hole connected in the bit line direction C-C ′. Subsequently, the capacitor insulating layer 27 and the lower electrode 28 are selectively removed in the word line direction B-B 'to disconnect the adjacent capacitor lower electrode 28.

Next, as shown in FIG. 4, the dielectric thin film 29 is formed on the lower electrode 27, and the upper electrode 30 is formed thereon. Here, the dielectric thin film may be formed of high dielectric materials such as NO (Nitride-Oxide) and ONO, TaON, RuO, Ta ₂ O ₅ , (Ba, Sr) TiO ₃ (BST), or (Pb, Zr) TiO ₃ ( PZT), (Pb, La) (Zr, Ti) O ₃ (PLZT), SrBi ₂ Ta ₂ O ₉ (SBT), SrBi ₂ (Ta _1-x , Nbx) ₂ O ₉ (SBTN), Bi _4-x Ferroelectric materials such as La _x Ti ₃ O ₁₂ (BLT) and Bi ₄ Ti ₃ O ₁₂ (BIT) can be used, and Pt, Ir, Ru, IrOx, W, TiN, and polysilicon films can be used as the upper electrode. Can be.

5 shows a plan view after the lower electrode 28 is formed.

Referring to Figure 5, while the cross-section of the conventional concave-type capacitor was elliptical, in the present invention it can be seen that formed in a rectangular shape. Therefore, although it is difficult to stably form a capacitor in a region having a large radius of curvature which is both ends of an ellipse in the cross section of the capacitor in the related art, it is possible to form a highly reliable capacitor at both ends of the capacitor according to the present invention.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, it is possible to manufacture a concave capacitor having improved capacitance in a semiconductor manufacturing process having a fine design rule.

Claims (2)

Forming a capacitor insulating film on the substrate; Selectively removing the capacitor insulating film to form a line-shaped hole; Forming a conductive film for a lower electrode in the line-shaped hole; Selectively removing the capacitor insulating film and the conductive film for the lower electrode to form a plurality of lower electrode patterns; Forming a dielectric thin film on the lower electrode; And Forming an upper electrode on the dielectric thin film Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, And the line-shaped holes are formed in the bit line direction.