KR20040008543A - Method for cutting semiconductor wafer - Google Patents

Method for cutting semiconductor wafer Download PDF

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Publication number
KR20040008543A
KR20040008543A KR1020020042183A KR20020042183A KR20040008543A KR 20040008543 A KR20040008543 A KR 20040008543A KR 1020020042183 A KR1020020042183 A KR 1020020042183A KR 20020042183 A KR20020042183 A KR 20020042183A KR 20040008543 A KR20040008543 A KR 20040008543A
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KR
South Korea
Prior art keywords
semiconductor wafer
cutting groove
cutting
local thinning
directional local
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KR1020020042183A
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Korean (ko)
Inventor
이정훈
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엘지전자 주식회사
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Application filed by 엘지전자 주식회사 filed Critical 엘지전자 주식회사
Priority to KR1020020042183A priority Critical patent/KR20040008543A/en
Publication of KR20040008543A publication Critical patent/KR20040008543A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

PURPOSE: A dicing method of a semiconductor wafer is provided to be capable of preventing the propagation of crack for improving the reliability and reproductivity of a device, by applying a directional local thinning structure and forming a cutting groove at the semiconductor wafer. CONSTITUTION: A cutting groove is formed at the upper portion of a semiconductor wafer. A dicing process is then carried out along the cutting groove by applying a directional local thinning structure(40) to the semiconductor wafer. At this time, the directional local thinning structure is that both sides of the semiconductor wafer become thinner and thinner from the cutting groove. At the time, the cutting groove is used as a reference line.

Description

반도체 웨이퍼 절단 방법{Method for cutting semiconductor wafer}Method for cutting semiconductor wafer

본 발명은 반도체 웨이퍼의 절단 방법에 관한 것으로, 보다 상세하게는 반도체 레이저 다이오드를 제조하기 위한 웨이퍼에서 소자들을 분리하기 위한 절단 공정시, 디렉셔널 로칼 씨닝(Directional Local Thinning)구조를 적용하고, 커팅 그루브(Cutting Groove)를 형성하여 난 리렉셔널 랜덤 밴팅(Non Directional random bending)을 없게하여 크랙의 전파를 차단할 수 있는 반도체 웨이퍼의 절단 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of cutting a semiconductor wafer, and more particularly, in a cutting process for separating elements from a wafer for manufacturing a semiconductor laser diode, a directional local thinning structure is applied, and a cutting groove is used. The present invention relates to a method of cutting a semiconductor wafer capable of blocking propagation of cracks by eliminating non-directional random bending by forming a cutting groove.

도 1은 종래의 반도체 웨이퍼에 생성된 크랙 등에 의해 방향 왜곡이 발생한 절단된 반도체 웨이퍼의 단면도로써, 반도체 레이저 다이오드가 제조된 반도체 웨이퍼(10)상에 커팅 그루브(Cutting Groove)형성 방향으로 밴딩(20)이 있어 크랙(30)등이 발생하게 된다.FIG. 1 is a cross-sectional view of a cut semiconductor wafer in which direction distortion occurs due to a crack generated in a conventional semiconductor wafer, etc., and bending of the semiconductor wafer 10 in the direction of forming a cutting groove on the semiconductor wafer 10 on which the semiconductor laser diode is manufactured. ) And cracks 30 are generated.

이러한 미세한 크랙들(30)은 반도체 레이저 다이오드를 제조하기 위해, 반도체 웨이퍼(10)를 얇게 가공할 때, 반도체 웨이퍼(10)의 가장자리 부근에서 스트레스가 극대화되면서 파열이 일어나서 발생된다.These minute cracks 30 are generated when the semiconductor wafer 10 is thinly manufactured in order to manufacture a semiconductor laser diode, while the stress is maximized in the vicinity of the edge of the semiconductor wafer 10 to cause rupture.

이 크랙들(30)은 반도체 웨이퍼(10)상에 반도체 레이저 디이오드들을 분리하기 위한 커팅 그루브(Cutting Groove)(30)를 형성하게 되면, 반도체 웨이퍼(10)의 가장자리에서 내부로 전파하게 된다.When the cracks 30 form a cutting groove 30 for separating semiconductor laser diodes on the semiconductor wafer 10, the cracks 30 propagate inwardly at the edge of the semiconductor wafer 10.

이렇게 크랙들(20)이 소자들이 형성된 반도체 웨이퍼(10)의 내부로 전파하게 되면, 소자에 악영향을 주게 되고, 소자의 신회성이 저하되는 문제점이 발생한다.As such, when the cracks 20 propagate into the semiconductor wafer 10 in which the devices are formed, the device may adversely affect the device, and deterioration of the device may occur.

이에 본 발명은 상기한 바와 같은 문제점을 해결하기 위하여 안출된 것으로, 레이저 다이오드가 제조된 반도체 웨이퍼에서 소자들을 분리하기 위한 절단 공정시, 자주 발생되는 방향왜곡에 희해 절단 후 형상이 반듯하지 않게 되고 미러(Mirror)면 형성이 잘 되지 않는 등의 현상을 없애고자 하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the problems described above, and during the cutting process for separating the elements from the semiconductor wafer fabricated by the laser diode, the shape is not smooth after cutting due to the directional distortion often generated. (Mirror) The purpose is to eliminate the phenomenon such as poor surface formation.

상기한 본 발명의 목적을 달성하기 위한 바람직한 양태(樣態)는, 반도체 웨이퍼상에 커팅 그루브(Cutting Groove)를 형성하는 제 1단계;A preferred aspect for achieving the above object of the present invention is a first step of forming a cutting groove (cutting groove) on the semiconductor wafer;

상기 커팅 그루브가 형성된 반도체 웨이퍼에 디렉셔널 로컬 씨닝(Directional Local Thinning)구조를 적용하여 상기 커팅 그루브(Cutting Groove)형성 방향으로 절단하는 제 2단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 웨이퍼 절단 방법이 제공된다.And a second step of cutting in the cutting groove forming direction by applying a directional local thinning structure to the semiconductor wafer on which the cutting groove is formed. do.

도 1은 종래의 반도체 웨이퍼에 생성된 크랙 등에 의해 방향 왜곡이 발생한 절단된 반도체 웨이퍼의 단면도이다.1 is a cross-sectional view of a cut semiconductor wafer in which direction distortion occurs due to a crack or the like generated in a conventional semiconductor wafer.

도 2a는 본 발명에 따른 디렉셔널 로컬 씨닝(Directional Local Thinning)구조를 적용하는 모습을 나타내는 단면도이다.Figure 2a is a cross-sectional view showing the appearance of applying a directional local thinning (Directional Local Thinning) structure according to the present invention.

도 2b는 본 발명에 따른 반도체 웨이퍼에 절단 방법을 나타내는 단면도 이다.2B is a cross-sectional view showing a cutting method for a semiconductor wafer according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 반도체 웨이퍼 20 : 밴딩(Bending)10: semiconductor wafer 20: bending

30 : 크랙(Crack) 40 : 디렉셔널 로컬 씨닝(Directional Local Thinning)30: Crack 40: Directional Local Thinning

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2a는 본 발명에 따른 디렉셔널 로컬 씨닝(Directional Local Thinning)구조(40)를 나타내는 도면으로 커팅 그루브(Cutting Groove)형성 방향으로는 밴딩(20)이 없고 웨이퍼(10)의 좌우 방향으로만 밴딩(20)이 형성되는 것을 나타낸다.FIG. 2A is a view illustrating a directional local thinning structure 40 according to the present invention. FIG. 2A shows no directional banding in the cutting groove forming direction and only the left and right directions of the wafer 10. (20) is formed.

도 2b는 본 발명에 따른 반도체 웨이퍼의 절단 공정을 나타내는 도면으로써,반도체 웨이퍼(10)의 좌우측만 얇아진 구조에서 좌우측에서만 밴딩(20)이 발생하고 커팅 그루브(Cutting Groove)형성 후 디렉셔널 로컬 씨닝(Directional Local Thinning)구조(40)를 적용하여 상기 커팅 그루브 형성 방향으로 밴딩(20)이나 크랙(30)등의 왜곡 없이 반듯하게 절단된 반도체 웨이퍼를 얻을 수 있는 장점이 있다.FIG. 2B is a view illustrating a cutting process of a semiconductor wafer according to the present invention. In the structure in which only the left and right sides of the semiconductor wafer 10 are thinned, banding 20 occurs only on the left and right sides, and after forming a cutting groove, directional local thinning ( Directional Local Thinning (40) structure 40 is applied to obtain a semiconductor wafer that is smoothly cut without distortion such as banding 20 or crack 30 in the cutting groove forming direction.

이는 결국 소자의 신뢰성과 재현성을 향상 시킬 수 있는 장점이 될 수 있다.This may eventually be an advantage to improve the reliability and reproducibility of the device.

이상에서 상세히 설명한 바와 같이 본 발명은 반도체 레이저 다이오드를 제조하기 위한 웨이퍼에서 소자들을 분리하기 위한 절단 공정시, 디렉셔널 로컬 씨닝(Directional Local Thinning)구조(40)와 커팅 그루브를 형성하여 크랙의 전파를 차단하여, 소자의 신뢰성과 재현성을 향상 시킬수 있는 효과가 있다.As described in detail above, the present invention forms a directional local thinning structure 40 and a cutting groove in a cutting process for separating devices from a wafer for manufacturing a semiconductor laser diode, thereby preventing propagation of cracks. By blocking, there is an effect that can improve the reliability and reproducibility of the device.

본 발명은 구체적인 예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the invention has been described in detail only with respect to specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the spirit of the invention, and such modifications and variations belong to the appended claims.

Claims (2)

반도체 웨이퍼상에 커팅 그루브(Cutting Groove)를 형성하는 제 1단계;A first step of forming a cutting groove on the semiconductor wafer; 상기 커팅 그루브가 형성된 반도체 웨이퍼에 디렉셔널 로컬 씨닝(Directional Local Thinning)구조를 적용하여 상기 커팅 그루브(Cutting Groove)형성 방향으로 절단하는 제 2단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 웨이퍼 절단 방법.And a second step of cutting in a cutting groove forming direction by applying a directional local thinning structure to the semiconductor wafer on which the cutting groove is formed. 제 1항에 있어서 상기 디렉셔널 로컬 씨닝 구조 적용은 상기 반도체 웨이퍼의 커팅 그루브와 반대 방향으로만 얇게 하는 구조로 적용하는 것을 특징으로 하는 반도체 웨이퍼 절단 방법.The method of claim 1, wherein the directional local thinning structure is applied in a structure that is thinned only in a direction opposite to the cutting groove of the semiconductor wafer.
KR1020020042183A 2002-07-18 2002-07-18 Method for cutting semiconductor wafer KR20040008543A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2325882A4 (en) * 2008-09-18 2017-01-04 The University of Tokyo Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2325882A4 (en) * 2008-09-18 2017-01-04 The University of Tokyo Method for manufacturing semiconductor device

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