KR20040007793A - Method for manufacturing capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to increase the capacitance by forming an HSG only on an inner wall of a capacitor bottom electrode pattern. CONSTITUTION: An interlayer dielectric(11) having an opening portion(11a) is formed on a semiconductor substrate(10). A conductive plug(13) is formed to bury the opening portion(11a). A cap oxide layer is formed on the interlayer dielectric(11). A capacitor bottom electrode structure is formed by etching the cap oxide layer. A silicon nitride layer is formed on the capacitor bottom electrode structure. The silicon nitride layer is etched. A polycrystalline silicon layer is formed on the remaining silicon nitride layer and the capacitor bottom electrode structure. A photoresist layer is formed on the polycrystalline silicon layer. A top part of the interlayer dielectric is exposed by etching the photoresist layer and the polycrystalline silicon layer. A capacitor bottom electrode pattern is formed by removing the remaining photoresist layer and the cap oxide layer. A capacitor bottom electrode having an HSG is formed on an inner wall of the capacitor bottom electrode pattern. A dielectric layer(20) and a polycrystalline silicon layer(22) for top electrode are formed thereon.

Description

METHODS FOR MANUFACTURING CAPACITOR IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device having a cylindrical structure capable of securing a capacitance.

Recently, with the development of semiconductor manufacturing technology, the demand for memory devices is increasing rapidly. The capacitor used as the data storage means varies in capacitance depending on the area of the electrode, the distance between the electrodes, and the dielectric constant of the dielectric film inserted between the electrodes.

However, as the semiconductor device is highly integrated, the capacitor formation area in the semiconductor device is reduced, and as a result, the electrode area of the capacitor is reduced, thereby reducing the capacitance of the capacitor. In general, such a capacitor manufacturing method is provided with a semiconductor substrate having an interlayer insulating film provided with a contact hole. A polysilicon film is deposited inside the contact hole and then etched back to form a plug polysilicon film. Then, a PE-Nitride film is deposited as an etch barrier film on the plug polysilicon film, and a PSG film having a relatively high wet etching rate is deposited by a cap oxide film. Then, the cap oxide film is etched to form a basic lower electrode structure for producing a capacitor. In this case, the etch barrier nitride layer serves as a dry etching barrier when cap oxide is etched and a wet etching barrier when the cap oxide layer is diped out, and an etching barrier having a sufficient thickness of at least 200 mm 3 or more is required to secure an etching selectivity. Do. However, when the thickness of the etching barrier is increased to secure the etching selectivity, cracks are generated due to stress on the semiconductor substrate. On the other hand, when the nitride film is formed to have a thin thickness so that cracks do not occur, the nitride film is attacked due to lack of selectivity when the cap oxide film is dry etched, and the subsequent interlayer insulating film is etched to become a leakage current source during subsequent etching of the nitride film. The refresh characteristics of the capacitors deteriorate.

Accordingly, as shown in FIG. 1A, an interlayer insulating film 2 having a contact hole 2a is formed on the semiconductor substrate 1. Then, the conductive plug 3 filling the contact hole 2a is formed, and the cap oxide film 5 is sequentially formed on the entire surface of the resultant using the etching barrier film 4 and the PSG film. Subsequently, a photoresist pattern (not shown) defining a capacitor region is formed, and a cap oxide film is etched using the photoresist pattern as an etch barrier so that the interlayer insulating film 2 is exposed to form a basic lower electrode structure for manufacturing a capacitor. .

Referring to FIG. 1B, a polycrystalline silicon film 6 for lower electrodes is formed on the entire surface of the resultant product. Then, the photoresist film 8 is coated on the entire surface of the substrate to fill the inside of the cylinder structure.

Next, referring to FIG. 1C, after chemical-mechanical polishing (CMP) of the photoresist film 8 is performed until the upper end of the interlayer insulating film 2 is exposed, the photoresist film 8 is wetted. Perform etching.

Subsequently, referring to FIG. 1D, the capacitor lower electrode pattern of the cylindrical cylinder structure is formed by dipping out the cap oxide film 5 to use both the inside and the outside of the lower electrode pattern 6a of the capacitor. .

Subsequently, referring to FIG. 1E, HSG (Hemi-Spherical Grain) is formed on the surface of the capacitor lower electrode pattern 6a of the cylindrical cylinder structure to complete the formation of the lower electrode 7, as shown in FIG. 1F. The dielectric film 9 covering the lower electrode 7 and the polycrystalline silicon film 11 for the upper electrode are formed in this order to complete the capacitor manufacturing.

However, in the conventional method of manufacturing a capacitor of a semiconductor device as described above, as the unit area of the device decreases, the space between the cylinder and the cylinder becomes very small. Therefore, when the lower electrode including the HSG is formed in the cylinder structure having such a narrow space, there is a problem of contact with the adjacent cylinder.

In order to solve this problem, a concave structure using the inside of the cylinder as the lower electrode without removing the cap oxide film 5 is used in FIG. 1C.

However, since this concave structure uses only the inside of the lower electrode of the capacitor, the capacitor area is reduced by approximately 50% as compared to the cylinder structure using both the inside and the outside of the lower electrode of the capacitor. There was a problem that was reduced.

Accordingly, the present invention has been made to solve the above problems, in the capacitor lower electrode of the cylinder structure, to provide a method of manufacturing a capacitor of a semiconductor device that can secure the capacitance without contact with the adjacent cylinder. Its purpose is to.

1A to 1E are cross-sectional views for explaining a capacitor manufacturing method of a conventional semiconductor device.

2A to 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device of the present invention.

Explanation of symbols on the main parts of the drawings

10. Semiconductor substrate 11. Interlayer insulating film

11a. Opening 12,16. Silicon nitride film

13. Conductive plug 14. Capoxide film

17. Silicon nitride film pattern 18, 19. Polycrystalline silicon film

30. Photoresist 20. Dielectric Film

S1. Lower electrode pattern S2 of the capacitor. Lower electrode of capacitor

22. Polycrystalline Silicon Film for Upper Electrodes

In order to achieve the above object, a method of manufacturing a capacitor of a semiconductor device of the present invention, forming an interlayer insulating film having an opening for exposing a predetermined region of the substrate on a semiconductor substrate, and a conductive plug for embedding the opening Forming a cap oxide film on the entire surface of the interlayer insulating film including the conductive plug, etching the cap oxide film by a photolithography process to form a lower electrode structure of the capacitor, and forming a silicon nitride film on the entire lower electrode structure. Forming a silicon nitride film and etching the silicon nitride film to form an inner wall of the lower electrode structure; forming a remaining silicon nitride film and a polycrystalline silicon film for lower electrode on the entire lower electrode structure; and then forming a photoresist on the polycrystalline silicon film. Coating the photoresist and the polycrystalline silicon film Etching to expose the upper portion of the interlayer insulating film, removing the remaining photoresist and the cap oxide film in order to form a lower electrode pattern of the capacitor, and HSG treatment on the lower electrode pattern surface to form a capacitor having an HSG on the inner wall. Forming a lower electrode of the capacitor; and sequentially forming a dielectric film covering the lower electrode of the capacitor and a polycrystalline silicon film for the upper electrode.

The silicon nitride film is DCS, MS, NH3, N2 as a source gas, and at any one of atmospheric pressure chemical vapor deposition or low pressure chemical vapor deposition at a deposition pressure of 0.1 to 760 Torr and a deposition temperature of 500 to 800 ° C. The source gas of DCS, MS, NH3, and N2 is supplied at a flow rate of 50 to 5000 sccm. Further, the silicon nitride film is formed to a thickness of 10 to 100 GPa.

The polycrystalline silicon film for the lower electrode may use any one of a single layer of polycrystalline silicon doped with an impurity and a double stacked film of a polycrystalline silicon film doped with an impurity and a polycrystalline silicon film without an impurity. The double layered film forms a polycrystalline silicon film doped with impurities at a thickness of 50 to 250 GPa, and a polycrystalline silicon film not doped with impurities is formed at a thickness of 100 to 500 GPa.

The polycrystalline silicon film for the lower electrode uses DCS, MS, N2 and PH3 diluted MS as the source gas, and has an impurity concentration of 1E19 to 1E21 atoms / cc, a deposition pressure of 0.1 to 760 Torr and a deposition temperature of 400 to 700 ° C. Forming by proceeding any one of atmospheric pressure chemical vapor deposition or low pressure chemical vapor deposition. In addition, the DCS, MS, N and PH3 diluted MS gas is supplied at a flow rate of 50 to 5000 sccm.

In the HSG forming process, SiH 6 gas is supplied at 5 to 10 sccm at a temperature of 500 to 1000 ° C., and annealed for 100 to 500 seconds.

(Example)

Hereinafter, with reference to the accompanying drawings will be described in detail a capacitor manufacturing method of the semiconductor device of the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device of the present invention.

In the method of manufacturing a capacitor of a semiconductor device of the present invention, referring to FIG. 2A, an interlayer insulating film (not shown) is formed on a semiconductor substrate 10 on which a transistor including impurity regions (not shown) of a gate, a source, or a drain is manufactured. 11), the interlayer insulating film 11 is etched by the photolithography process to form the opening 11a exposing the impurity region.

Subsequently, a conductive film such as polycrystalline silicon is formed on the interlayer insulating film 11 including the opening 11a, and then the conductive film is etched back to form a conductive plug 13 for filling the opening 11a.

Then, the silicon nitride film 12 and the cap oxide film 14 are sequentially formed on the interlayer insulating film 11 including the conductive plug 13. In this case, the silicon nitride film 12 is used as an etch stop film in the subsequent process of etching the cap oxide film.

Thereafter, a photoresist pattern (not shown) defining a capacitor region is formed, and the cap oxide layer 14 is etched using the photoresist pattern as an etch barrier so that the interlayer insulating layer 11 is exposed, thereby manufacturing a capacitor. Form an electrode structure.

Subsequently, as shown in FIG. 2B, after the silicon nitride film 16 is formed to have a thickness of 10 to 100 kPa by the chemical vapor deposition process on the entire surface of the resultant product, as shown in FIG. 2C, the remaining cap oxide film ( The silicon nitride film pattern 17 is etched back until the time point 14) is exposed. At this time, the silicon nitride film pattern 17 is formed as uniform and thin as possible, and is not removed in the subsequent etching process for forming the capacitor lower electrode of the cylinder structure and remains on the outer wall of the cylinder structure to serve as a dielectric film of the capacitor.

In addition, the silicon nitride film forming process uses DCS (DiCloroSilane), MS (MonoSilane), NH 3, and N 2 as the source gas, and at atmospheric pressure chemical vapor deposition at a deposition pressure of 0.1 to 760 Torr and a deposition temperature of 500 to 800 ° C. Or low pressure chemical vapor deposition. The source gas of DCS, MS, NH3, N2 is supplied at a flow rate of 50 to 5000 sccm.

Then, a polycrystalline silicon film 18 for lower electrodes is formed to a thickness of 100 to 1000 Å on the entire surface of the substrate including the silicon nitride film pattern 17. At this time, the lower electrode polycrystalline silicon film 18 uses either a single layer of polycrystalline silicon doped with an impurity and a double stacked film of a polycrystalline silicon film doped with an impurity or a polycrystalline silicon film not doped with an impurity. In the case where the double stacked structure is used as the lower electrode polycrystalline silicon film 18, a polycrystalline silicon film doped with impurities is first formed to have a thickness of 50 to 250 GPa, and a polycrystalline silicon film not doped with impurities is formed to have a thickness of 100 to 500 GPa. . Alternatively, when a single structure is used as the lower electrode polycrystalline silicon film 18, a polycrystalline silicon film doped with impurities is formed to have a thickness of 50 to 500 kHz.

In detail, the process of forming the polycrystalline silicon film 18 for the lower electrode is performed using DCS, MS, N2 and PH3 diluted MS as the source gas, and an impurity concentration of 1E19 to 1E21 atoms / cc, 0.1 to 760 Torr. Atmospheric chemical vapor deposition at a deposition pressure of 400) and a deposition temperature of 400 to 700 ° C. On the other hand, the DCS, MS, N and PH3 diluted MS gas is supplied at a flow rate of 50 to 5000 sccm.

Thereafter, as shown in FIG. 2D, the inside of the cylinder structure is embedded by coating the photoresist film 30 on the entire surface of the polycrystalline silicon film 18 for the lower electrode.

Next, as shown in FIG. 2E, the photoresist film is dry-etched or chemically-mechanically polished to expose the polycrystalline silicon film, and then the polycrystalline silicon film is exposed until the upper end of the cap oxide film 14, which is the basic lower electrode structure, is exposed. Dry etching or chemical-mechanical polishing. Then, the photoresist film is removed by wet etching. In this case, reference numeral 19 denotes a polycrystalline silicon film remaining after the chemical-mechanical polishing process is completed.

Thereafter, as shown in FIG. 2F, the cap oxide layer is diped out to use both the inside and the outside of the lower electrode S1 of the capacitor, thereby forming the capacitor lower electrode pattern S1 of a cylindrical cylinder structure. . Thereafter, although not shown in the figure, a natural oxide film removal process is performed using HF or BOE (Buffer Oxide Etchant) wet liquid.

Thereafter, as shown in FIG. 2G, the HSG film is formed on the surface of the capacitor lower electrode pattern of the cylindrical cylinder structure to form the capacitor lower electrode S2. The HSG forming process supplies SiH 6 gas at 5 to 10 sccm at a temperature of 500 to 1000 ° C., a seeding time of 50 to 150 seconds, and annealing for 100 to 500 seconds. At this time, HSG does not grow on the tungsten silicide film in the capacitor lower electrode S2, and HSG grows only on the polycrystalline silicon film inside the cylinder, thereby securing the maximum area in the ultra-high density memory device having a very small unit cell area in the cylinder structure. At the same time, the HSG process can be performed without any contact between the capacitors.

Subsequently, the dielectric film 20 and the polycrystalline silicon film 22 for the upper electrode are sequentially formed on the entire surface of the capacitor lower electrode S2 of the cylindrical cylinder structure to complete the capacitor manufacturing. At this time, after forming the dielectric film 20, a polycrystalline silicon film for the upper electrode of the capacitor should be formed within 5 hours. In addition, the dielectric film 20 forms a silicon nitride film with a thickness of 10 to 100 GPa or a silicon oxide film with a thickness of 50 to 500 GPa at a temperature of 600 to 1000 占 폚.

According to the present invention, by growing the HSG only inside the capacitor lower electrode pattern of the cylindrical cylinder structure, the HSG is secured to the cylinder structure in the ultra-high density memory device having a significantly small unit cell area, and the HSG is not contacted between the capacitors. The process can proceed.

As described in detail above, in the present invention, in the implementation of the semiconductor device, the HSG is formed only inside the capacitor lower electrode pattern of the cylindrical cylinder structure in order to increase the capacitance, thereby increasing the capacitance of about 1.5 times that of the conventional one. Increase the cylinder height by 25%.

Therefore, in the present invention, since the capacitance can be increased, the process margin can be secured by reducing the height of the cylinder structure.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (9)

Forming an interlayer insulating film having an opening on the semiconductor substrate to expose a predetermined region of the substrate; Forming a conductive plug to fill the opening; Forming a cap oxide film on the entire interlayer insulating film including the conductive plug; Etching the cap oxide layer by a photolithography process to form a lower electrode structure of a capacitor; Forming a silicon nitride film over the lower electrode structure; Etching the silicon nitride film and remaining on an inner wall of the lower electrode structure; Forming a polycrystalline silicon film for a lower electrode on the remaining silicon nitride film and the lower electrode structure, and then coating a photoresist on the polycrystalline silicon film; Etching the photoresist and the polycrystalline silicon film to expose an upper portion of the interlayer insulating film; Removing the remaining photoresist and the cap oxide layer in order to form a lower electrode pattern of the capacitor; HSG treatment on the lower electrode pattern surface to form the lower electrode of the capacitor having the HSG on the inner wall; And sequentially forming a dielectric film covering the lower electrode of the capacitor and a polycrystalline silicon film for the upper electrode. The method of claim 1, wherein the silicon nitride film using DCS, MS, NH3, N2 as the source gas, the atmospheric pressure chemical vapor deposition or low pressure chemical vapor deposition at a deposition pressure of 0.1 to 760 Torr and a deposition temperature of 500 to 800 ℃ A capacitor manufacturing method of a semiconductor device, characterized in that formed by any one of the steps. The method of manufacturing a capacitor of a semiconductor device according to claim 2, wherein the source gas of DCS, MS, NH3, N2 is supplied at a flow rate of 50 to 5000 sccm. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein the silicon nitride film is formed to a thickness of 10 to 100 GPa. The polycrystalline silicon film of claim 1, wherein the lower electrode polycrystalline silicon film uses any one of a single layer of polycrystalline silicon doped with an impurity and a double stacked film of a polycrystalline silicon film doped with an impurity and an undoped polycrystalline silicon film. A method for producing a capacitor of a semiconductor device. 6. The semiconductor device according to claim 5, wherein the double lamination film forms a polycrystalline silicon film doped with impurities at a thickness of 50 to 250 GPa, and a polycrystalline silicon film not doped with impurities is formed at a thickness of 100 to 500 GPa. Capacitor Manufacturing Method. 2. The polycrystalline silicon film for lower electrode according to claim 1, wherein the lower electrode polycrystalline silicon film uses DCS, MS, N2 and PH3 diluted MS as a source gas, and has an impurity concentration of 1E19 to 1E21 atoms / cc, a deposition pressure of 0.1 to 760 Torr and A method for manufacturing a capacitor of a semiconductor device, characterized in that formed by performing any one of atmospheric pressure chemical vapor deposition and low pressure chemical vapor deposition at a deposition temperature of 400 ~ 700 ℃. The method of claim 4, wherein the DCS, MS, N, and PH3 diluted MS gases are supplied at a flow rate of 50 to 5000 sccm. The method of claim 1, wherein the HSG forming process supplies SiH 6 gas at 5 to 10 sccm at a temperature of 500 to 1000 ° C., and anneals for 100 to 500 seconds.