KR100268428B1 - A capacitor and a method for fabricating the same - Google Patents

Abstract

The present invention relates to a capacitor and a method of manufacturing the same. According to the present invention, a first insulating layer formed on a semiconductor substrate is etched to form a storage node contact hole, and the storage node contact hole is filled with a conductive material to store the same. Forming a node contact plug, forming a second insulating layer on the first insulating layer and the storage node contact plug, and partially etching the second insulating layer to form an upper surface of the storage node contact plug and both sides of the storage node contact plug. Forming an opening that exposes a portion of the first insulating film, forming a doped polysilicon film on the second insulating film to partially fill the opening, and opening on the doped polysilicon film to completely fill the opening. Forming a photoresist film as a filling material, and The doped polysilicon layer and the photoresist layer may be planarized and etched until the upper surfaces of the second insulating layers are exposed to form a storage node, the photoresist layer may be removed, and the inner surface and the upper surface of the storage node may be removed. Forming an HSG polysilicon film on a surface, and removing the second insulating film on both sides of the storage node until an upper surface of the first insulating film is exposed. According to such a capacitor and its manufacturing method, by forming an HSG polysilicon film inside and on a top surface of a cylindrical storage node, the effective area of the capacitor is increased, thereby increasing capacitance and being very close to a neighboring storage node. Capacitor is formed.

Description

A CAPACITOR AND A METHOD FOR FABRICATING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a capacitor with increased capacitance and a method for manufacturing the same.

Ensuring sufficient capacitance in a small area is one of the most important problems in ultra large scale integration (ULSI) dynamic random access memory (DRAM) fabrication technology. As higher integration of DRAMs is required, the storage nodes of each memory cell must be manufactured to fit in an increasingly smaller area. The decrease in cell capacitance due to the reduction of memory cell area due to the high integration is a serious obstacle in increasing the packing density of the DRAM. Therefore, in order to solve the capacitance reduction problem, it is important to secure an increase in the packing density of the DRAM.

In general, in a 64 MB DRAM having a memory cell area of about 1.5 μm ² to which a conventional two dimensional structure stacked capacitor is applied, a high dielectric material such as tantalum oxide (Ta ₂ O ₃₎ Is used as a dielectric film, it is difficult to secure a sufficient capacitance. Therefore, stacked capacitors having three dimensional structures have been studied to increase cell capacitance. Such stacked capacitors are, for example, double-stacked, fin stacked, cylindrical, and box structure capacitors.

Since both the inner and outer surfaces of the capacitor become the effective area of the capacitor, the cylindrical capacitor is the most preferred form of capacitor among the three-dimensional stacked capacitors, and is particularly suitable for 64 MB or more integrated memory cells.

On the other hand, in recent years, a new technology, that is, a technology for increasing the effective area by changing the surface shape of capacitor polysilicon has been developed. The shape change of the surface is caused by controlling or manipulating the nucleation and growth conditions of polysilicon. HSG polysilicon films are being used to deposit on storage nodes to increase the surface area and capacitance of capacitors.

1A and 1E are flowcharts sequentially showing processes of a capacitor manufacturing method according to the related art.

First, referring to FIG. 1A, an insulating film 11 is formed on a semiconductor substrate 10. For example, it may be formed of an oxide film such as BPSG and USG. The insulating layer 11 is patterned and etched to form a contact hole 12. As in a capacitor over bit line (COB) cell, there are various active regions, bit lines, word lines, and other structures (not shown) in the semiconductor substrate 10. A polysilicon film is deposited over the structure. For example, the polysilicon film is a polysilicon film doped with phosphorus (P).

The polysilicon film is then patterned and etched to form a doped polysilicon region 13 as shown in FIG. 2B. The width and length of the doped polysilicon region 13 will vary depending on the design but can generally be in the range of 0.3 to 1 micron.

Next, as shown in Fig. 1C, a thin HSG polysilicon film 14 is formed over the entire structure. The HSG polysilicon film 14 is typically formed by depositing through a siren (SiH ₄ ) deposition at an amorphous silicon / polysilicon transition temperature, thus forming a storage node having the HSG polysilicon film 14. (15) is formed. The HSG polysilicon film on the insulating film 11 on both sides of the storage node 15 is removed to electrically isolate each storage node 15.

Then, as shown in FIG. 1D, a dielectric film 16 is deposited on the storage node 15. The dielectric layer 16 may be formed of three layers of oxide-nitride-oxide.

The problem of the above-mentioned conventional method is as follows. Since the HSG polysilicon film is formed on the outer surface of the capacitor storage node, there is a limit in minimizing the distance between adjacent storage nodes in the manufacture of highly integrated DRAM. In addition, HSG growth also encounters limitations in terms of HSG size over time.

Therefore, there is a need for a method of using HSG polysilicon to maximize DRAM surface area while maximizing capacitor surface area.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and by forming the HSG polysilicon film on the inside and the upper surface of the cylinder type capacitor, it is possible to increase the effective area and capacitance, and the distance from the adjacent capacitor storage node. The purpose is to provide a capacitor and a method of manufacturing the same that can be minimized.

1A-1D are cross-sectional views sequentially illustrating the processes of a method of forming a capacitor according to the prior art; and

2A-2G are cross-sectional views sequentially illustrating the processes of a method of forming a novel capacitor in accordance with a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

30 semiconductor substrate 31 field oxide film

32: gate oxide film 33: gate

34,36 insulation film 35 storage contact plug

37,40 photoresist 38 opening

41: storage node 42: HSG polysilicon film

43: dielectric film

(Configuration and action)

According to the present invention for achieving the above object, first, etching the first insulating film formed on the semiconductor substrate, forming a storage node contact hole; Filling the storage node contact hole with a conductive material to form a storage node contact plug; Forming a second insulating layer on the first insulating layer and on the storage node contact plug; Partially etching the second insulating layer to form an opening that exposes an upper surface of the storage node contact plug and a portion of the first insulating layer on both sides of the storage node contact plug; Forming a polysilicon film on the second insulating film to partially fill the opening; Forming a photoresist film on the polysilicon film to completely fill the opening; Forming a storage node by planar etching the polysilicon layer and the photoresist layer on both sides of the opening until the upper surface of the second insulating layer is exposed; Removing the photoresist film inside the opening; Forming HSG polysilicon on the storage node inner surface and upper surface; And removing the second insulating layers on both sides of the storage node until the upper surface of the first insulating layer is exposed.

The forming of the storage node contact hole may include filling the storage node contact hole with a nitride film; The method may further include forming a spacer on both sides of the storage node contact hole by dry etching the nitride layer.

Referring to FIG. 2G, in a novel capacitor and a method of manufacturing the same, an insulating film formed on a semiconductor substrate is etched to form an opening for forming a storage node. A doped polysilicon film is deposited to partially fill the opening. The doped polysilicon film on both sides of the opening is removed for electrical isolation of the storage node. HSG polysilicon is formed on the inner surface and top surface of the storage node.

By using the semiconductor device manufacturing method as described above, by forming the HSG polysilicon film inside the capacitor, the effective area and capacitance of the capacitor can be increased, and the distance from the immediately neighboring storage node can be minimized. In addition, since the insulating film is stripped after the HSG polysilicon film is formed inside the capacitor, there is no problem of an electrical short circuit with an adjacent storage node caused by the deposition of the HSG polysilicon film on another insulating film formed under the insulating film.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2G.

Referring to FIG. 2A, a field oxide layer 31 is formed on the semiconductor substrate 30 by defining active regions and inactive regions. The gate 33 is formed on the active region of the semiconductor substrate 30 with the gate oxide layer 32 interposed therebetween. Subsequently, a source / drain region (not shown) is formed by implanting impurities into the active region of the semiconductor substrate 30 on both sides of the gate 33.

The first insulating layer 34 is formed on the semiconductor substrate 30 including the gate 33. For example, it may be formed of an oxide film such as BPSG and USG. Subsequently, a photoresist film (not shown) is formed on the first insulating layer 34, and the photoresist film is patterned by a well-known photolithography process to form a photoresist pattern (not shown) for defining a storage contact region. . The first insulating layer 34 is etched using the photoresist pattern as a mask to form a storage node contact hole 35a exposing an upper surface of the source / drain region. The etching may be performed by dry etching using, for example, CF ₄ , CHF ₃ , and argon. The argon is provided by physical sputtering and is used to minimize polymer production.

Then, a conductive material, preferably a doped polysilicon layer (not shown), is formed on the first insulating layer 34 and inside the storage node contact hole 35a to completely fill the storage node contact hole 35a. Is deposited. The doped polysilicon layer is planarized by a well-known CMP process or dry etch back to form a storage node contact plug 35. Before the storage node contact plug 35 is formed, spacers 35b formed of a nitride film may be formed on both sidewalls of the storage node contact hole 35a to coat the storage node contact plug 35. . Forming the nitride layer spacer 35b may include filling the storage node contact hole 35a with a nitride layer and dry etching the nitride layer to form the spacer 35b.

A second insulating layer 36 is formed on the first insulating layer 34 including the storage node contact plug 35. The second insulating layer 36 is formed of a doped oxide film, for example, PSG, BSG, doped SOG, or the like, and is preferably formed of a silicon oxide film. The thickness of the second insulating layer 36 is determined according to the height of the desired capacitor.

Next, referring to FIG. 2B, a first photoresist film 37 in which an opening region is defined is formed on the second insulating film 36. 2C, the second insulating layer 36 is etched using the first photoresist layer 37 as a mask to etch the storage node contact plug 35 and the storage node contact plug 35. An opening 38 exposing portions of the first insulating layer 34 on both sides is formed. The first photoresist film 37 is removed from the surface of the second insulating film 36.

Next, as shown in FIG. 2D, a polysilicon film 39 doped with impurities is deposited thinly on the entire surface of the structure, and the deposition temperature is controlled to, for example, about 510 ° C. to be in an amorphous state. At this time, an N-type impurity such as phosphorus is used as the impurity, and the concentration thereof is about 1.0 x 10 ²⁰ atoms / cm ³ . The doped polysilicon film 39 is deposited in a thickness range of about 1000 GPa to 2000 GPa, thereby forming a polysilicon opening 38a. Polysilicon Opening 38a Filling Material For example, the second photoresist film 40 is deposited inside the polysilicon opening 38a and onto the doped polysilicon film 39 such that planarization is possible. To completely fill the opening 38a. This is to fill the opening 38a to remove the doped polysilicon layer 39 on both sides of the storage node for electrical isolation between the storage nodes, thereby protecting the inside of the opening 38a.

The second photoresist 40 on both sides of the opening 38a is then dry etched back and removed. Then, as shown in FIG. 2E, the doped polysilicon layer 39 on both sides of the opening 38a is planarized and etched to electrically isolate the adjacent storage node to form the cylindrical storage node 41. Then, the second photoresist remaining inside the opening 38a is removed.

Next, as shown in FIG. 2F, an HSG nucleation process for forming the HSG polysilicon film 42 only on the inner surface and the upper surface of the cylindrical storage node 41 is performed. The nucleation is performed by conventional LPCVD, plasma deposition, molecular beam deposition, or the like. In the case of LPCVD, the process pressure is approximately 1.0 × 10 ⁻⁵ Torr, the temperature is about 530 ° C. to 540 ° C., and the atmospheric gases include xylene (SiH ₄ ), dichloro xylene (SiH ₂ Cl ₂ ), Si ₂ H ₆ Etc. are used. After the nucleation process is completed, the annealing process is performed in an ultrahigh vacuum state of 1.0 × 10 ⁻⁹ to 1.0 × 10 ⁻¹⁰ . The processing time of each step plays an important role in determining the size and density of the HSG. The average grain size of the HSG polysilicon is, for example, about 100 kPa to 200 kPa. In the present invention, since the HSG nuclei are formed only on the inner and upper surfaces of the cylindrical storage 41, when the HSG nucleus is grown, it is possible to overcome the limitation on the HSG size with the growth time.

Next, the second insulating layer 36 on both sides of the storage node 41 is removed. Removal of the second insulating layer 36 may be performed by HF etching. In the present invention, since the second insulating film 36 is removed after the HSG polysilicon film 42 is formed, there is no possibility that the HSG polysilicon film 42 is deposited on the first insulating film 34. Therefore, short circuit problem between storage nodes does not occur.

Then, as shown in FIG. 2G, a dielectric film 43 is formed on the first insulating film 34 including the storage node 41.

According to the above-described capacitor of the present invention and a method of manufacturing the same, as shown in FIG. 2G, the capacitor is formed in a cylindrical shape so that the surface area of the capacitor increases and thus the capacitance also increases. In addition, HSG polysilicon is formed on the inside and top surfaces of the cylinder to further increase the capacitor surface area, minimizing the distance between adjacent storage nodes as much as possible in the fabrication of high density memory cells.

In addition, according to the above-described capacitor of the present invention and a manufacturing method thereof, as shown in FIGS. 2E and 2F, the second oxide film 36 is formed after the HSG polysilicon film 42 is completely formed inside the capacitor and then stripped. . Accordingly, the problem that the HSG polysilicon layer 42 is deposited on the first insulating layer 34 does not occur, and electrical isolation between storage nodes is improved.

The conventional capacitor manufacturing method has a problem that the HSG polysilicon is formed on the outside of the capacitor, and the HSG polysilicon size of the adjacent capacitor is limited to each other due to the problem that the HSG polysilicon is attached to each other, and thus the spacing between adjacent capacitors is limited. There was a limit to the increase of the effective area. According to the present invention to solve this problem, by forming a cylindrical capacitor storage node and forming HSG polysilicon only on the inner and upper surfaces of the cylinder, it is possible to overcome the limitation of HSG polysilicon size and maximize the capacitor effective area. In addition, the spacing between adjacent storage nodes can be minimized, which is advantageous for high integration of semiconductor devices.

Claims (6)

Etching the first insulating layer formed on the semiconductor substrate to form a storage node contact hole; Filling the storage node contact hole with a conductive material to form a storage node contact plug; Forming a second insulating layer on the first insulating layer and on the storage node contact plug; Partially etching the second insulating layer to form an opening that exposes an upper surface of the storage node contact plug and a portion of the first insulating layer on both sides of the storage node contact plug; Forming a polysilicon film on the second insulating film to partially fill the opening; Forming a photoresist film on the polysilicon film to completely fill the opening; Forming a storage node by planar etching the polysilicon layer and the photoresist layer on both sides of the opening until the upper surface of the second insulating layer is exposed; Removing the photoresist film inside the opening; Forming HSG polysilicon on the storage node inner surface and upper surface; And Removing the second insulating layer on both sides of the storage node until the upper surface of the first insulating layer is exposed. The method of claim 1, The polysilicon film is a capacitor manufacturing method is formed to have a thickness range of 1000kW to 2000kW. The method of claim 1, And the planarization etching is performed by an etch back process. The method of claim 1, The forming of the storage node contact hole may include: Filling the storage node contact hole with a nitride film; And And dry etching the nitride layer to form spacers on both side walls of the storage contact hole. A storage node contact plug formed through the insulating layer formed on the semiconductor substrate and electrically connected to an active region of the semiconductor substrate; A spacer formed between the insulating layer and the storage node contact plug and surrounding the storage node contact plug; A cylindrical polysilicon layer formed on the storage node contact plug and the spacer, including a portion of the insulating layer on both sides of the storage node contact plug to be electrically connected to the storage node contact plug; And, And a HSG polysilicon film formed on and in the cylindrical polysilicon film. The method of claim 5, The storage node contact plug is a capacitor storage node formed of a polysilicon layer.