KR20040005482A - Method of manufacturing a transistor in a semiconductor device - Google Patents
Method of manufacturing a transistor in a semiconductor device Download PDFInfo
- Publication number
- KR20040005482A KR20040005482A KR1020020040058A KR20020040058A KR20040005482A KR 20040005482 A KR20040005482 A KR 20040005482A KR 1020020040058 A KR1020020040058 A KR 1020020040058A KR 20020040058 A KR20020040058 A KR 20020040058A KR 20040005482 A KR20040005482 A KR 20040005482A
- Authority
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- South Korea
- Prior art keywords
- ion implantation
- concentration impurity
- film
- region
- implantation process
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000012535 impurity Substances 0.000 claims abstract description 31
- 238000005468 ion implantation Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000002513 implantation Methods 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 239000010941 cobalt Substances 0.000 claims description 16
- 229910017052 cobalt Inorganic materials 0.000 claims description 16
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 16
- 125000004429 atom Chemical group 0.000 claims description 6
- -1 boron ion Chemical class 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 125000005843 halogen group Chemical group 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 소정의 주입 각도로 고농도 불순물 이온 주입 공정을 실시함으로써 소자 분리막의 가장자리와 활성 영역의 경계면에서 접합 깊이를 충분히 확보할 수 있어 전류 누설을 방지할 수 있는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. In particular, by performing a high concentration impurity ion implantation process at a predetermined implantation angle, the junction depth can be sufficiently secured at the interface between the edge of the device isolation layer and the active region, thereby preventing current leakage. A transistor manufacturing method of a semiconductor device which can be used.
반도체 소자의 고집적화되고 면적이 축소됨에 따라 접합 영역을 얕게 형성하고, 고속 스위칭 동작을 위해 게이트 전극 상부 및 접합 영역 상부에 코발트 실리사이드막을 형성한다. 이에 따른 반도체 소자의 트랜지스터 제조 방법을 도 1을 이용하여 설명하면 다음과 같다.As the semiconductor device is highly integrated and the area is reduced, a junction region is formed to be shallow, and a cobalt silicide layer is formed on the gate electrode and the junction region to form a high speed switching operation. The transistor manufacturing method of the semiconductor device according to this will be described with reference to FIG.
도 1을 참조하면, 소정 영역에 소자 분리막(12)이 형성된 반도체 기판(11) 상부에 게이트 산화막(13) 및 폴리실리콘막(14)을 형성한 후 게이트 마스크를 이용한 리소그라피 공정 및 식각 공정으로 패터닝하여 게이트 전극을 형성한다. 저농도 불순물 이온 주입 공정으로 반도체 기판(11)상의 소정 영역에 저농도 불순물 영역을 형성한다. 게이트 전극 측벽에 스페이서(15)를 형성한 후 고농도 불순물 이온 주입 공정을 실시하여 LDD 구조의 접합 영역(16)을 형성한다. 그리고, 게이트 전극 상부 및 접합 영역(16) 상부에 코발트 실리사이드막(CoSi2)(17)을 형성한다.Referring to FIG. 1, a gate oxide layer 13 and a polysilicon layer 14 are formed on a semiconductor substrate 11 on which a device isolation layer 12 is formed in a predetermined region, and then patterned by a lithography process and an etching process using a gate mask. To form a gate electrode. A low concentration impurity region is formed in a predetermined region on the semiconductor substrate 11 by a low concentration impurity ion implantation process. After forming the spacer 15 on the sidewall of the gate electrode, a high concentration impurity ion implantation process is performed to form the junction region 16 of the LDD structure. A cobalt silicide layer (CoSi 2 ) 17 is formed over the gate electrode and the junction region 16.
그런데, 반도체 소자의 고집적화에 따라 트랜지스터의 소오스와 드레인의 간격이 좁아지게 되고, 이에 따라 채널의 길이도 짧아지게 되며, 접합 깊이 또한 1000Å 이하로 낮아지게 되는데, 낮은 접합 깊이로 인하여 코발트 실리사이드막을 형성할 때 소자 분리막의 가장자리 부위와 활성 영역의 경계면에서 반도체 기판과 코발트 실리사이드막이 직접 접촉하게 되는 부분(18)이 발생한다. 이 때문에 드레인 전극에 전압을 인가하게 되면 반도체 기판과 코발트 실리사이드막이 직접 접촉되는 부분(18)에서 전류 누설 현상이 발생하게 되어 소자의 동작의 신뢰성을 저하시키게 된다.However, as the semiconductor device is highly integrated, the gap between the source and the drain of the transistor is narrowed, and thus the channel length is shortened, and the junction depth is also lowered to 1000 占 Å or less. The low junction depth may form a cobalt silicide film. At this time, a portion 18 in which the semiconductor substrate and the cobalt silicide layer are in direct contact with each other is formed at the interface between the edge of the device isolation layer and the active region. For this reason, when a voltage is applied to the drain electrode, a current leakage phenomenon occurs in a portion 18 in which the semiconductor substrate and the cobalt silicide film are in direct contact, thereby reducing the reliability of the operation of the device.
본 발명의 목적은 반도체 기판과 코발트 실리사이드막이 직접 접촉되는 것을 방지할 수 있어 누설 전류의 발생을 방지할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a transistor of a semiconductor device capable of preventing direct contact between a semiconductor substrate and a cobalt silicide film and thus preventing leakage current.
본 발명에서는 소오스 및 드레인을 형성하기 위한 이온 주입 공정을 실시할 때 소정의 주입 각도로 고농도 불순물 이온 주입 공정을 실시함으로써 소자 분리막의 가장자리와 활성 영역의 경계면에서 접합 깊이를 충분히 확보할 수 있어 전류 누설을 방지할 수 있도록 한다.In the present invention, when the ion implantation process for forming the source and drain is performed, a high concentration impurity ion implantation process is performed at a predetermined implantation angle, thereby sufficiently securing the junction depth at the interface between the edge of the device isolation layer and the active region, thereby preventing current leakage. To prevent this.
도 1은 종래의 반도체 소자의 트랜지스터 제조 방법을 설명하기 위해 도시한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view of a device shown for explaining a transistor manufacturing method of a conventional semiconductor device.
도 2(a) 및 도 2(b)는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) and 2 (b) are cross-sectional views of devices sequentially shown in order to explain a transistor manufacturing method of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 및 21 : 반도체 기판12 및 22 : 소자 분리막11 and 21: semiconductor substrate 12 and 22: device isolation film
13 및 23 : 게이트 산화막14 및 24 : 폴리실리콘막13 and 23: gate oxide film 14 and 24: polysilicon film
15 및 25 : 스페이서16 및 26 : 접합 영역15 and 25: spacer 16 and 26: junction region
17 및 27 : 텅스텐 실리사이드막17 and 27: tungsten silicide film
18 : 반도체 기판과 코발트 실리사이드막이 직접 접촉되는 부분18: portion where the semiconductor substrate and the cobalt silicide film are in direct contact
본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 반도체 기판 상부의소정 영역에 게이트 산화막 및 폴리실리콘막이 적층된 게이트 전극을 형성하는 단계와, 저농도 불순물 이온 주입 공정을 실시하여 상기 반도체 기판상의 소정 영역에 저농도 불순물 영역을 형성하는 단계와, 상기 게이트 전극 측벽에 스페이서를 형성한 후 소정의 경사 각도로 고농도 불순물 이온 주입 공정을 실시하여 고농도 불순물 영역을 형성함으로써 접합 영역을 형성하는 단계와, 상기 게이트 전극 상부 및 상기 접합 영역 상부에 실리사이드막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In the method of manufacturing a transistor of a semiconductor device according to the present invention, forming a gate electrode in which a gate oxide film and a polysilicon film are stacked in a predetermined region on a semiconductor substrate, and performing a low concentration impurity ion implantation process to perform a low concentration in a predetermined region on the semiconductor substrate. Forming a junction region by forming an impurity region, forming a spacer on the sidewall of the gate electrode, and performing a high concentration impurity ion implantation process at a predetermined inclination angle to form a high concentration impurity region; And forming a silicide film on the junction region.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.
도 2(a) 및 도 2(b)는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) and 2 (b) are cross-sectional views of devices sequentially shown in order to explain a transistor manufacturing method of a semiconductor device according to the present invention.
도 2(a)를 참조하면, 소정 영역에 소자 분리막(22)이 형성된 반도체 기판(21) 상부에 게이트 산화막(23) 및 폴리실리콘막(24)을 형성한 후 게이트 마스크를 이용한 리소그라피 공정 및 식각 공정으로 이들을 패터닝하여 게이트 전극을 형성한다. 할로(halo) 이온 주입 공정을 실시한 후 저농도 불순물 이온 주입 공정을 실시하여 반도체 기판(21)상의 소정 영역에 저농도 불순물 영역을 형성한다. 할로 이온 주입 공정은 2∼4E13atoms/㎠의 붕소 이온을 10∼40keV의 에너지와 25∼45°정도의 주입 각도로 주입하여 실시한다. 한편, 저농도 불순물 이온 주입 공정은 1∼5E14atoms/㎠의 비소 이온을 1∼5keV의 에너지와 0°의 주입 및 회전 각도로 주입하여 실시한다. 게이트 전극 측벽에 스페이서(25)을 형성한다. 스페이서(25)는 전체 구조 상부에 100Å 정도의 두께로 산화막을 형성하고 800Å 정도의 두께로 질화막을 형성한 후 전면 식각 공정을 실시하여 형성한다. 이때, 산화막은 TEOS와 산소를 이용하여 680℃의 온도에서 2분정도의 산화 공정으로 형성하고, 질화막은 DCS와 NH3를 이용하여 760℃의 온도에서 90분정도의 질화 공정으로 형성한다. 이후 소정의 경사를 갖도록 고농도 불순물 이온 주입 공정을 실시하여 반도체 기판(21)상의 소정 영역에 고농도 불순물 영역을 형성함으로써 저농도 불순물 영역과 고농도 불순물 영역이 중첩된 접합 영역(26)을 형성한다. 고농도 불순물 이온 주입 공정은 1∼3E15atoms/㎠의 비소 이온을 1∼5keV의 에너지와 4∼7°의 주입 각도 및 0°의 회전 각도로 주입하여 실시하는데, 회전 각도를 0°부터 90°씩 회전시키면서 4회로 나누어 이온 주입 공정을 실시한다. 이와 같은 주입 각도 및 회전 각도로 이온 주입 공정을 실시함으로써 소자 분리막(22)의 가장자리와 활성 영역의 경계면에서 접합 깊이를 충분히 확보할 수 있다. 이후 1000∼1100℃의 온도에서 10∼20초동안 급속 열처리 공정을 실시한다.Referring to FIG. 2A, after the gate oxide layer 23 and the polysilicon layer 24 are formed on the semiconductor substrate 21 on which the device isolation layer 22 is formed, the lithography process and the etching using the gate mask are performed. These processes are patterned to form gate electrodes. After performing a halo ion implantation process, a low concentration impurity ion implantation process is performed to form a low concentration impurity region in a predetermined region on the semiconductor substrate 21. The halo ion implantation step is carried out by implanting 2 to 4E13 atoms / cm 2 of boron ions at an energy of 10 to 40 keV and an implant angle of about 25 to 45 °. On the other hand, the low concentration impurity ion implantation process is carried out by implanting arsenic ions of 1 to 5E14 atoms / cm 2 at an energy of 1 to 5 keV and an implantation and rotation angle of 0 °. Spacers 25 are formed on the sidewalls of the gate electrodes. The spacer 25 is formed by forming an oxide film with a thickness of about 100 mW over the entire structure, forming a nitride film with a thickness of about 800 mW, and then performing an entire surface etching process. At this time, the oxide film is formed by an oxidation process of about 2 minutes at a temperature of 680 ° C using TEOS and oxygen, and the nitride film is formed by a nitriding process of about 90 minutes at a temperature of 760 ° C using DCS and NH 3 . Thereafter, a high concentration impurity ion implantation process is performed to have a predetermined slope to form a high concentration impurity region in a predetermined region on the semiconductor substrate 21 to form a junction region 26 in which the low concentration impurity region and the high concentration impurity region overlap. The high concentration impurity ion implantation process is performed by implanting 1 to 3E15 atoms / cm 2 of arsenic ions at an energy of 1 to 5 keV, an implantation angle of 4 to 7 °, and a rotation angle of 0 °. The ion implantation process is performed by dividing into four times while making the By performing the ion implantation process at such an implantation angle and rotation angle, the junction depth can be sufficiently secured at the interface between the edge of the device isolation film 22 and the active region. After that, the rapid heat treatment is performed for 10 to 20 seconds at a temperature of 1000 to 1100 ℃.
도 2(b)를 참조하면, 게이트 전극 상부 및 접합 영역(26)의 상부에 코발트실리사이드막(27)을 형성한다. 코발트 실리사이드막(27)은 전체 구조 상부에 코발트막 및 TiN막을 각각 120Å 및 250Å 정도의 두께로 증착한 후 500℃의 온도에서 60초동안 1차 급속 열처리 공정을 실시하고 미반응 코발트막 및 TiN막을 제거한 후 750℃의 온도에서 30초동안 2차 급속 열처리 공정을 실시하여 형성한다.Referring to FIG. 2B, a cobalt silicide layer 27 is formed on the gate electrode and the junction region 26. The cobalt silicide layer 27 is formed by depositing a cobalt layer and a TiN layer on the entire structure at a thickness of about 120 kPa and 250 kPa, respectively, and performing a first rapid heat treatment process at a temperature of 500 ° C. for 60 seconds, and applying an unreacted cobalt film and a TiN film. After removal, it is formed by performing a second rapid heat treatment process for 30 seconds at a temperature of 750 ℃.
상술한 바와 같이 본 발명에 의하면 소정의 주입 각도를 유지하여 고농도 불순물 이온 주입 공정을 실시함으로써 소자 분리막의 가장자리와 활성 영역의 경계면에서 충분한 접합 깊이를 확보할 수 있어 반도체 기판과 코발트 실리사이드막의 직접적인 접촉을 방지할 수 있어 소자의 동작시 발생하는 접합 누설 전류를 방지할 수 있다.As described above, according to the present invention, by performing a high concentration impurity ion implantation process at a predetermined implantation angle, a sufficient junction depth can be secured at the interface between the edge of the device isolation layer and the active region, thereby making direct contact between the semiconductor substrate and the cobalt silicide layer. It is possible to prevent the junction leakage current generated during the operation of the device can be prevented.
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| KR20020053191A (en) * | 2000-12-27 | 2002-07-05 | 박종섭 | Method for reducing a leakage current of semiconductor device |
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| KR20020053191A (en) * | 2000-12-27 | 2002-07-05 | 박종섭 | Method for reducing a leakage current of semiconductor device |
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