KR20040002306A - Method of driving plasma display panel - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel is provided to increase the address period and the sustain period by reducing the reset discharge period. CONSTITUTION: A method for driving a plasma display panel includes the steps of: selecting a first cell in a first address period; and selecting a second cell in a second address period following the first address period. The plasma display panel includes the first cell and the second cell adjacent to each other with commonly owning the scan electrode and the sustain electrode.

Description

Driving method of plasma display panel {METHOD OF DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly to a method of driving a plasma display panel in which a reset discharge period is reduced to increase an address period and a sustain period.

As the information processing system develops and its spread is expanded, the importance of the display device as a means of transmitting visual information is increasing. Cathode ray tubes (CRTs), which dominate the display device, have large size, high operating voltage, and display distortion. Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and plasma display panels (hereinafter referred to as "PDPs") can solve the disadvantages of cathode ray tubes. Flat panel display devices are being developed. Among flat plate display apparatuses, the PDP displays an image by emitting phosphors by 147 nm vacuum ultraviolet rays generated when the He + Xe or Ne + Xe inert mixed gas is discharged. Such a PDP is not only thin and large in size, but also simple in structure, and has a high luminance and high luminous efficiency as compared to other flat display devices. In particular, AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect electrodes from sputtering caused by discharge.

Referring to FIG. 1, an AC surface discharge type PDP includes an upper substrate 10 having a discharge sustaining electrode 16 and a lower substrate 12 having an address electrode 22 formed thereon.

The upper substrate 10 and the lower substrate 12 are spaced in parallel with the partition 14 therebetween. A mixed gas such as Ne + Xe, He + Xe, He + Ne + Xe is injected into the discharge space provided by the upper substrate 10, the lower substrate 12, and the partition wall 14. Two discharge sustaining electrodes 16 are paired in one plasma discharge channel. Each of the discharge sustaining electrodes 16 includes a wide transparent electrode and a narrow metal bus electrode connected to one edge of the transparent electrode. Any one of the pair of discharge sustaining electrodes 16 causes an opposite discharge with the address electrode 22 in response to the scan pulse supplied in the address period, and then adjacent discharge sustain electrodes in response to the sustain pulse supplied in the sustain period. And (16) as a scan electrode causing surface discharge. In addition, another discharge sustaining electrode 16 paired with a scan electrode is used as a sustain electrode to which a sustain pulse is commonly supplied. The dielectric layer 18 and the protective layer 20 are stacked on the upper substrate 10 on which the discharge sustain electrodes 16 are formed. The dielectric layer 18 limits the plasma discharge current and also accumulates wall charges during discharge. The passivation layer 20 is usually made of magnesium oxide (MgO), thereby preventing damage to the dielectric layer 18 caused by sputtering generated during plasma discharge and increasing emission efficiency of secondary electrons. Partition walls 14 for dividing the discharge space are vertically extended to the lower substrate 12. On the surfaces of the lower substrate 12 and the partition walls 14, phosphor layers 24R, 24G, and 24B are excited by vacuum ultraviolet rays to generate visible light of red, green, and blue (R, G, B).

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

2 illustrates a driving waveform of a driving signal supplied to the PDP shown in FIG. 1.

Referring to FIG. 2, the PDP is driven by dividing into a reset period for initializing the full screen, an address period for selecting a cell, a sustain period for maintaining the discharge of the selected cell, and an erase period.

In the reset period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. The rising ramp waveform Ramp-up causes a priming discharge to occur between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. Due to the priming discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

In the set-down period SD, after the rising ramp waveform Ramp-up is supplied, it starts to fall at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up, and thus the base voltage GND or the negative polarity is specified. A falling ramp waveform Ramp-down falling to the voltage level is simultaneously applied to the scan electrodes Y. At the same time, a positive sustain voltage Vs is applied to the sustain electrode Z which is a common electrode, and 0 [V] is applied to the address electrode X. When the falling ramp waveform Ramp-down is applied, a set-down discharge occurs between the scan electrode Y and the sustain electrode Z. This set-down discharge eliminates unnecessary wall charges unnecessary for address discharge among wall charges generated during the setup period SU.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage due to the wall charge generated during the reset period are added, an address discharge is generated in the cell to which the data pulse data is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied.

On the other hand, the sustain electrode Z is supplied with a positive DC voltage (Vz-com) to reduce the voltage difference between the scan electrode (Y) during the set-down period and the address period so as to prevent erroneous discharge from the scan electrode (Y). .

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

In the erasing period, ramp-ers having a small pulse width and a low voltage level are supplied to the sustain electrode Z and remain in the cells turned on by the sustain discharge (hereinafter referred to as an "on cell"). It will erase the charge.

However, in the PDP shown in FIG. 1, since the partition wall 14 is formed in a stripe shape only in the vertical direction, an erroneous discharge may occur because a phosphor coating area is limited and optical and electrical interference between three adjacent cells is large. In addition, the PDP shown in FIG. 1 has a disadvantage in that the luminance decreases as much as the area of the metal bus electrode since the metal bus electrode exists on the light emission path. In order to solve this problem, a PDP having a structure in which a lattice-shaped partition wall (or well-shaped partition wall) including a horizontal partition wall and a vertical partition wall is formed and a metal bus electrode overlaps the partition wall as shown in FIGS. .

3 and 4, another conventional PDP is formed side by side on the upper substrate 30, and includes a scan electrode Y and a sustain electrode each including a metal bus electrode 51 and a transparent electrode 52. Z1 and Z2, the address electrode X formed on the lower substrate 32 to be orthogonal to the scan electrodes Y and the sustain electrodes Z1 and Z2, and the scan electrodes Y and the sustain electrodes Z1 and Z2. And a lattice-shaped partition wall 34 formed on the lower substrate 32 to overlap with each other.

A mixed gas such as Ne + Xe, He + Xe, He + Ne + Xe is injected into the discharge space provided by the upper substrate 30, the lower substrate 32, and the partition wall 34. The dielectric layer 38 and the protective layer 40 are stacked on the upper substrate 30 so as to cover the scan electrodes Y and the sustain electrodes Z1 and Z2. Lattice-shaped partition wall 34 divides the cell in the horizontal and vertical directions. The scan electrodes Y and the metal bus electrodes 51 of the sustain electrodes Z1 and Z2 overlap on the horizontal partition walls of the lattice partition 34. The phosphor layer 44 is formed on the surface of the lower dielectric layer 33 printed on the lower substrate 32 and the horizontal and vertical barrier surfaces of the lattice-shaped partition wall 34.

In the PDP illustrated in FIG. 3, two vertically adjacent cells C1 and C2 share the scan electrode Y and the sustain electrodes Z1 and Z2 as shown in FIG. 4.

FIG. 5 shows waveforms for driving the PDP shown in FIG. 3.

Referring to FIG. 5, the PDP shown in FIG. 3 includes a first reset period for initializing one subfield of a full screen cell, and an upper one of upper and lower adjacent first and second cells C1 and C2. A first address period for selecting one cell C1, a second reset period for erasing the second cell C2 at the same time as causing a sustain discharge to the first cell C1, and first and second adjacent ones The second address period for selecting the lower second cell C2 among the two cells C1 and C2, the sustain period and the sustain discharge for causing the sustain discharge at the same time for the first and second cells C1 and C2. The driving is performed by dividing the wall charge generated by the erase period.

In the first reset period, the rising ramp waveform is applied to all the scan electrodes Y simultaneously. The rising ramp waveform causes a priming discharge to occur between the scan electrode (Y) and the address electrode (X) and between the scan electrode (Y) and the sustain electrode (Z) in the cells of the full screen. Due to the priming discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. Subsequently, a falling ramp waveform which starts to fall at a positive voltage lower than the peak voltage of the rising ramp waveform and falls to 0 [V] is simultaneously applied to the scan electrodes Y. At the same time, a positive sustain voltage Vs is applied to the sustain electrodes Z1 and Z2, and 0 [V] is maintained at the address electrode X. When the falling ramp waveform is applied, unnecessary down wall charges are erased in the first and second cells C1 and C2 while set-down discharge occurs between the scan electrode Y and the sustain electrode Z.

In the first address period, a negative scan pulse is applied to the scan electrode Y and a data pulse synchronized with the scan pulse is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the first reset period are added, an address discharge is generated in the cells to which the data pulse is applied. In the cells selected by the address discharge, that is, the cells selected by the selective writing, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed. During this period, the positive sustain voltage Vs is supplied to the sustain electrodes Z1 and Z2 so as to reduce the voltage difference from the scan electrode Y so that no mis-discharge occurs with the scan electrode Y.

During the second reset period, the falling ramp waveform falling from the sustain voltage level Vs to 0 [V] is applied to the scan electrode Y. At the same time, after 0 [V] is applied to the first sustain electrode Z1, a pulse for maintaining the sustain voltage level is applied to the first sustain electrode Z1, and the second sustain electrode Z2 is initially supplied to the scan electrode Y. The sustain voltage Vs is supplied during the falling section of the falling ramp waveform after a voltage of 0 [V] is applied for the initial sustain voltage holding period of the falling ramp waveform. Then, the first cells C1 maintain the wall charge state at the end of the first address period due to the sustain discharge generated by the voltage difference between the first sustain electrode Z1 and the scan electrode Y. On the other hand, erase discharge occurs in the second cells C2 due to the voltage difference between the scan electrode Y and the second sustain electrode Z2. Due to this erase discharge, the wall cells generated by the address discharge in the first address period are erased and the discharge conditions in the cell are initialized to the state after the reset period ends.

In the second address period, the negative scan pulse is applied to the scan electrode Y and the data pulse synchronized with the scan pulse is applied to the address electrodes X. At the same time, a positive voltage between the sustain voltage level Vs and 0 [V] is applied to the first sustain electrode Z1, and a sustain voltage Vs is applied to the second sustain electrode Z2. At this time, the first cells C1 maintain the previous discharge characteristics, and the cells to which the data pulses are applied among the second cells C2 are addressed as the voltage difference between the scan pulse and the data pulse and the wall voltage in the cell are added. Discharge is generated. In the cells selected by the address discharge, that is, the second cells C2 selected by the selective writing, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed.

In the sustain period, sustain pulses are alternately applied to the scan electrodes Y and the sustain electrodes Z1 and Z2 and 0 [V] is applied to the address electrodes X. Then, the cells selected by the address discharge are added with the wall voltage and the sustain pulse in the cell, and a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrodes Z1 and Z2 whenever the sustain pulse is applied. .

In the erase period, the falling ramp waveform falling from the sustain voltage level Vs to 0 [V] is applied to the scan electrode Y. During this period, the sustain voltage VS is applied to the sustain electrodes Z1 and Z2. During the erase period, an erase discharge occurs in the on cells among the first and second cells due to the voltage difference between the voltage of the falling ramp waveform applied to the scan electrode Y and the voltages of the sustain electrodes Z1 and Z2. As a result of the erasure discharge, the wall charge remaining in the on cells is erased.

However, when the driving waveform shown in FIG. 4 is applied to the PDP shown in FIG. 3, the address period and the sustain period are included as long as a second reset period for separately controlling the discharges of the upper and lower adjacent cells C1 and C2 is included. As the resolution is increased, it is difficult to secure the address period and the sustain period when the resolution is increased, and as shown in FIGS. 6A and 6B, unwanted mis-discharge occurs between the scan electrodes Y and the sustain electrodes Z1 and Z2. As the brightness difference occurs between two adjacent cells C1 and C2, the image quality is deteriorated.

Accordingly, it is an object of the present invention to provide a method of driving a PDP in which the reset discharge period is reduced to increase the address period and the sustain period.

1 is a diagram showing a conventional three-electrode alternating surface discharge plasma display panel.

FIG. 2 is a driving waveform diagram of the plasma display panel shown in FIG. 1.

3 is a view showing another conventional plasma display panel.

4 is an enlarged plan view of a portion of the plasma display panel illustrated in FIG. 3.

FIG. 5 is a driving waveform diagram of the plasma display panel shown in FIG. 3.

6A and 6B are waveform diagrams illustrating an error discharge occurring when the plasma display panel shown in FIG. 3 is driven.

7 is an enlarged plan view of a portion of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view of a cell showing wall charge distribution immediately after a reset period in driving a plasma display panel according to an exemplary embodiment of the present invention.

9 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

10 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

11 is a driving waveform diagram of a plasma display panel according to a third embodiment of the present invention.

In order to achieve the above object, a method of driving a PDP according to an embodiment of the present invention includes selecting a first cell in a first address period, and perpendicular to the first cell in a second address period following the first address period. And selecting a second cell to cut.

A method of driving a PDP according to an embodiment of the present invention further includes supplying erase data for causing an erase discharge in a cell to a data electrode crossing the scan electrode and the sustain electrode.

According to an embodiment of the present invention, a method of driving a PDP may include supplying a first scan pulse to a scan electrode, and a second scan pulse having a polarity opposite to that of the first scan pulse and partially overlapping the first scan pulse to the sustain electrode. It further comprises the step of supplying.

In the method of driving a PDP according to an embodiment of the present invention, the first cell is selected in the early half period of the second scan pulse overlapping the second half of the first scan pulse.

In the driving method of the PDP according to the embodiment of the present invention, the second cell is selected in the second half period of the second scan pulse overlapping the first part of the first scan pulse.

In the method of driving a PDP according to an embodiment of the present invention, a square wave is applied to a scan electrode during a reset period set in advance of the first address period to generate a reset discharge, thereby accumulating negative wall charges on the scan electrode, and scanning electrodes and sustain. A positive wall charge is accumulated on the data electrode and the sustain electrode crossing the electrode.

In the method of driving a PDP according to an embodiment of the present invention, a lamp discharge is applied to a scan electrode in a reset period set before the first address period to generate a reset discharge, thereby accumulating negative wall charges on the scan electrode, A positive wall charge is accumulated on the data electrode and the sustain electrode crossing the sustain electrode.

The driving method of the PDP according to the embodiment of the present invention further includes applying sustain pulses alternately to the scan electrodes and the sustain electrodes during the sustain period following the second address period, thereby causing sustain discharge.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 11.

Referring to FIG. 7, the PDPs according to the embodiment of the present invention are formed side by side on an upper substrate (not shown) and include scan electrodes Y1 to Y3 including metal bus electrodes 61 and transparent electrodes 62, respectively; The sustain electrodes Z1 to Z3, the scan electrodes Y1 to Y3 and the address electrodes X1 to X3 formed on the lower substrate not shown to be orthogonal to the sustain electrodes Z1 to Z3, and the scan electrodes Y1 to Z3. Y3) and a lattice-shaped partition wall 64 formed on the lower substrate so as to overlap the sustain electrodes Z1 to Z3. This PDP has substantially the same structure as the PDP shown in FIGS. 3 and 4. Therefore, a dielectric layer and a protective layer are stacked on the upper substrate to cover the scan electrodes Y1 to Y3 and the sustain electrodes Z1 to Z3. The scan electrodes Y1 to Y3 and the metal bus electrodes 61 of the sustain electrodes Z1 to Z3 overlap each other on the horizontal partition wall of the lattice partition 64. On the lower substrate, a lower dielectric layer is printed over the entire surface, and a lattice partition 64 is formed on the dielectric layer. Phosphors are printed on the surfaces of the lower dielectric layer and the lattice partition 64. Therefore, in the PDP according to the present invention, phosphors are printed on both the horizontal and vertical barrier ribs of the lattice partition 64 so that the brightness can be increased. The metal bus electrode 61 is disposed on the horizontal partition of the lattice partition 64. ), The aperture ratio is increased. In addition, in the PDP according to the present invention, the two upper and lower adjacent cells C1 and C2 share the scan electrode Y and the sustain electrodes Z1 and Z2, so that the number of upper electrodes is at least 1 compared to the PDP shown in FIG. Can be reduced to less than / 2.

In driving the PDP, the driving method of the PDP according to the embodiment of the present invention accumulates negative wall charges on the scan electrode Y when the cells of the full screen are initialized in the reset period as shown in FIG. A positive wall charge is accumulated on (Z) and the address electrode (X) to set the wall voltage condition at which the address can be started.

9 is a waveform diagram illustrating a method of driving a PDP according to a first embodiment of the present invention.

Referring to FIG. 9, in the driving method of the PDP according to the first embodiment of the present invention, after the full screen cells are initialized as shown in FIG. -yscan is sequentially applied and positive scan pulse zcan partially applied to the negative scan pulse -yscan is sequentially applied to the sustain electrodes Z1 to Z3.

In the address period, a negative scan pulse (-yscan) is applied to the first scan electrode Y1 during the t1 period.

During the t2 period, the first scan electrode Y1 maintains the negative scan voltage (-Vysc), and the positive scan pulse zscan is supplied to the first sustain electrode Z1. During the t2 period, the priming discharge occurs due to the voltage difference between the first scan electrode Y1 and the first sustain electrode Z1, and the first cells C1 are selected. In this way, when erase data for selecting an off cell is applied to the address electrodes X1 to X3 within a period t2 in which the first cells C1 are selected, the off cells included in the first cells C1. An erase discharge occurs between the first scan electrode Y1 and the address electrodes X1 to X3 within the wall charges in the off-cell. On the contrary, on cells in which erase data is not applied in the first cells C1 maintain the previous wall voltage without erasing discharge.

During the t3 period, the first sustain electrode Z1 maintains the positive scan voltage Vzsc, and 0 [V] or the ground voltage GND is applied to the first scan electrode Y1 and the second scan electrode Y2 is applied. The negative scan pulse (-yscan) is supplied to the. During the t3 period, the priming discharge occurs due to the voltage difference between the second scan electrode Y2 and the first sustain electrode Z1, and the second cells C1 are selected. In this manner, when erase data data for selecting an off cell is applied to the address electrodes X1 to X3 within a period t3 during which the second cells C2 are selected, the second cell within the off cell included in the second cells C2 is selected. An erase discharge occurs between the scan electrodes Y2 and the address electrodes X1 to X3, so that wall charges are erased in the off-cell. On the contrary, on-cells to which erase data is not applied in the second cells C2 do not discharge erase and maintain the previous wall voltage.

As a result, the driving method of the PDP according to the embodiment of the present invention is an address period in which the upper and lower adjacent cells C1 and C2 drive the PDP sharing the scan electrodes Y1 to Y3 and the sustain electrodes Z1 to Z3. The cells C1 and C2 adjacent to each other up and down without a separate reset period are stably selected by the selective erasing without the influence of crosstalk.

10 is a waveform diagram illustrating a method of driving a PDP according to a second embodiment of the present invention.

Referring to FIG. 10, in the method of driving a PDP according to the second embodiment of the present invention, a reset period for initializing a cell of a full screen, an address period for selecting a cell, and an erase address discharge do not occur. The on-cell C1 is driven by being divided into a sustain period for causing sustain discharge and an erasing period for erasing wall charges generated by the sustain discharge.

The reset period is applied to all the scan electrodes Y at the same time with a square wave reset pulse (sqrst) rising up to a positive peak voltage larger than the sustain voltage. Immediately after the reset period, negative wall charges are accumulated on the scan electrode Y by the spherical Paris-set pulse (sqrst), and positive wall charges are formed on the sustain electrode Z and the address electrode X. Will accumulate. At this time, the wall voltages 81 and 82 rapidly rise to uniform levels in the cells of the full screen.

During the address period, negative scan pulses (-yscan) are sequentially applied to the scan electrodes (Y) as shown in FIG. 9 and have the same pulse width as that of the negative scan pulses (-yscan), and 1 / th of the pulse width. The positive scan pulse zscan delayed by two is sequentially applied to the sustain electrodes Z. At this time, vertically adjacent cells C1 and C2 are sequentially selected, and erase data data is supplied to the address electrode X during the period in which the cells are selected. The off-cells to which the erase data is supplied have a low wall voltage 82 as the wall charges are erased by the erase discharge. On-cells to which the erase data is not supplied have negative scan pulses (-yscan) and The priming discharge generated by the voltage difference between the positive scan pulses zscan maintains the previous wall voltage 81 until the end of the address period.

In the sustain period, the sustain pulse su is applied to the scan electrodes Y and the sustain electrodes Z1 and Z2 alternately, and 0 [V] or the ground voltage GND is applied to the address electrodes X. . Then, since the off-cells selected by the erase address discharge have a low wall voltage 82, no discharge occurs even when a sustain pulse is applied, whereas the on-cells add their high wall voltage 81 and sustain voltage to each cell. Each sustain pulse sustains a sustain discharge.

In the erase period, an erase ramp waveform ers rising from 0 [V] or the base voltage GND to the sustain voltage level Vs is simultaneously applied to the scan electrodes Y. The erase ramp waveform ers erases wall charges generated by the sustain discharge.

11 is a waveform diagram illustrating a method of driving a PDP according to a third embodiment of the present invention.

Referring to FIG. 11, in the driving method of the PDP according to the third embodiment of the present invention, a reset period for initializing a cell of a full screen using a ramp waveform and an address for selecting a cell The driving period is divided into a sustain period for causing sustain discharge and an erase period for erasing wall charges generated by the sustain discharge.

In the reset period, ramp waveforms gradually rising from 0 [V] or the base voltage GND to a positive peak voltage larger than the sustain voltage are simultaneously applied to all the scan electrodes Y. Due to the ramp waveform Ramprst, negative wall charges are accumulated on the scan electrode Y immediately after the reset period, and positive wall charges are accumulated on the sustain electrode Z and the address electrode X as shown in FIG. do. At this time, the wall voltages 81 and 82 gradually increase to uniform levels in the cells of the full screen.

During the address period, negative scan pulses (-yscan) are sequentially applied to the scan electrodes (Y) as shown in FIG. 9 and have the same pulse width as that of the negative scan pulses (-yscan), and 1 / th of the pulse width. The positive scan pulse zscan delayed by two is sequentially applied to the sustain electrodes Z. At this time, vertically adjacent cells C1 and C2 are sequentially selected, and erase data data is supplied to the address electrode X during the period in which the cells are selected. The off-cells to which the erase data is supplied have a low wall voltage 82 as the wall charges are erased by the erase discharge. On-cells to which the erase data is not supplied have negative scan pulses (-yscan) and The priming discharge generated by the voltage difference between the positive scan pulses zscan maintains the previous wall voltage 81 until the end of the address period.

In the sustain period, the sustain pulse su is applied to the scan electrodes Y and the sustain electrodes Z1 and Z2 alternately, and 0 [V] or the ground voltage GND is applied to the address electrodes X. . Then, since the off-cells selected by the erase address discharge have a low wall voltage 82, no discharge occurs even when a sustain pulse is applied. Each sustain pulse sustains a sustain discharge.

In the erase period, an erase ramp waveform ers rising from 0 [V] or the base voltage GND to the sustain voltage level Vs is simultaneously applied to the scan electrodes Y. The erase ramp waveform ers erases wall charges generated by the sustain discharge.

As described above, the driving method of the PDP according to the present invention sequentially applies negative scan pulses to the scan electrodes in order to drive the PDP in which the vertically adjacent cells share the scan electrode and the sustain electrode. The scan pulses and the reverse polarity scan pulses are sequentially applied to the sustain electrodes such that the scan pulses are delayed than the negative scan pulses and some sections overlap each other, thereby stably selecting adjacent cells up and down without setting a separate reset period within the address period. It becomes possible. As a result, the driving method of the PDP according to the present invention can reduce the reset discharge period, increase the address period and the sustain period, and further minimize unwanted mis-discharge during the address period.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

A method for driving a plasma display panel having first and second cells adjacent to each other while sharing a scan electrode and a sustain electrode, the method comprising: Selecting the first cell in a first address period; And selecting the second cell in a second address period subsequent to the first address period. The method of claim 1, And supplying erase data for causing an erase discharge in said cell to a data electrode intersecting said scan electrode and said sustain electrode. The method of claim 1, Supplying a first scan pulse to the scan electrode; And supplying a second scan pulse having a polarity opposite to the first scan pulse and partially overlapping the first scan pulse to the sustain electrode. The method of claim 1, And wherein the first cell is selected in the first half of the second scan pulse overlapping the second half of the first scan pulse. The method of claim 1, And wherein the second cell is selected in a second half period of the second scan pulse overlapping the first portion of the first scan pulse. The method of claim 1, A square wave is applied to the scan electrode in the reset period set before the first address period to cause a reset discharge, thereby accumulating negative wall charges on the scan electrode and intersecting the scan electrode and the sustain electrode with the data electrode. A method of driving a plasma display panel, wherein positive wall charges are accumulated on a sustain electrode. The method of claim 1, Applying a ramp wave to the scan electrode in the reset period set in advance of the first address period to cause a reset discharge, thereby accumulating negative wall charges on the scan electrode and intersecting the scan electrode and the sustain electrode; And a positive wall charge is accumulated on the sustain electrode. The method of claim 1, And applying sustain pulses alternately to the scan electrodes and the sustain electrodes during the sustain period following the second address period to cause sustain discharge.