JPH10307560A - Plasma display panel and its driving method as well as plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make further high gradation and brightness and better black display quality or high contrast. SOLUTION: Surface discharge electrodes containing X-electrodes and Y- electrodes are alternately arranged in parallel and shading masks 41-43 are formed alternately between the surface discharge electrodes to be blind rows B1-B3 so that discharge emission in the blind rows can be shaded. In a resetting period, voltage is applied between the electrodes constituting the blind rows B1-B3 so that voltage applied between the electrodes constituting display rows L1-L4 can be in-phase, to cause priming discharge. The surfaces on the observer' s side of the shading masks 41-43 are colored black, by which outside light is absorbed. Plural address electrodes are arranged in one picture element column and selectively connected to pads located thereon so that plural rows can be selected at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a surface discharge AC type plasma display panel, a method of driving the same, and a plasma display device using the same.

[0002]

2. Description of the Related Art Plasma display panels (PDPs)
Since they are self-luminous, they have good visibility, are thin, and can perform large-screen display and high-speed display. In particular, the surface discharge AC type PDP is suitable for full-color display, is expected in the field of high-definition television, and is required to have high image quality. Higher image quality includes higher definition, higher gradation, higher luminance, lower luminance of black display, higher contrast, and the like. High definition is achieved by narrowing the pixel pitch, high gradation is achieved by increasing the number of subfields in a frame, and high brightness is achieved by increasing the number of sustain discharges. Reducing the luminance of black display is achieved by reducing the amount of light emission during the reset period.

FIG. 30 shows a schematic configuration of a conventional AC type and surface discharge type plasma display panel (PDP) PDP10P. One of the opposing glass substrates (observer side)
, Electrodes X1 to X5 are formed in parallel with each other at an equal pitch, and electrodes Y1 to Y5 are respectively formed in parallel and in pairs. On the other glass substrate, address electrodes A1 to A6 are formed in a direction orthogonal to these electrodes,
A phosphor is entirely coated thereon. Partitions 171 to 177 are provided between the opposing glass substrates in order to prevent the discharge of one pixel from affecting the adjacent pixels and causing erroneous display.
And the partitions 191 to 196 are arranged in a grid pattern so as to cross each other.

[0004] In the surface discharge type, since discharge occurs between adjacent electrodes on the same surface, it is possible to prevent the phosphor formed on the opposing surface from colliding with ions and thereby deteriorating the phosphor. Having. However, since a pair of electrodes are arranged in each of the display rows L1 to L5, narrowing of the pixel pitch is restricted, and high definition is prevented. Further, since the number of electrodes is large, the scale of the driving circuit is increased.

Therefore, a PDP 10Q as shown in FIG.
(JP-A-5-2993 and JP-A-2-220330). In the PDP 10Q, partitions 191 to 199 are arranged along the center line of the electrodes X1 to X5 and Y1 to Y4, which are surface discharge electrodes.
Electrodes X2 to X4 and electrodes Y1 to Y4 excluding 1 and X5
Are shared by display rows adjacent in the address electrode direction.
As a result, the number of electrodes is almost halved, so that the pixel pitch can be narrowed, and higher definition than in the case of FIG. 30 can be achieved. Further, the size of the driving circuit can be reduced.

[0006]

However, due to the full discharge light emission during the reset period, the luminance of black display increases and the display quality deteriorates. Further, since the phosphor is white or light gray, when an image of the PDP is viewed in a bright place, external light is reflected by the phosphor in the non-display row, and the contrast of the image is reduced.

Furthermore, since only one row can be addressed at a time, the address period cannot be reduced, and high gradation by increasing the number of subfields or high brightness by increasing the number of sustain discharges is prevented. In view of the above problems, a general object of the present invention is to provide a plasma display panel, a driving method thereof, and a plasma display device capable of achieving high image quality. It is on the street.

That is, a first object of the present invention is to provide a plasma display panel, a driving method thereof, and a plasma display device capable of suppressing a decrease in black display quality due to full discharge light emission during a reset period. A second object of the present invention is to provide a plasma display panel, a driving method thereof, and a plasma display device capable of improving the contrast of an image by reducing reflected light from a non-display row.

A third object of the present invention is to provide a plasma display panel, a driving method thereof, and a plasma display device capable of shortening the address period by simultaneously addressing a plurality of rows to achieve high gradation or high luminance. Is to do.

[0010]

According to the plasma display panel of the present invention, a plurality of X electrodes and a plurality of Y electrodes are provided in parallel and alternately with each other, as shown in FIG. In a plasma display panel in which a display row is constituted by the X electrodes and the Y electrodes, and a plurality of address electrodes are arranged so as to be spaced apart from and intersect with the X electrodes and the Y electrodes, the adjacent X electrodes and the Y electrodes Among the electrodes, a light shielding body is arranged between the electrodes in the non-display row.

According to this plasma display panel, there is an effect that the black display quality can be suppressed from being deteriorated by the discharge light emission in the non-display row by the light shielding body. According to a second aspect of the present invention, in the plasma display panel according to the first aspect, a phosphor is provided on the address electrode, and the light-shielding body has a darker color on the observer side than the phosphor.

According to this plasma display panel, since the external light is absorbed by the light shields in the non-display rows, the contrast of the image of the PDP placed in a bright place is reduced by the external light reflected by the phosphors in the non-display rows. This has the effect of improving the image quality as compared with the case in which the image is observed by the observer. In the plasma display device according to the third aspect, for example, as shown in FIGS. 25 and 26, a plurality of X electrodes and a plurality of Y electrodes are provided in parallel and alternately with each other, and display is performed by a pair of the X electrode and the Y electrode. A plurality of address electrodes are arranged so as to be spaced apart from and intersect with the X electrodes and the Y electrodes, and a light shield between non-display rows among the adjacent X electrodes and Y electrodes. And an electrode driving circuit for driving the X electrode, the Y electrode, and the address electrode, and the electrode driving circuit discharges between the electrodes constituting the non-display row. Reset means for performing, an address means for performing address discharge between one of the electrode pairs constituting the display row and the address electrode selected in accordance with display data, and selecting a display cell; Display line And a maintaining means for supplying an alternating sustain pulse to the electrode pair to formed.

According to this plasma display device,
The light-shielding member has an effect of suppressing a reduction in black display quality due to light emission during discharge for priming. Although the high-definition is impeded by the light-shielding member, compared with the conventional configuration of FIG. 30, there is no need to form the partitions 191 to 196, so that it is easy to manufacture and the pixel pitch can be further shortened. Play.

According to a fourth aspect of the present invention, in the third aspect, the reset means applies a voltage waveform of the same phase or the same voltage to the pair of electrodes constituting the display row. According to this plasma display device, discharge in a display row is reliably prevented.

In a fifth aspect, for example, as shown in FIGS. 25 and 26, a plurality of X electrodes and a plurality of Y electrodes are provided in parallel and alternately with each other, and a pair of X electrodes and Y electrodes form a display row. And a plurality of address electrodes are disposed so as to be spaced apart from and intersect with the X electrodes and the Y electrodes, and between the adjacent X electrodes and the Y electrodes, a light-shielding body is provided between the electrodes in a non-display row. Is a method for driving a plasma display panel, wherein a discharge is performed between electrodes constituting the non-display row during a reset period, and an electrode constituting the display row is formed during an address period after the reset period has elapsed. An address discharge is performed between one electrode of the pair and the address electrode selected according to the display data to select a display cell, and in a sustain period after the elapse of the address period, the display row is connected. Supplies AC sustain pulse to the electrode pair to formed.

According to a sixth aspect of the present invention, in the fifth aspect, during the reset period, the electrode pairs forming the display row are:
A voltage waveform having the same phase or the same voltage is applied. In the plasma display panel according to the seventh aspect, for example, as shown in FIG. 27, in order to select a display cell, a plurality of address electrode bundles for discharging between scanning electrodes crossing each other are arranged along the substrate. Wherein each address electrode bundle is formed of m (m ≧ m) formed on the substrate along with each other corresponding to one single-color pixel column.
2) an address electrode, a pad disposed above the m address electrodes as viewed from the substrate and corresponding to each single-color pixel along the longitudinal direction of the address electrode, and a longitudinal direction of the address electrode. Along with the contact for regularly connecting each pad to any one of the address electrodes.

According to this plasma display panel, a plurality of rows can be addressed at the same time, and the address period is shortened, so that the number of subframes can be increased and the number of gradations can be increased or the number of sustain discharges can be reduced. This has the effect of increasing the brightness at most. In claim 8, for example, as shown in FIG. 27, in order to select a display cell, a plurality of address electrode bundles for discharging between scanning electrodes crossing each other are formed on the substrate along each other. Each address electrode bundle includes m (m ≧ 2) address electrodes formed on the substrate along with each other corresponding to one single-color pixel column, and above the m address electrodes as viewed from the substrate. A pad arranged corresponding to each single-color pixel along the longitudinal direction of the address electrode, and a contact for regularly connecting each pad to any one of the address electrodes along the longitudinal direction of the address electrode A driving method for a plasma display panel, comprising: simultaneously selecting m scan electrodes facing pads connected to the m address electrodes, and simultaneously corresponding to the m address electrodes. A voltage is applied in accordance with the display data, to scan the scan electrodes in the m units.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a PD according to a first embodiment of the present invention.
P10 is shown. In FIG. 1, pixels are indicated by dotted lines only in the display row L1. For simplicity of explanation, PDP1
The number of pixels of 0 is 6 × 8 = 48 in monochrome pixel conversion. The present invention can be applied to either color or monochrome, and one color pixel corresponds to three monochrome pixels.

The PDP 10 shown in FIG. 31 is used to facilitate manufacture and reduce the pixel pitch for higher definition.
The configuration is such that partitions 191 to 199 are removed from 10Q. In order to prevent erroneous discharge from occurring due to the influence between adjacent display rows due to this removal, the distance between the electrodes L1 to L8 of the surface discharge will be described later.
(In the conventional interlaced scanning, L2, L4, L6, and L8 are completely non-display rows, so that the odd-numbered rows and even-numbered rows are completely non-display rows. Fields scanned rows L1 and L5 and even fields scanned rows L3 and L7).

FIG. 2 shows a state where the space between the opposing surfaces of the color pixel 10a is widened. FIG. 3 shows an electrode X of the color pixel 10a.
1 shows a longitudinal section along 1; On one side of the glass substrate 11,
Transparent electrodes 121 and 122 such as an ITO film are arranged in parallel with each other, and metal electrodes 131 and 132 such as copper are connected to the transparent electrodes 121 and 122, respectively, in order to reduce a voltage drop along the longitudinal direction of the transparent electrodes 121 and 122. It is formed along the upper center line. The transparent electrode 121 and the metal electrode 131 constitute an electrode X1, and the transparent electrode 122 and the metal electrode 132 constitute an electrode Y1. On the glass substrate 11, the electrode X1, and the electrode Y1, a dielectric 14 for retaining wall charges is deposited, and further thereon, an MgO protective film 15 is formed.
Is attached.

On the other hand, the MgO protective film 1 of the glass substrate 16
The address electrodes A1, A2, A3 and partitions 171 to 173 partitioning the address electrodes A1, A2, A3 are formed on the surface facing the electrode 5 in a direction perpendicular to the electrodes X1 and Y1. Partition wall 171
Between the partition 172 and the partition 172, between the partition 172 and the partition 173, and between the partition 173 and the partition 174, the ultraviolet light generated by the discharge enters, and the phosphor 18 emits red light.
1. A phosphor 182 emitting green light and a phosphor 183 emitting blue light are attached. In the discharge space between the phosphors 181 to 183 and the MgO protective film 15, for example, Ne +
Xe Penning mixed gas is sealed.

The partition walls 171 to 174 prevent ultraviolet rays generated by the discharge from being incident on adjacent pixels, and function as spacers for forming a discharge space. Phosphor 1
If the same material is used for 81 to 183, the PDP 10 is for monochrome display. FIG. 4 shows a schematic configuration of a plasma display device 20 using the PDP 10 having the above configuration.

The control circuit 21 converts display data DATA supplied from the outside into data for the PDP 10 and supplies the data to the shift register 221 of the address circuit 22, and also supplies a clock CLK and a vertical synchronization signal supplied from the outside. Based on the VSYNC and the horizontal synchronization signal HSYNC, various control signals are generated and supplied to the components 22 to 27, 281 and 282.

In order to apply voltage waveforms as shown in FIGS. 7 and 8 to the electrodes,
2, the voltages Vaw, Va and Ve are supplied to the odd-numbered Y sustain circuit 24 and the even-numbered Y sustain circuit 25, respectively. Voltage V to each
w, Vx and Vs are supplied.

The numerical value in the box 221 is for identifying elements having the same configuration as each other.
(3) is the third bit of the shift register 221. The same applies to other components. In the address circuit 22, when one row of display data is supplied from the control circuit 21 to the shift register 221 during the address period, the bits 221 (1) to 221 (6) are respectively stored in the latch circuit 222.
Are held in the bits 222 (1) to 222 (6), and switches (not shown) in the drivers 223 (1) to 223 (6) are turned on / off in accordance with the values, and the binary voltage of the voltage Va or 0V is applied. The pattern is supplied to the address electrodes A1 to A6.

The scanning circuit 23 has a shift register 231 and a driver 232. In the address period, each VSYNC is connected to the serial data input terminal of the shift register 231.
Only '1' is supplied in the first address cycle of the cycle, which is shifted in synchronization with the address cycle.
Switches (not shown) in the drivers 232 (1) to (6) are turned on / off by the values of the bits 231 (1) to (4) of the shift register 231, and the selection voltage -Vy or the non-selection voltage -Vc is changed. It is applied to the electrodes Y1 to Y4. That is, the shift of the shift register 231 causes the electrodes Y1 to Y
4 are sequentially selected, and a selection voltage −Vy is applied to the selected electrode Y.
Is applied, and a non-selection voltage −Vc is applied to the non-selection electrode Y. These voltages -Vy and -Vc are supplied from the odd Y sustain circuit 24 and the even Y sustain circuit 25. In the sustain period, the first sustain pulse train is supplied from the odd Y sustain circuit 24 to the odd electrodes Y1 and Y3 of the Y electrodes via the drivers 232 (1) and (3), and the even Y sustain circuit 25 supplies the first sustain pulse train. Driver 2
The first sustain pulse train and the phase of 18 are applied to the even-numbered electrodes Y2 and Y4 of the Y electrodes via 32 (2) and (4).
A second sustain pulse train shifted by 0 ° is supplied.

In the circuit of the electrode X, in the sustain period, the odd-numbered X sustain circuits 26 drive the driver 281 to form odd-numbered electrodes X1, X3 and X5 of the X electrodes.
, The second sustain pulse train is supplied, and the even sustain circuit 27 supplies the first sustain pulse train to the even-numbered electrodes X2 and X4 of the X electrodes. In the reset period, the X-sustain circuits 26 and 27 supply a full-surface write pulse to the electrodes X1 to X5, respectively. In the address period, a pulse train of two address cycles is output from the odd X sustain circuit 26 in response to the scan pulse as shown in FIGS.
A pulse train that is supplied to odd-numbered electrodes X1, X3, and X5 of the electrodes and that is 180 ° out of phase with the pulse train is
The even X sustain circuit 27 supplies the X electrodes to even electrodes X2 and X4.

The circuits 223, 232, 24, 25, 2
6 and 27 are switching circuits for turning on / off the voltage supplied from the power supply circuit 29. FIG. 5 shows a configuration of one frame of a display image. This frame is divided into an odd field and an even field, and each field includes first to third subfields. For each subfield, in the odd field, a voltage having a waveform shown in FIG. 7 is supplied to each electrode of the PDP 10 so that rows L1 and L1 in FIG.
3, L5 and L7 are displayed.
By supplying a voltage having a waveform shown in FIG. 8 to each electrode of P10, FIG.
, L2, L4, L6 and L8 are displayed. First to third
The sustain period in the subfield is T1, 2 respectively.
T1 and 4T1, and in each subfield, sustain discharge is performed a number of times proportional to the length of the period.
As a result, the luminance becomes eight gradations. Similarly, the number of subfields is set to 8, and the ratio of the sustain period is set to 1: 2: 4:
8: 16: 32: 64: 128, the luminance is 256.
It becomes gradation.

The scanning of the display row during the address period is shown in FIG.
(A) are performed in the order of the numbers in the circles. That is, in odd fields, scanning is performed in the order of display rows L1, L3, L5, and L7, and in even fields, scanning is performed in the order of display rows L2, L4, L6, and L8. Next, an operation in an odd field will be described with reference to FIG. W, E, A and S in FIG.
Indicates the time points at which a full write discharge, a full self erase discharge, an address discharge and a sustain discharge occur, respectively. Hereinafter, for simplicity, they are collectively referred to as follows.

X electrode: Electrodes X1 to X5 Odd X electrode: Electrodes X1, X3 and X5 Even X electrode: Electrodes X2 and X4 Y electrode: Electrodes Y1 to Y4 Odd Y electrode: Electrodes Y1 and Y3 Even Y electrode: Electrodes Y2 and Y4 Address electrode: Address electrodes A1 to A6 Vfxy: Discharge start voltage between adjacent X electrode and Y electrode Vfay: Discharge start voltage between opposing address electrode and Y electrode Vwall: Adjacent X electrode The voltage (wall voltage) between the positive wall charge and the negative wall charge due to the wall charge generated by the discharge between the Y electrode. For example, Vfxy = 290V and Vfay = 180V. Further, a space between the address electrode and the Y electrode is referred to as an A-Y electrode, and a space between other electrodes is similarly referred to. (1) Reset period In the reset period, the voltage waveform supplied to the X electrode is the same as the entire write pulse, the voltage waveform supplied to the Y electrode is 0 V and the same, and the voltage supplied to the address electrode is The waveforms are identical for the intermediate voltage pulses.

Initially, the voltage applied to each electrode is 0V. Due to the last sustain pulse in the sustain period before the reset period, a positive wall charge exists on the X electrode side and a negative wall charge exists on the Y electrode side on the MgO protective film 15 of the lighting pixel. Almost no wall charge exists on the X electrode side and the Y electrode side of the unlit pixel. When a ≦ t ≦ b, the voltage Vw is applied to the X electrode.
Reset pulse is supplied, and the voltage Vaw is applied to the address electrode.
Are supplied. For example, Vw = 310V
Where Vw> Vfxy, and X between adjacent XY electrodes, that is, X in display rows L1 to L8 regardless of the presence or absence of wall charges.
The entire-area writing discharge W occurs between the -Y electrodes, and the generated electrons and positive ions are attracted by the electric field by the XY-electrode voltage Vw to generate wall charges of opposite polarity, thereby reducing the electric field strength in the discharge space. , 1 to several μs, the discharge ends. The voltage Vaw is about Vw / 2, and when a reset pulse is applied, AX
Since the voltage between the electrodes and the voltage between the A and Y electrodes are opposite to each other and have substantially the same absolute value, the average of the wall charges attached to the phosphor due to the discharge is substantially zero.

When the reset pulse falls at t = b,
That is, when the applied voltage having the opposite polarity to the wall voltage disappears, X-
The wall voltage Vwall between the Y electrodes becomes higher than the discharge starting voltage Vfxy, and the entire self-erasing discharge E occurs. At this time, since the X electrode, the Y electrode, and the address electrode are all at 0 V, this discharge hardly generates wall charges, and the ions and electrons recombine in the discharge space and are almost completely neutralized. In the space, there are some charges that cannot be recombined, but this space charge plays a role of a pilot in the next address discharge, which facilitates the discharge. This is known as the priming effect.

(2) Address discharge period In the address period, the voltage waveforms supplied to the odd-numbered X electrodes are the same as each other, and the voltage waveforms supplied to the even-numbered X electrodes are the same as each other. The resulting voltage waveforms are the same at the voltage -Vc. Y electrodes are Y1 to Y
4, the scanning pulse of the voltage -Vy is supplied to the selected electrodes, and the non-selected electrodes are set to the voltage -Vc. For example, Vc = Va = 50V and Vy = 150V.

(C ≦ t ≦ d) A scanning pulse of voltage -Vy is supplied to the electrode Y1, and a writing pulse of voltage Va is supplied to the address electrode for a pixel to be turned on. The following relationship is established: Va + Vy> Vfay, an address discharge occurs only in the pixel to be lit, and a wall charge of the opposite polarity is generated to terminate the discharge. At the time of this address discharge, of the electrodes X1 and X2 adjacent to the electrode Y1, the pulse of the voltage Vx is supplied only to the electrode X1. Assuming that the discharge start voltage between the X and Y electrodes when triggered by this address discharge is Vxyt, the following relationship holds: Vx + Vc <Vxyt <Vx + Vy <Vfxy Discharge occurs, and wall charges of opposite polarity to the extent that self-discharge does not occur are generated between the X1 and Y1 electrodes, and the discharge ends. On the other hand, no discharge occurs between the X2 and Y1 electrodes of the display row L2.

(D ≦ t ≦ e) A scanning pulse of a voltage −Vy is supplied to the electrode Y2, a pulse of the voltage Vx is supplied to the even-numbered X electrodes, and a voltage Va is written to a pixel to be turned on to the address electrode. A pulse is supplied, and a write discharge is generated between the X2 and Y2 electrodes of the display row L3 in the same manner as described above to generate wall charges of the opposite polarity.
No discharge occurs between the X3-Y2 electrodes.

Hereinafter, the same operation as described above is performed when e ≦ t ≦ g. In this way, the display rows L1, L3, L5
Then, in the order of L7, a writing discharge of display data occurs for a pixel to be turned on, a positive wall charge is generated on the Y electrode side, and a negative wall charge is generated on the X electrode side. (3) Sustain Period In the sustain period, a sustain pulse train having the same phase and the same voltage Vs is supplied to the odd-numbered X electrodes and the even-numbered Y electrodes, and the sustain pulse train whose phase is shifted by 180 ° (１ ／ cycle) is even. It is supplied to the X electrode and the odd Y electrode. Further, the voltage Ve is supplied to the address electrode in synchronization with the rising of the first sustain pulse, and is maintained until the sustain period ends.

(H ≦ t ≦ p) A sustain pulse of the voltage Vs is supplied to the odd Y electrodes and the even X electrodes. Odd Y-Odd X
The effective voltage of the pixel between the electrodes is Vs + Vwall, and the even number Y
The effective voltage of the pixel between the even X electrodes is Vs-Vwall, and the effective voltage of the pixel between the odd X and even Y electrodes and between the even X and odd Y electrodes is 2 Vwall. The following relationship is satisfied: Vs <Vfxy <Vs + Vwall, 2Vwall <Vfxy, a sustain discharge is generated between the odd-numbered Y-odd-numbered X electrodes, and a wall charge of the opposite polarity is generated to terminate the discharge. No sustain discharge occurs between the other electrodes. Therefore, only the odd display rows L1 and L5 in the odd field are displayed. No sustain discharge occurs between the even-numbered Y electrode and the even-numbered X electrode only at the first time.

(Q ≦ t ≦ r) Sustain pulses of voltage Vs are supplied to odd-numbered X electrodes and even-numbered Y electrodes. Odd number X-odd number Y
The effective voltages of the pixels between the electrodes and between the even Y and even X electrodes are both Vs + Vwall, and the effective voltages between the odd Y and even X electrodes and between the odd X and even Y electrodes are zero. As a result, a sustain discharge is generated between the odd-numbered X-odd-numbered Y electrodes and between the even-numbered Y-even-numbered X electrodes, and wall charges of the opposite polarity are generated to terminate the discharge. No sustain discharge occurs between the other electrodes. Therefore, the display of all the odd display rows L1, L3, L5 and L7 of the odd field is simultaneously enabled.

Thereafter, the same sustain discharge as described above is repeated. In this case, as is apparent from the wall charges described in FIG. 7, the effective voltage of the pixel between the odd Y-even X electrodes and the pixel between the odd X-even Y electrodes in the non-display row is zero. The sustain discharge at the end of the sustain period causes the polarity of the wall charges to be in the state at the beginning of the reset period. Next, the operation in the even field will be described.

In FIG. 1, in the odd field, the electrodes Y1 to Y4 and the electrodes X1 to X4 adjacent to the upper side in FIG.
The display of the line display lines L1, L3, L5 and L7 in pairs with X4 is enabled. In the even-numbered field, a pair of rows of electrodes Y1 to Y4 and electrodes X2 to X5 adjacent to the lower side of FIG.
The display of 2, L4, L6, and L8 may be enabled. In this case, the roles of the electrodes X1 and X2 with respect to the electrode Y1 are reversed, the roles of the electrodes X2 and X3 with respect to the electrode Y2 are reversed, and so on. That is, the voltage waveforms supplied to the grouped odd X electrodes and even X electrodes may be interchanged. FIG. 8 shows such an electrode applied voltage waveform in an even field.

The operation in the even-numbered field is clear from the above description and FIG. 8. In summary, the overall write discharge W and the full self-erase discharge E are performed in the reset period.
In the address period, the electrodes Y1 to Y4 are sequentially selected, and the writing discharge of the display data is performed in the order of the display rows L2, L4, L6, and L8. In the sustain period, these display rows L2,
Simultaneous sustain discharges at L4, L6 and L8 are repeated.

According to the driving method of the first embodiment, the display row of the odd field and the display row of the even field do not affect each other with respect to the discharge.
1 in which the partition walls 191 to 199 are removed from the P10Q, the PDP 10 can be easily manufactured and inexpensive, and the pixel pitch can be reduced to achieve high definition.

[Second Embodiment] In FIG. 7 and FIG.
If the number of pulses can be reduced, power consumption can be reduced. In the address period, the odd X electrode and the even X
If the pulse supplied to the electrode can be made continuous,
The number of pulses can be reduced. To achieve this, the scanning order may be as shown in FIG. That is, the display rows L1, L3, L5, and L7 in the odd-numbered field are further divided into odd-numbered rows and even-numbered rows. The same applies to the even field as to the odd field.

FIG. 9 shows a schematic configuration of a plasma display device 20A according to a second embodiment for performing such a method. In the address period, the electrodes Y1, Y3,
In order to scan in the order of Y2 and Y4, the driver 232 is used.
The output terminal of (2) is connected to the electrode Y3 and the driver 232
The output terminal of (3) is connected to the electrode Y2. In the scanning circuit 23A, the output terminal of the odd Y sustain circuit 24 is connected to the input terminals of the driver 232 (1) and the driver 232 (2), and the output terminal of the even Y sustain circuit 25 is connected to the driver 232 (3) and the driver 232 ( 4) is different from the scanning circuit 23 of FIG. 4 in that it is connected to the input terminal of 4).
Accordingly, the odd X sustain circuit 26A and the even X
The sustain circuit 27A outputs a signal such that voltage waveforms applied to the odd-numbered X electrodes and the even-numbered X electrodes are as shown in FIGS.

The odd X electrode and the even X electrode are respectively
Since it is sufficient to supply one wide pulse in each address period of the odd field and the even field, the power consumption can be reduced as compared with the case of FIG. 4, and the odd X sustain circuit 26A and the even X sustain circuit 27 can be supplied.
A is composed of an odd X sustain circuit 26 and an even X
This is simpler than the sustain circuit 27.

The other points are the same as the first embodiment. [Third Embodiment] In FIG. 7, electrodes X1, X3 and X
5, a pulse of a voltage Vx is supplied commonly to the electrodes X2 and X4, and a pulse of a voltage Vx is supplied commonly to the electrodes X2 and X4.
It is sufficient to sequentially select the electrodes X1 to X4 and supply the pulse of the voltage Vx when sequentially selecting 1 to Y4. By doing so, the number of pulses supplied to the electrodes is reduced, so that power consumption can be reduced.

Therefore, in the plasma display device 20B of the third embodiment, as shown in FIG. 12, a scanning circuit 30 is provided for the X electrode. The scanning circuit 30 has only one component more than the scanning circuit 23 in configuration. In the address period, '1' is supplied from the control circuit 21A to the shift register 301 to the data input terminal of the bit 301 (1) in the odd field, and '1' is supplied to the data input terminal of the bit 301 (2) in the even field. Supplied. During the reset period and the sustain period, the output of the shift register 301 is set to 0.

The other points are the same as in the first embodiment. According to the third embodiment, only necessary pulses are supplied to the X electrodes during the address period, and the power consumption is reduced as compared with the first embodiment. Fourth Embodiment The drive voltage waveforms shown in FIGS. 7 and 8 are the same as each other. If the control signal for obtaining the same drive voltage waveform is output from a common circuit, the circuit configuration is simplified. become.

Therefore, in the fourth embodiment of the present invention, the plasma display device 20C is configured as shown in FIG. In this device, sustain circuits 31, 32 and a switching circuit 33 are used instead of the odd Y sustain circuit 24, the even Y sustain circuit 25, the odd X sustain circuit 26, and the even X sustain circuit 27 in FIG. Output voltage waveforms S1 and S2 of sustain circuits 31 and 32
Are respectively equal to the applied voltage waveforms of the odd-numbered X electrode and the even-numbered X electrode in FIG. 7 as shown in FIG. FIG.
, The changeover circuit 33 includes an interlocking changeover switch 33
1 and 332 and interlocking changeover switches 333 and 33
4 and interlocking changeover switches 335 and 336. The changeover switch is constituted by, for example, an FET.
Switching control of the switching circuit 33 is performed by the control circuit 21B.

In the illustrated state, the drivers 232 (1) to 232 (1)
232 (4) is supplied with 0 V to the input terminal of the driver 28
1 and 282 have voltage waveforms S1 and S2 respectively.
2 are supplied. This corresponds to the reset period and the address period in FIGS. When the changeover switches 331 and 332 are switched from the state of FIG. 13, the voltage waveforms S2 and S1 are supplied to the input terminals of the odd element and the even element of the driver 232, respectively, and correspond to the sustain period of FIG.

From this state, the changeover switches 335 and 33
When the switch 6 is switched, the voltage waveforms S2 and S1 are supplied to the input terminals of the drivers 281 and 282, respectively, corresponding to the sustain period in FIG. According to the plasma display device 20C of the fourth embodiment, the same operation as the device of FIG. 4 can be performed with a simpler configuration than the device of FIG.

[Fifth Embodiment] The features of the apparatus shown in FIG.
It can also be applied to the device of FIG. FIG. 15 shows a plasma display device 20D to which this is applied as a fifth embodiment of the present invention. Sustain circuits 31, 32
The switching circuit 33 performs the same operation as in FIG. 13 based on the control signal from the control circuit 21C.

According to the plasma display device 20D of the fifth embodiment, the same operation as the device of FIG. 12 can be performed with a simpler configuration than the device of FIG. [Sixth Embodiment] In each of the above embodiments, the entire write discharge W and the full self-erasing discharge E are performed in the reset period for each subfield of the odd field in FIG. 5 even though the even field is not displayed. This causes the display quality of black display to deteriorate due to invalid light emission. The same applies to the even field. In the sixth embodiment, in order to reduce this invalid light emission, a voltage having a waveform as shown in FIGS. 16 and 17 is supplied to the electrodes.

The first subfield of FIG. 16 is the same as that of FIG. 7, and light emission by the full write discharge W and the full self erase discharge E also occurs in the non-display row in the reset period. This is because display is performed in the immediately preceding even-numbered field, and wall charges exist, so that it is necessary to eliminate them. However, since no discharge occurs in the address period and the sustain period in the non-display row, it is not necessary to generate the write discharge W and the self-erase discharge E in the non-display row in the reset period after the second subfield of the odd field. .

Therefore, during the reset period after the second subfield of the odd field, the cancel pulse PC of the voltage Vs is supplied to the even Y electrode adjacent to the odd X electrode, so that the voltage between the odd X and even Y electrodes is increased. Voltage to V
It is set to less than fxy-Vwall to prevent discharge.
At this time, if a write pulse of the voltage Vw is supplied to the even-numbered X electrodes, no discharge occurs between the even-numbered X-even-numbered electrodes in the display row.
It is shifted from a to b to t = c to d. As a result, a discharge occurs between the odd-numbered Y electrode and the even-numbered X electrode in the non-display row, so that a cancel pulse PC of the voltage Vs is further supplied to the odd-numbered Y electrode. Since the cancel pulse PC is shifted on the time axis from the write pulse supplied to the odd X electrode, it does not affect the write discharge between the odd X electrode and the odd Y electrode.

At t = ab and t = cd, odd numbers X
A pulse of the voltage Vaw is supplied to the address electrode in accordance with the write voltage supplied to the electrode and the even-numbered X electrode. The operation after t = d is the same as when the cancel pulse PC is not supplied. The reset period of the third and subsequent subfields and the odd field is the same as the reset period of the second subfield.

The case of the even field is the same as the case of the odd field, which is shown in FIG. In the case of the even-numbered field, the voltage waveforms supplied to the odd-numbered X electrodes and the even-numbered X electrodes in FIG. 16 may be replaced with each other for the same reason as described in the first embodiment. Seventh Embodiment FIG. 18 shows a plasma display device 20E according to a seventh embodiment of the present invention.

The schematic configuration of the PDP 10A is the
10, but the way of using the electrodes is different from that of FIG. That is, the electrodes Y1, Y2, and Y3 are not divided into odd and even groups, one electrode X1, X3, and X5 adjacent to the electrodes Y1 to Y3 is an odd X electrode, and the other electrodes X2, X4, and X6 are As even X electrodes, electrode pairs (Y1, X1), (Y2, X3) and (Y3, X5)
And the electrode pairs (Y1, X2), (Y2, X
4) and interlaced display with even display lines of (Y3, X6).

Although a complete non-display row is formed between the even-numbered X-odd-numbered X electrodes, since two display rows are formed by three parallel electrodes and no partition wall is provided in parallel with the surface discharge electrodes, FIG. Thus, the pixel pitch can be made shorter than in the case where two display rows are formed by four parallel electrodes and partition walls are provided in parallel with the surface discharge electrodes, and high definition can be achieved. Further, since the electrodes Y1 to Y3 are not divided into even numbers and odd numbers, the configuration is simpler than in the first embodiment.

FIG. 19 shows a vertical section along the address electrodes of the PDP 10A of FIG. The difference from the configuration of FIG. 2 is that, for the electrodes X1 and X2 on both sides of the electrode Y1, the metal electrodes 131 and 133 are transparent electrodes 121 and 1 respectively.
23, on the side remote from the electrode Y1. The same applies to both sides of the other Y electrodes. By doing so, for example, when a voltage is supplied between the X1 and Y1 electrodes, the electric field on the electrode X1 becomes stronger on the metal electrode 131 side, so that even if the electrode pitch is narrowed for higher definition, The pixel area can be made substantially wider than when the metal electrode 131 is formed at the center line of the transparent electrode 121. Since the non-display row is formed on the opposite side of the electrodes X1 and X2 from the electrode Y1, there is no problem in this case, and the non-display row can be substantially narrowed. In FIG. 19, the width of the transparent electrode 122 is
Although the width is the same as that of the electrode 23, the power consumption of the electrode Y1 to which the scanning pulse is supplied can be reduced by reducing the width.

In FIG. 18, the scanning circuit 23B, the odd-numbered sustain circuit 26B and the even-numbered sustain circuit 27B correspond to the scanning circuit 23 and the odd-numbered X-sustain circuit 2 of FIG.
6 and the even X sustain circuit 27. FIG.
In comparison with the above, one Y sustain circuit 2 is used instead of the odd Y sustain circuit 24 and the even Y sustain circuit 25.
Since 4A may be used, the configuration is simplified.

FIG. 20 shows the display row scanning order in the address period. Since the even X-odd X electrodes are completely non-display rows, if one frame is divided into odd fields and even fields as shown in FIG. 6A, the ratio of the display rows in each field is reduced to 1/3. , Which is not preferable in terms of display quality. The problem is that in odd frames, scanning is performed in the order of display rows L1, L3, and L5, and only display data of odd fields is written.
The problem is solved by scanning in the order of 2, L4 and L6 and writing only the display data of the even field. In this case, the frame configuration corresponding to FIG. 5 is as shown in FIG.

FIG. 22 shows an electrode applied voltage waveform in an odd frame when there are four Y electrodes. In the reset period, a full write discharge W and a full self erase discharge E occur in the display rows L1 to L6 of FIG. 20, but no discharge occurs in a completely non-display row because the voltage between the even X-odd X electrodes becomes 0. . This is different from the case of FIG.

In the address period, since the electrodes Y1 to Y4 are sequentially scanned, one wide pulse is supplied to the odd-numbered X electrodes, so that the power consumption can be reduced as compared with the case of FIG. In the sustain period, a sustain pulse of the voltage Vs is periodically supplied to the Y electrode, a pulse train whose phase is shifted by 180 ° is supplied to the odd X electrode, and an AC sustain pulse is supplied between the odd XY electrodes. Is supplied, and a sustain discharge occurs as in the case of the first embodiment. The even X electrodes are brought to 0V,
As a result, no AC is supplied to the non-display rows between the even-numbered XY electrodes and between the even-numbered and odd-numbered X electrodes, and no discharge occurs between these electrodes.

FIG. 23 shows an electrode applied voltage waveform in an even frame. This waveform is obtained by replacing the voltage waveforms supplied to the odd X electrodes and the even X electrodes in FIG. 22 with each other. According to the seventh embodiment, the interlaced scanning for alternately displaying the odd-numbered frames and the even-numbered frames can shorten the address period by half compared with the case of the non-interlaced scanning. Accordingly, it is possible to increase the number of sub-frames to increase the number of gradations, or to increase the number of sustain discharges to increase the luminance.

[Eighth Embodiment] FIG. 24 shows an eighth embodiment of the present invention.
3 shows a vertical cross section of a part of the PDP 10B of the embodiment along an address electrode. The difference from FIG. 19 is that the electrode Y <b> 1 is composed of only the metal electrode 132 and the transparent electrode 122 is omitted. The same applies to other Y electrodes. Thereby, as described above, the power consumption when the scanning pulse is supplied to the Y electrode is reduced. Further, the pixel pitch can be further reduced.

[Ninth Embodiment] In a discharge for erasing wall charges during a reset period, an address discharge is likely to occur due to a priming effect, and an address discharge voltage can be reduced. However, since discharge light emission occurs on the entire surface, the quality of black display deteriorates. Therefore, in the ninth embodiment, a PDP 10C as shown in FIG. 25 is used to reduce invalid light emission.

The PDP 10C has blind rows B1 to B3 every other electrode between the electrodes of the PDP 10 in FIG. Since the blind rows B1 to B3 are completely non-display rows, non-interlace scanning is performed on the display rows L1 to L4. The blind films (light-shielding masks) 41 to 41 prevent the ineffective light emission in the blind rows B1 to B3 from leaking to the observer side.
43 is formed on the glass substrate 11 corresponding to or between the transparent electrode 121 and the transparent electrode 122 in FIG. 2, for example.

FIG. 26 shows an electrode applied voltage waveform in the reset period and the sustain period in which the address period is omitted. In the figure, PE is an erase pulse, PW is a write pulse,
PS is a sustain pulse. In the reset period, first, an erase pulse PE having a lower voltage than the sustain pulse is supplied to the odd X electrodes and the odd Y electrodes, and all the blind rows B1 to B
At 3, erasing discharge is performed on the wall charges. Then, even X
A write pulse PW having a higher voltage than the sustain pulse is supplied to the electrodes and the even-numbered Y electrodes.
1 to B3, a write discharge is performed, and all the blind rows B1
The wall charges at B3 become almost uniform. The voltage of the write pulse PW is equal to or higher than the discharge start voltage but lower than the voltage Vw in FIG. 7, and no self-erasing discharge occurs after the fall of the write pulse PW. Then, the erasing pulse PE is again supplied to the odd-numbered X electrode and the odd-numbered Y electrode, and the erasing discharge is performed on the wall charges in all the blind rows B1 to B3.
Due to such a discharge in the reset period, space charges that have not been completely recombined flow into the display rows L1 to L4, and an address discharge in the address period is likely to occur.

In the reset period, since the voltage between the electrodes X and Y of all the display rows L1 to L4 becomes 0 V, no discharge is performed, and the occurrence of invalid light emission and the deterioration of black display quality are prevented. The electrode applied voltage waveform during the address period is represented by display rows L1 to L4.
Is the same as before, or the odd field in FIG.
It is the same as when it is regarded as a frame. The sustain period is the same as in FIG.

The blind rows B1 to B3 prevent higher definition than in the first embodiment. However, compared with the conventional configuration of FIG. 30, there is no need to form the partitions 191 to 196, so that manufacturing is easy. And the pixel pitch can be further reduced. Note that the reset period may be the same as the reset period in FIG. 7 to perform the entire write discharge and the entire self-erase discharge.

Further, even in a driving type PDP in which discharge is not performed in the blind rows B1 to B3, the blind film 41
-43 is made darker than the phosphor, preferably black, so that external light can be transmitted to the blind films 41 to 4.
3, the contrast of the image is improved as compared with the case where outside light is reflected by the phosphors in the blind rows B1 to B3 and enters the eyes of the observer in a bright place.

[Tenth Embodiment] FIGS. 27A to 27E
Indicates an address electrode according to the tenth embodiment of the present invention. FIG. 27A is a plan view, and FIGS. 27B to 27E are respectively along the BB line, CC line, DD line, and EE line in FIG. 27A. FIG. FIGS. 28B and 28E also show the configuration around the address electrode, and the configuration of other portions can be easily understood from the relationship with FIG.

A pair of address electrodes A11 and A21 are formed on the glass substrate 16 corresponding to the address electrode A1 of FIG. Pads B11, B21, and B31 are formed in the body corresponding to each pixel (single color).
The address electrode A11 is connected to the pad B21 via the contact C21, and the address electrode A21 is
11 and C31 through pads B11 and B3, respectively.
1 connected. That is, every other pad arranged in one row is connected to the address electrodes A11 and A21. Other address electrodes Akj, pads Bij and contacts Cij, k = 1, 2, i = 1 to 3, j = 1,
The same applies to No. 2.

With such a configuration, arbitrary odd-numbered rows and even-numbered rows, for example, rows of pads B11 to B13 and pads B21
To B23 at the same time and the address electrodes A11 to A11 are selected.
Address pulses for the rows of pads B21 to B23 can be supplied to A13, and simultaneously address pulses for the rows of pads B11 to B13 can be supplied to address electrodes A21 to A23.

Therefore, the address period can be reduced to half of the conventional one, and the sustain discharge period can be lengthened accordingly.
This makes it possible to increase the number of sub-frames to increase the number of gradations, or increase the number of sustain discharges to increase the luminance. The tenth embodiment is applicable to various types of PDPs. [Eleventh Embodiment] FIG. 28 shows an address electrode according to an eleventh embodiment of the present invention. FIG. 28A is a plan view,
FIGS. 28B to 28E respectively show B- in FIG. 28A.
It is sectional drawing along the B line, CC line, DD line, and EE line. FIG. 28B also illustrates the configuration around the address electrodes.

In this embodiment, four address electrodes are formed between the partition walls, pads are formed above and in the phosphor, and one row of pads is connected to four electrode lines in order. In FIG. 28, A11 to A43 are address electrodes, B11 to B43 are pads, and C11 to C43 are contacts. According to the address electrode having such a configuration, it is possible to simultaneously select any two odd rows and any two even rows and supply the address pulse.

[Twelfth Embodiment] FIG. 29 shows a schematic structure of an address electrode according to a twelfth embodiment of the present invention. In this embodiment, the display surface is divided into two regions 51 and 52,
The address electrode A11 is connected to a pad belonging to the region 51, and the address electrode A21 is connected to a pad belonging to the region 52. The same applies to other address electrodes and pads.

According to such a configuration, an address pulse can be supplied by simultaneously selecting an arbitrary display row belonging to the area 51 and an arbitrary display row belonging to the area 52.
The present invention also includes various modified examples. For example, in the above embodiment, the case where the address electrode, the X electrode, and the Y electrode are formed on the substrate facing each other via the discharge space has been described. However, the present invention has a configuration in which these are formed on the same substrate side. It is also applicable to

In the above embodiment, the case where the wall charge is completely erased in the reset period and the wall charge is written in the pixel to be turned on in the address period has been described. Can be also applied to a configuration in which the wall charge is erased from the pixels which are to be turned off during the address period by writing the entire area.

In FIG. 1, the metal electrode 131 is
It may be formed on the back side of the transparent electrode 121, the front side and the back side of the transparent electrode 121, or inside the transparent electrode 121. This is the same for all the metal electrodes in FIGS. 1, 19 and 24.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a surface discharge type PDP according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a state in which a space between opposing surfaces of color pixels of the PDP in FIG. 1 is widened.

FIG. 3 is a longitudinal sectional view of a color pixel of the PDP of FIG. 1 along an electrode X1.

FIG. 4 is a block diagram showing a schematic configuration of the plasma display device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a frame.

FIGS. 6A and 6B are diagrams showing a display row scanning order in an address period.

FIG. 7 shows a PDP driving method according to an embodiment of the present invention.
FIG. 9 is a waveform diagram of an electrode applied voltage in an odd field.

FIG. 8 shows a PDP driving method according to an embodiment of the present invention.
FIG. 7 is a waveform diagram of an electrode applied voltage in an even field.

FIG. 9 is a block diagram illustrating a schematic configuration of a plasma display device according to a second embodiment of the present invention.

FIG. 10 is a diagram showing electrode applied voltage waveforms in odd fields, showing the PDP driving method according to the second embodiment of the present invention.

FIG. 11 is a diagram showing electrode applied voltage waveforms in an even-numbered field, showing the PDP driving method according to the second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a schematic configuration of a plasma display device according to a third embodiment of the present invention.

FIG. 13 is a block diagram illustrating a schematic configuration of a plasma display device according to a fourth embodiment of the present invention.

14 is a diagram showing output voltage waveforms of the sustain circuits 31 and 32 in FIG. 13 together with voltage waveforms applied to address electrodes in odd fields in FIG. 7;

FIG. 15 is a block diagram illustrating a schematic configuration of a plasma display device according to a fifth embodiment of the present invention.

FIG. 16 is a diagram showing electrode applied voltage waveforms in odd fields, showing a PDP driving method according to a sixth embodiment of the present invention.

FIG. 17 is a diagram showing electrode applied voltage waveforms in an even-numbered field, showing the PDP driving method according to the sixth embodiment of the present invention.

FIG. 18 is a block diagram illustrating a schematic configuration of a plasma display device according to a seventh embodiment of the present invention.

19 is a longitudinal sectional view of a part of the PDP of FIG. 18 along an address electrode.

FIG. 20 is a diagram showing a display row scanning order in an address period.

FIG. 21 is a diagram illustrating a configuration of a frame.

FIG. 22 is a diagram showing electrode applied voltage waveforms in an odd-numbered frame, showing the PDP driving method according to the seventh embodiment of the present invention.

FIG. 23 is a diagram showing electrode applied voltage waveforms in an even-numbered frame, showing the PDP driving method according to the seventh embodiment of the present invention.

FIG. 24 is a longitudinal sectional view of a part of a PDP according to an eighth embodiment of the present invention, taken along an address electrode.

FIG. 25 is a schematic configuration diagram of a surface discharge type PDP according to a ninth embodiment of the present invention.

FIG. 26 is a schematic electrode applied voltage waveform diagram showing a PDP driving method according to a ninth embodiment of the present invention.

FIG. 27A is a plan view showing an address electrode according to a tenth embodiment of the present invention, and FIGS. 27B to 27E are respectively BB line, CC line, and D line in FIG. It is sectional drawing along the -D line and the EE line.

FIG. 28A is a plan view showing an address electrode according to the eleventh embodiment of the present invention, and FIGS. 28B to 28E are respectively BB line, CC line, and D line in FIG. It is sectional drawing along the -D line and the EE line.

FIG. 29 is a schematic configuration diagram of an address electrode according to a twelfth embodiment of the present invention.

FIG. 30 is a schematic configuration diagram of a conventional surface discharge type PDP.

FIG. 31 is a schematic configuration diagram of another conventional surface discharge type PDP.

[Explanation of symbols]

 10, 10A to 10C PDP 11, 16 Glass substrate 121 to 123 Transparent electrode 131 to 133 Metal electrode 14 Dielectric 15 MgO protective film 171 to 177 Partition wall 181 to 183 Phosphor 20, 20A to 20E Plasma display device 21, 21A to 21D Control circuit 22 Address circuit 221, 231, 301 Shift register 222 Latch circuit 223, 232, 232A, 28, 302 Driver 23, 23A, 23B Scan circuit 24 Odd Y sustain circuit 24A Y sustain circuit 25 Even Y sustain circuit 26, 26A Odd X sustain circuit 27, 27A Even X sustain circuit 31, 32 Sustain circuit 33 Switching circuit 331-336 Switch A1-A6 Address electrode X1-X5, Y1-Y4 Electrode L1-L5 Display row B1 ~ B3 Blind line

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Yoshikazu Kanazawa 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Fumitaka Asami 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Co., Ltd. (72) Yoshio Ueda 4-1-1, Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture 1-1 Inside Fujitsu Co., Ltd. (72) Tomokatsu Kishi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Shigehisa Tomio 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited

Claims (8)

[Claims] 1. A plurality of X electrodes and a plurality of Y electrodes are provided in parallel and alternately with each other, a display row is constituted by a pair of the X electrodes and the Y electrodes, and is spaced from the X electrodes and the Y electrodes. In a plasma display panel in which a plurality of address electrodes are arranged so as to intersect with each other, a light-shielding member is arranged between electrodes in a non-display row among adjacent X electrodes and Y electrodes. Plasma display panel. 2. The plasma display panel according to claim 1, wherein a phosphor is provided on the address electrode, and the light-shielding body has a darker color on the viewer side than the phosphor. . 3. A plurality of X electrodes and a plurality of Y electrodes are provided in parallel and alternately with each other, a display row is constituted by a pair of the X electrodes and the Y electrodes, and is spaced from the X electrodes and the Y electrodes. A plurality of address electrodes are arranged so as to intersect with each other, and a light-shielding body is arranged between electrodes in a non-display row among the adjacent X electrodes and Y electrodes; , An electrode drive circuit for driving the Y electrode and the address electrode, the electrode drive circuit comprising: reset means for causing a discharge between the electrodes constituting the non-display row; and the electrode constituting the display row. Address means for causing an address discharge to be performed between one of the pair and the address electrode selected in accordance with the display data to select a display cell; and supplying an AC sustaining pulse to the electrode pair constituting the display row. Maintenance means and A plasma display apparatus according to claim Rukoto. 4. The plasma display apparatus according to claim 3, wherein said reset means applies a voltage waveform of the same phase or the same voltage to the pair of electrodes constituting said display row. 5. A plurality of X electrodes and a plurality of Y electrodes are provided in parallel and alternately with each other, a display row is constituted by a pair of the X electrodes and the Y electrodes, and a display row is separated from the X electrodes and the Y electrodes. A plurality of address electrodes are arranged so as to intersect with each other, and a light-shielding body is arranged between electrodes in a non-display row among adjacent X electrodes and Y electrodes. In the reset period, discharge is performed between the electrodes forming the non-display row, and in the address period after the reset period elapses, one electrode of the electrode pair forming the display row is selected according to display data. Address discharge is performed between the address electrode and the selected address electrode, and a display cell is selected, and in a sustain period after the elapse of the address period, an AC sustaining pulse is supplied to an electrode pair forming the display row. The driving method of a plasma display panel according to symptoms. 6. The method according to claim 5, wherein in the reset period, a voltage waveform of the same phase or the same voltage is applied to the electrode pairs forming the display row. 7. A plasma display panel having a plurality of address electrode bundles formed on a substrate along with each other to discharge between scan electrodes that intersect each other in order to select a display cell. Each address electrode bundle includes m (m ≧ 2) address electrodes formed on the substrate along with each other corresponding to one single-color pixel column, and above the m address electrodes as viewed from the substrate, A pad arranged along the longitudinal direction of the address electrode so as to correspond to each single-color pixel; and a contact for regularly connecting each pad to any one of the address electrodes along the longitudinal direction of the address electrode. A plasma display panel comprising: 8. In order to select a display cell, a plurality of address electrode bundles for discharging between opposed and intersecting scan electrodes are formed on a substrate along each other, and each address electrode bundle is M (m ≧ 2) address electrodes formed on the substrate along with each other corresponding to one single-color pixel column, and above the m address electrodes as viewed from the substrate, in the longitudinal direction of the address electrodes And a contact for connecting each pad to any one of the address electrodes regularly along the longitudinal direction of the address electrodes. A driving method, wherein m scanning electrodes opposed to the pads connected to the m address electrodes are simultaneously selected, and the electrodes corresponding to the display data of the corresponding row are simultaneously selected by the m address electrodes. Was applied to scan the scan electrodes in the m units, a method of driving a plasma display panel, characterized in that.