KR20040002218A - manufacturing method of semiconductor device - Google Patents

manufacturing method of semiconductor device Download PDF

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KR20040002218A
KR20040002218A KR1020020037664A KR20020037664A KR20040002218A KR 20040002218 A KR20040002218 A KR 20040002218A KR 1020020037664 A KR1020020037664 A KR 1020020037664A KR 20020037664 A KR20020037664 A KR 20020037664A KR 20040002218 A KR20040002218 A KR 20040002218A
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South Korea
Prior art keywords
ion implantation
gate electrode
semiconductor substrate
insulating film
dummy gate
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KR1020020037664A
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Korean (ko)
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KR100835471B1 (en
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곽병일
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to easily control a threshold voltage of a parasitic transistor by selectively implanting ions into the interface between an active region and an isolation region before a gate electrode is formed by a damascene process, and to improve insulation characteristic and contact resistance characteristic by preventing the boron ions implanted into a junction region from being out-diffused. CONSTITUTION: An isolation layer(13) is formed on a semiconductor substrate to define the active region. A stack structure of a gate insulation pattern and a dummy gate electrode is formed on the semiconductor substrate. An insulation layer spacer is formed on the sidewall of the stack structure. An interlayer dielectric is formed on the resultant structure. The interlayer dielectric is planarized to expose the dummy gate electrode. The dummy gate electrode is eliminated. A photoresist pattern(27) is formed on the resultant structure to expose the isolation region of the semiconductor substrate. Impurity ions are implanted into an interface between the isolation layer and the active region by using the photoresist pattern as an ion implantation mask.

Description

반도체소자의 제조방법{manufacturing method of semiconductor device}Manufacturing method of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 다마신공정으로 금속 게이트전극 형성 전에 소자분리영역과 활성영역의 경계부에 기생 트랜지스터의 문턱전압을 높이는 이온주입공정을 실시하여 소자분리 특성 및 누설전류 특성을 향상시키는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an isolation process and leakage by performing an ion implantation process to increase the threshold voltage of the parasitic transistor at the boundary between the device isolation region and the active region before the metal gate electrode is formed by the damascene process. The present invention relates to a method of manufacturing a semiconductor device for improving current characteristics.

고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.

일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.

그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리절연막이 얇아지는 문제와 버즈빅(bird's beak) 현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method is limited in application to Giga DRAM devices due to the problem of thinning the device isolation insulating film and the bird's beak phenomenon. There is.

그리고, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process becomes difficult to bury the trench region as the design rule decreases as well as the complexity of the process, and when the design rule approaches 0.1 μm, it will be difficult to apply the trench isolation process.

상기 트렌치를 이용한 소자분리공정은 소자분리영역으로 예정되는 반도체기판을 식각하여 트렌치를 형성한 후 매립절연막을 형성하여 상기 트렌치를 매립시킨 다음, 평탄화공정을 실시하여 소자분리절연막을 형성하는 방법이다.The device isolation process using the trench is a method of forming a device isolation insulating film by etching a semiconductor substrate intended to be an isolation region to form a trench, forming a buried insulating film to fill the trench, and then performing a planarization process.

상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 소자분리절연막을 트렌치를 이용한 소자분리공정으로 형성하고 있으나, 이는 반도체기판의 활성영역과 소자분리영역 간의 경계 부분이 함몰하는 모우트(moat) 현상을 유발시켜 기생트랜지스터를 형성하였다. 상기 기생 트랜지스터는 셀 트랜지스터보다 문턱전압이 낮아서 트랜지스터에 험프 현상 및 누설전류를 유발한다. 또한, 소자분리절연막 형성 후 실시되는 고온공정으로 인하여 후속 소오스/드레인영역을 형성하기 위해 주입된 보론이 상기 소자분리절연막으로 이동(boron pile up)하는 현상이 발생하여 절연 특성을 저하시키는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, a device isolation insulating film is formed by a device isolation process using a trench, but this is a moat in which a boundary between an active region and a device isolation region of a semiconductor substrate is recessed. The phenomenon was caused to form a parasitic transistor. The parasitic transistors have lower threshold voltages than cell transistors, causing a hum phenomenon and a leakage current in the transistors. In addition, due to the high temperature process performed after the device isolation insulating film is formed, boron injected to form subsequent source / drain regions may move to the device isolation insulating film, resulting in a problem of deteriorating insulation characteristics. .

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 다마신 방법에 의해 게이트전극을 형성하되, 게이트전극을 형성하기 전에 반도체기판의 활성영역과 소자분리영역의 경계부분에 선택적으로 이온주입공정을 실시하여 기생 트랜지스터의 문턱전압 조절을 용이하게 하고, 열공정에 의해 접합영역에 이온주입된 보론이 외확산되는 것을 방지하여 소자의 절연 특성 및 콘택 저항 특성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the gate electrode is formed by the damascene method, and the ion implantation process is selectively performed at the boundary between the active region and the device isolation region of the semiconductor substrate before the gate electrode is formed. To facilitate the adjustment of the threshold voltage of the parasitic transistor, and to prevent the diffusion of the boron ion implanted into the junction region by the thermal process, thereby improving the insulation and contact resistance characteristics of the device. The purpose is.

도 1 은 일반적인 트랜지스터의 평면도.1 is a plan view of a typical transistor.

도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10 : 반도체기판 11 : 활성영역10 semiconductor substrate 11: active region

13 : 소자분리절연막 15 : 게이트전극13 device isolation insulating film 15 gate electrode

17 : 게이트절연막패턴 19 : 더미게이트전극17 gate insulating film pattern 19 dummy gate electrode

21 : 절연막 스페이서 23 : 층간절연막21 insulating film spacer 23 interlayer insulating film

25 : 트렌치 27 : 감광막패턴25 trench 27 photosensitive film pattern

29 : 필드스톱 이온주입영역 31 : 1차 펀치스톱 이온주입영역29: field stop ion implantation region 31: primary punch stop ion implantation region

33 : 2차 펀치스톱 이온주입영역33: 2nd punch stop ion implantation area

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

반도체기판에 활성영역을 정의하는 소자분리절연막을 형성하는 공정과,Forming a device isolation insulating film defining an active region on the semiconductor substrate;

상기 반도체기판 상부에 게이트절연막패턴과 더미 게이트전극의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate insulating film pattern and a dummy gate electrode on the semiconductor substrate;

상기 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the laminated structure;

전체표면 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;

상기 층간절연막을 평탄화시켜 상기 더미 게이트전극을 노출시키는 공정과,Exposing the dummy gate electrode by planarizing the interlayer insulating film;

상기 더미 게이트전극을 제거하는 공정과,Removing the dummy gate electrode;

전체표면 상부에 상기 반도체기판의 소자분리영역을 노출시키는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the entire surface of the semiconductor substrate to expose the device isolation region of the semiconductor substrate;

상기 감광막패턴을 이온주입마스크로 상기 소자분리절연막과 활성영역의 경계부분만 불순물을 이온주입하는 공정과,Implanting impurities only at a boundary between the device isolation insulating layer and an active region using the photoresist pattern as an ion implantation mask;

상기 이온주입공정은 문턱전압 조절용 이온주입공정, 펀치 스톱 이온주입공정 및 필드 스톱 이온주입공정인 것과,The ion implantation process is a threshold voltage ion implantation process, punch stop ion implantation process and field stop ion implantation process,

상기 펀치 스톱 이온주입공정은 이온주입에너지 및 도즈를 달리 하여 2차례에 걸쳐 실시되는 것을 포함하는 것을 특징으로 한다.The punch stop ion implantation process is characterized in that it is carried out two times with different ion implantation energy and dose.

이하, 첨부된 도면을 참고로 하여 본 발명에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the present invention.

도 1 은 일반적인 트랜지스터의 평면도이고, 도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도로서, 도 2a 내지 도 2c 는 도 1의 선A-A'에 따른 공정 단면도이고, 도 2d 는 선B-B'에 따른 공정 단면도이다. 상기 트랜지스터는 NMOS 또는 PMOS일 수 있다.1 is a plan view of a general transistor, and FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention, and FIGS. 2A to 2C are cross-sectional views along a line A-A 'of FIG. 1. 2D is a cross sectional view along the line B-B '. The transistor may be an NMOS or a PMOS.

먼저, 반도체기판(10)에 활성영역을 정의하는 소자분리절연막(13)을 형성한다. 이때, 상기 소자분리절연막(13)은 반도체기판(10)에 트렌치를 형성한 후 이를 매립하여 형성된 것이다.First, an isolation layer 13 is formed on the semiconductor substrate 10 to define an active region. In this case, the device isolation insulating layer 13 is formed by forming a trench in the semiconductor substrate 10 and then filling it.

다음, 전체표면 상부에 게이트절연막(도시안됨)과 더미 게이트전극용 도전층(도시안됨)의 적층구조를 형성한다. 여기서, 상기 더미 게이트전극용 도전층은 다결정실리콘층으로 형성된 것이다.Next, a stacked structure of a gate insulating film (not shown) and a conductive layer for dummy gate electrodes (not shown) are formed over the entire surface. Here, the conductive layer for the dummy gate electrode is formed of a polycrystalline silicon layer.

그 다음, 게이트전극 마스크를 이용한 사진식각공정으로 상기 적층구조를 식각하여 더미 게이트전극(19)과 게이트절연막패턴(17)을 형성한다.Next, the stacked structure is etched by a photolithography process using a gate electrode mask to form a dummy gate electrode 19 and a gate insulating layer pattern 17.

다음, 전체표면 상부에 소정 두께의 절연막을 형성한 후 전면식각하여 상기 더미 게이트전극(19) 및 게이트절연막패턴(17)의 측벽에 절연막 스페이서(21)를 형성한다. 이때, 상기 절연막 스페이서(21)는 질화막으로 형성된 것이다.Next, an insulating film having a predetermined thickness is formed on the entire surface and then etched to form an insulating film spacer 21 on sidewalls of the dummy gate electrode 19 and the gate insulating film pattern 17. At this time, the insulating film spacer 21 is formed of a nitride film.

그 다음, 전체표면 상부에 층간절연막(23)을 형성한다. (도 2a 참조)Next, an interlayer insulating film 23 is formed over the entire surface. (See Figure 2A)

다음, 상기 층간절연막(23)을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 제거하여 상기 더미 게이트전극(19)을 노출시킨다. (도 2b 참조)Next, the interlayer insulating layer 23 is removed by chemical mechanical polishing (hereinafter, referred to as CMP) to expose the dummy gate electrode 19. (See Figure 2b)

그 다음, 상기 더미 게이트전극(19)을 제거하여 트렌치(25)를 형성한다. 이때, 상기 더미 게이트전극(19)은 습식식각공정에 의해 제거된다. (도 2c 참조)Next, the dummy gate electrode 19 is removed to form the trench 25. In this case, the dummy gate electrode 19 is removed by a wet etching process. (See Figure 2c)

다음, 전체표면 상부에 감광막(도시안됨)을 도포한다.Next, a photoresist (not shown) is applied over the entire surface.

그 다음, 소자분리마스크를 이용한 사진공정으로 반도체기판(10)의 소자분리영역을 노출시키는 감광막패턴(27)을 형성한다.Next, a photosensitive film pattern 27 exposing the device isolation region of the semiconductor substrate 10 is formed by a photolithography process using an device isolation mask.

그 후, 상기 감광막패턴(27)을 이온주입마스크로 사용하여 상기 활성영과 소자분리영역의 경계면에 이온주입공정을 실시하여 필드 스톱 이온주입영역(29), 1차 펀치 스톱 이온주입영역(31) 및 2차 펀치 스톱 이온주입영역(33)을 형성한다.Thereafter, using the photosensitive film pattern 27 as an ion implantation mask, an ion implantation process is performed on the interface between the active region and the device isolation region to form a field stop ion implantation region 29 and a primary punch stop ion implantation region 31. And a secondary punch stop ion implantation region 33.

이때, 상기 이온주입공정은 채널 문턱전압 조절용 이온주입공정, 펀치 스톱 이온주입공정 및 필드 스톱 이온주입공정으로 실시되며, 상기 펀치 스톱 이온주입공정은 이온주입에너지 및 도즈를 변경하여 2차례에 걸쳐 실시한다.In this case, the ion implantation process is performed by the ion implantation process, punch stop ion implantation process and field stop ion implantation process for adjusting the channel threshold voltage, the punch stop ion implantation process is carried out two times by changing the ion implantation energy and dose do.

특히, 상기 이온주입공정은 0.8 × 1012∼ 6.0 × 1012/㎠의 B 또는 BF2를 40 ∼ 100keV의 이온주입 에너지 및 7 ∼ 45。의 틸트(tilt)로 주입하여 실시된다. (도 2d 참조)In particular, the ion implantation step is carried out by injecting B or BF 2 of 0.8 × 10 12 to 6.0 × 10 12 / cm 2 with an ion implantation energy of 40 to 100 keV and a tilt of 7 to 45 degrees. (See FIG. 2D)

그 후, 상기 감광막패턴(27)을 제거한 다음, 상기 트렌치(25)를 금속층으로 매립하여 게이트전극(15)을 형성한다.Thereafter, the photoresist layer pattern 27 is removed, and the trench 25 is buried in a metal layer to form the gate electrode 15.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 다마신 공정을 이용하여 금속 게이트전극을 형성하는 경우 더미 게이트전극을 제거한 후 소자분리마스크를 이용한 사진공정으로 이온주입마스크를 형성한 후 반도체기판의 활성영역과 소자분리영역의 경계 부분에 선택적으로 불순물을 이온주입하여 후속 열공정으로 활성영역에 이온주입된 보론이 외확산되는 것을 방지하여 소자간의 절연 특성을 향상시키고, 기생 트랜지스터에 의한 누설전류의 발생을 감소시키는 동시에 스위칭 속도를 향상시켜 소자의 동작 속도 및 리프레쉬 특성을 향상시키는 이점이 있다.As described above, in the method of fabricating a semiconductor device according to the present invention, when forming a metal gate electrode using a damascene process, after removing the dummy gate electrode, an ion implantation mask is formed by a photolithography process using an element isolation mask. Impurities are selectively implanted into the boundary between the active region and the device isolation region of the semiconductor substrate to prevent the diffusion of boron ion implanted into the active region in a subsequent thermal process, thereby improving the insulation characteristics between the devices, and by means of parasitic transistors. The advantage of reducing the leakage current and improving the switching speed is to improve the operation speed and refresh characteristics of the device.

Claims (3)

반도체기판에 활성영역을 정의하는 소자분리절연막을 형성하는 공정과,Forming a device isolation insulating film defining an active region on the semiconductor substrate; 상기 반도체기판 상부에 게이트절연막패턴과 더미 게이트전극의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate insulating film pattern and a dummy gate electrode on the semiconductor substrate; 상기 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the laminated structure; 전체표면 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface; 상기 층간절연막을 평탄화시켜 상기 더미 게이트전극을 노출시키는 공정과,Exposing the dummy gate electrode by planarizing the interlayer insulating film; 상기 더미 게이트전극을 제거하는 공정과,Removing the dummy gate electrode; 전체표면 상부에 상기 반도체기판의 소자분리영역을 노출시키는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the entire surface of the semiconductor substrate to expose the device isolation region of the semiconductor substrate; 상기 감광막패턴을 이온주입마스크로 상기 소자분리절연막과 활성영역의 경계부분만 불순물을 이온주입하는 공정을 포함하는 반도체소자의 제조방법.And implanting impurities only at the boundary between the device isolation insulating layer and the active region using the photoresist pattern as an ion implantation mask. 제 1 항에 있어서,The method of claim 1, 상기 이온주입공정은 문턱전압 조절용 이온주입공정, 펀치 스톱 이온주입공정 및 필드 스톱 이온주입공정인 것을 특징으로 하는 반도체소자의 제조방법.The ion implantation process is a semiconductor device manufacturing method, characterized in that the threshold voltage adjustment ion implantation process, punch-stop ion implantation process and field stop ion implantation process. 제 2 항에 있어서,The method of claim 2, 상기 펀치 스톱 이온주입공정은 이온주입에너지 및 도즈를 달리 하여 2차례에 걸쳐 실시되는 것을 특징으로 하는 반도체소자의 제조방법.The punch stop ion implantation process is a method of manufacturing a semiconductor device, characterized in that is carried out two times with different ion implantation energy and dose.
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