KR20040002139A - Method for fabricating of semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to reduce fabricating time and cost by forming the source/drain of a high voltage device region and a low voltage device region in the same sequence. CONSTITUTION: Gate electrodes(26a,26b,26c,26d) are formed on a semiconductor substrate(21) which has a high voltage device formation region with high voltage well regions of the first and second conductivity types and a low voltage device formation region with well regions of the first and second conductivity types that are separated from each other. A junction region of the second conductivity type is formed in the high voltage well region of the first conductivity type and the well region of the first conductivity type. A junction region of the first conductivity type is formed in the high voltage well region of the second conductivity type and the well region of the second conductivity type. A gate sidewall(28) is formed on the side surface of the gate electrodes. High density impurities of the second conductivity type are implanted into the junction region of the second conductivity type to form a source/drain region. High density impurities of the first conductivity type are implanted into the junction region of the first conductivity type to form a source/drain region.

Description

Method for fabricating a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices. In particular, in the manufacture of a high voltage transistor device having a high voltage device region and a low voltage device region, the source / drain of the two regions can be formed in the same sequence to reduce manufacturing time and cost. The present invention relates to a method for manufacturing a semiconductor device.

Hereinafter, a high voltage transistor device according to the related art will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view of a high voltage transistor device of the prior art.

Prior art high voltage transistor devices typically have an operating voltage of 12V and the configuration of the device includes a high voltage device part and a low voltage device part for configuring the logic circuit.

In the process of manufacturing such a device, a process for forming a source / drain in a high voltage device region and a low voltage device region for configuring a logic circuit is performed separately.

The source / drain in the high voltage device region adopts a double diffused drain (DDD) structure, and the source / drain in the low voltage device region adopts a lightly doped drain (LDD) structure.

The high voltage transistor device of the prior art first forms well regions in a semiconductor substrate 1 having a high voltage element region and a low voltage element region for constructing a logic circuit by a photolithography process and an ion implantation process.

The well region includes a high breakdown voltage n type well region (HN Well) 2a of a high voltage device region, a high breakdown voltage p well region (HP Well) 2b, and a p type well region P Well of a low voltage device region 3a. ), n-type well region (N Well) 3b is formed by each ion implantation process.

Subsequently, the high voltage device region and the low voltage device region for forming the logic circuit are isolated, and the device isolation layer 4 for device isolation formed in each region is formed.

Gate insulating films 5a and 5b are formed in the high voltage element region and the low voltage element region.

Subsequently, a gate electrode forming material layer is deposited and selectively patterned on the gate insulating layers 5a and 5b to form the gate electrodes 6a, 6b, 6c, and 6d.

A photo mask is selectively formed to form a P-junction region 7a for forming a source / drain into a double diffused drain (DDD) structure in the high withstand voltage n type well region (HN Well) 2a.

Subsequently, a photo mask is selectively formed to form an N-junction region 7b for forming a source / drain into a double diffused drain (DDD) structure in the high breakdown voltage p well region (HP Well) 2b.

The photo mask is selectively formed to form the LDD region 10 in the logic region.

Subsequently, a sidewall forming material layer is formed on the front surface including the gate electrodes 6a, 6b, 6c, and 6d and anisotropically etched to form sidewalls of the respective gate electrodes 6a, 6b, 6c, and 6d. Gate sidewalls 8 are formed.

Then, a photo mask is selectively formed to implant p + impurity ions and n + impurity ions, respectively, to form a high voltage PMOS transistor, a high voltage NMOS transistor, and a PMOS transistor and an NMOS transistor in the high voltage device region and the low voltage device region, respectively. .

In the high voltage transistor device of the prior art, the process is performed by adopting different structures for the high voltage device region and the low voltage device region for configuring the logic circuit, and thus the photolithography process and the ion implantation process must be repeatedly performed.

This has the effect of securing the junction breakdown voltage (BV) and extrapolated threshold voltage (VText) as needed in the high voltage device region.

However, the manufacturing process of such a high voltage transistor device of the prior art has the following problems.

Since the source / drain of the high voltage device region where the high voltage transistor is formed and the low voltage device region where the low voltage transistor is formed to form the logic circuit is different from each other in the DDD structure and the LDD structure, a masking step and an ion implantation step are performed. Should be repeated repeatedly.

That is, HNM, HPM, N +, P + ion implantation in the high voltage device region and a masking process therefor, and NM, PM, N +, P + ion implantation in the low voltage device region and a masking process therefor must be performed separately.

This has the effect of securing sufficient BV and VText, but the process to form the source / drain should be carried out in a total of 6 steps, resulting in an increase in process cost and an increase in manufacturing time, thereby lowering productivity.

SUMMARY OF THE INVENTION The present invention solves this problem of the prior art high voltage transistor device fabrication process, in which the source / drain of the two regions is subjected to the same process in the manufacture of the high voltage transistor device having the high voltage element region and the low voltage element region. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be formed to reduce manufacturing time and cost.

1 is a structural cross-sectional view of a high voltage transistor device of the prior art;

2A-2C are process cross-sectional views of a high voltage transistor device in accordance with the present invention.

Explanation of symbols for the main parts of the drawings

21. Semiconductor substrate 22a. High Voltage n-type Well Region

22b. High pressure p-type well region 23a. p-type well region

23b. n-type well region 24. Device isolation layer

25a.25b. Gate insulating film 26a.26b.26c.26d. Gate electrode

27a. P-junction region 27b. N-junction region

28. Gate Sidewalls 29. Gate Cap Layers

30a.30b. HV PMOS Source / Drain Area

31a.31b. HV NMOS source / drain regions

32a.32b. PMOS source / drain regions

33a.33b. NMOS source / drain regions

The semiconductor device manufacturing method according to the present invention for achieving the above object is a low voltage having a high voltage element formation region having a high voltage resistance well region of the first and second conductivity type, respectively separated and a well region of the first and second conductivity type Forming gate electrodes on a semiconductor substrate having an element formation region; forming a second conductivity type junction region in the high withstand voltage well region and the well region of the first conductivity type; a high withstand voltage well of the second conductivity type Forming a junction region of a first conductivity type in a region and a well region; forming a gate sidewall on side surfaces of the gate electrodes; implanting a second conductivity type high concentration impurity into the second conductivity type junction region; Forming a region, and implanting a first conductivity type high concentration impurity into the first conductivity type junction region to form a source / drain region. .

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A-2C are process cross-sectional views of a high voltage transistor device in accordance with the present invention.

The present invention is to reduce the manufacturing cost and time by forming the source / drain region of the high voltage device region and the low voltage device region for configuring the logic circuit through the same sequence.

First, as shown in FIG. 2A, well regions are formed in a semiconductor substrate 21 having a high voltage device region and a low voltage device region for forming a logic circuit by a photolithography process and an ion implantation process.

The well region is a first conductivity type, that is, a high breakdown voltage n-type well region (HN Well) 22a formed in the high voltage element region, and a second conductivity type, that is, a high breakdown voltage p-type well region (HP Well) 22b. And ion implantation into the second conductivity type, that is, the p type well region (P Well) 23a and the first conductivity type, that is, the n type well region (N Well) 23b formed in the low voltage element region, respectively. Form by process.

Subsequently, the high voltage device region and the low voltage device region for forming the logic circuit are isolated, and the device isolation layer 24 for device isolation formed in each region is formed.

Gate insulating films 25a and 25b are formed in the high voltage device region and the low voltage device region.

Subsequently, a gate electrode forming material layer is deposited on the gate insulating layers 25a and 25b and selectively patterned to form the gate electrodes 26a, 26b, 26c and 26d.

A photomask is selectively formed to form a P-junction in a portion of the high breakdown voltage n-type well region (HN Well) 22a, the n-type well region 23b, and a part of the high breakdown voltage p-type well region (HP Well) 22b. (27a) is formed.

When the P-junction region 27a is formed, gate ion implantation of gate electrodes on the high breakdown voltage n-type well region (HN Well) 22a and the n-type well region 23b is simultaneously performed.

Here, the P-junction region 27a of the n-type well region 23b is intended to replace the LDD ion implantation process for forming a PMOS transistor.

Subsequently, a photo mask is selectively formed to N-junction to a portion of the high breakdown voltage p well region (HP Well) 22b, the p type well region 23a and the high breakdown voltage n type well region (HN Well) 22a. The area 27b is formed.

When the N-junction region 27b is formed, gate ion implantation of gate electrodes on the high breakdown voltage p well region HP well 22b and the p type well region 23a is simultaneously performed.

Here, the N-junction region 27b of the p-type well region 23a replaces the LDD ion implantation process for forming an NMOS transistor.

Here, the arrows for indicating ion implantation in FIG. 2A indicate that the process is divided according to the dotted line and the solid line.

Subsequently, as shown in FIG. 2B, a sidewall forming material layer is formed on the entire surface including the gate electrodes 26a, 26b, 26c, and 26d and anisotropically etched to form the respective gate electrodes 26a, 26b, and 26c. Gate sidewalls 28 are formed on the sides of the edges 26d.

2C, a gate cap layer 29 is formed on each of the gate electrodes 26a, 26b, 26c, and 26d, and a photo mask is selectively formed to form p + impurity ions and n + impurity ions, respectively. HV PMOS source / drain regions 30a and 30b, HV NMOS source / drain regions 31a and 31b, PMOS source / drain regions 32a and 32b in the high voltage device region and the low voltage device region, respectively. NMOS source / drain regions 33a and 33b are formed.

Here, the p + impurity implantation process for forming the HV PMOS source / drain regions 30a and 30b and the p + impurity implantation process for forming the PMOS source / drain regions 32a and 32b are simultaneously performed.

Similarly, an n + impurity implantation process for forming HV NMOS source / drain regions 31a and 31b and NMOS source / drain regions 33a and 33b proceeds simultaneously.

The semiconductor device manufacturing method of the present invention skips the LDD ion implantation process in the low voltage transistor region and proceeds simultaneously with the ion implantation process for forming the DDD structure of the high voltage transistor region.

In the present invention, the design rule may be increased by adopting the DDD structure in the low voltage device region, but in the case of a driver IC in which a high voltage transistor is typically used, the ratio of the low voltage transistor is extremely small compared to that of the high voltage transistor. It does not cause a problem of increasing the size.

In the present invention, a high voltage transistor device having an operating voltage of 8 V is used as an embodiment. However, even when a high voltage transistor device having a different operating voltage is manufactured, a parameter of junction breakdown voltage or extra-textured threshold voltage (VText) is used. Naturally, the present invention can be applied to reduce the process step if it can be secured.

Such a method of manufacturing a semiconductor device according to the present invention has the following effects.

In manufacturing a high voltage transistor device having a high voltage element region and a low voltage element region (logic region), the process step can be reduced by at least two steps.

This can reduce the manufacturing cost of the mask during the ion implantation and photo process, and has the effect of reducing the manufacturing time of the device.

In addition, as the mask process is reduced, the possibility of defects is also reduced, thereby improving manufacturing yield.

Claims (4)

Forming gate electrodes on a semiconductor substrate having a high voltage element formation region having high withstand voltage regions of first and second conductivity types and a low voltage element formation region having well regions of first and second conductivity types; Forming a second conductivity type junction region in the high withstand voltage region and the well region of the first conductivity type; Forming a junction region of a first conductivity type in the high withstand voltage well region and the well region of the second conductivity type; Forming gate sidewalls on sides of the gate electrodes; Implanting a second conductivity type high concentration impurity into the second conductivity type junction region to form a source / drain region, and implanting a first conductivity type high concentration impurity into the first conductivity type junction region to form a source / drain region Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein a gate cap layer is formed on the gate electrodes before the ion implantation process for forming the source / drain regions is performed. 2. The semiconductor device according to claim 1, wherein a high breakdown voltage well region of the first conductivity type and a gate electrode ion implantation on the well region are simultaneously implanted in an ion implantation process for forming the second conductivity type junction region. Manufacturing method. 2. The semiconductor device according to claim 1, wherein a high breakdown voltage well region of said second conductivity type and a gate electrode ion implantation on said well region are simultaneously performed during an ion implantation process for forming a junction region of said first conductivity type. Method of preparation.