KR20040001498A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20040001498A
KR20040001498A KR1020020036716A KR20020036716A KR20040001498A KR 20040001498 A KR20040001498 A KR 20040001498A KR 1020020036716 A KR1020020036716 A KR 1020020036716A KR 20020036716 A KR20020036716 A KR 20020036716A KR 20040001498 A KR20040001498 A KR 20040001498A
Authority
KR
South Korea
Prior art keywords
pattern
arc
semiconductor device
sion
manufacturing
Prior art date
Application number
KR1020020036716A
Other languages
Korean (ko)
Inventor
조성윤
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020020036716A priority Critical patent/KR20040001498A/en
Publication of KR20040001498A publication Critical patent/KR20040001498A/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B66—HOISTING; LIFTING; HAULING
    • B66C—CRANES; LOAD-ENGAGING ELEMENTS OR DEVICES FOR CRANES, CAPSTANS, WINCHES, OR TACKLES
    • B66C15/00—Safety gear
    • B66C15/06—Arrangements or use of warning devices
    • B66C15/065—Arrangements or use of warning devices electrical
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B66—HOISTING; LIFTING; HAULING
    • B66C—CRANES; LOAD-ENGAGING ELEMENTS OR DEVICES FOR CRANES, CAPSTANS, WINCHES, OR TACKLES
    • B66C13/00—Other constructional features or details
    • B66C13/18—Control systems or devices
    • B66C13/40—Applications of devices for transmitting control pulses; Applications of remote control devices
    • B66C13/44—Electrical transmitters
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B66—HOISTING; LIFTING; HAULING
    • B66C—CRANES; LOAD-ENGAGING ELEMENTS OR DEVICES FOR CRANES, CAPSTANS, WINCHES, OR TACKLES
    • B66C23/00—Cranes comprising essentially a beam, boom, or triangular structure acting as a cantilever and mounted for translatory of swinging movements in vertical or horizontal planes or a combination of such movements, e.g. jib-cranes, derricks, tower cranes
    • B66C23/62—Constructional features or details
    • B66C23/64—Jibs
    • B66C23/70—Jibs constructed of sections adapted to be assembled to form jibs or various lengths
    • B66C23/701—Jibs constructed of sections adapted to be assembled to form jibs or various lengths telescopic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B66—HOISTING; LIFTING; HAULING
    • B66C—CRANES; LOAD-ENGAGING ELEMENTS OR DEVICES FOR CRANES, CAPSTANS, WINCHES, OR TACKLES
    • B66C2700/00—Cranes
    • B66C2700/03—Cranes with arms or jibs; Multiple cranes

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce defects and simplify processes when forming a storage node, and prevent striation phenomenon. CONSTITUTION: An oxide layer and an ARC(Anti-Reflective Coating) SiON layer are sequentially formed at the upper portion of a semiconductor substrate(100). An ARC SiON pattern(300a) is formed by selectively removing the ARC SiON layer using an RF(Radio Frequency) of 1-10 MHz under CHF3/CF4/Ar/O2 gas atmosphere. The first oxide pattern is formed by partially removing the oxide layer using the ARC SiON pattern as an etching mask under C4F8/CO/Ar/O2 gas atmosphere. At this time, the semiconductor substrate is not exposed to the outside. Then, the second oxide pattern(200b) is formed by selectively removing the first oxide pattern for exposing the semiconductor substrate.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 스토리지 노드 형성 공정을 단순화시키고 불량을 줄여 수율을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can improve the yield by simplifying the storage node forming process and reducing defects.

일반적으로 반도체 소자를 구성하는 요소중 스토리지 노드(storage node)를 형성하는데 있어서 중요한 점은 정전용량(capacitance)을 충분히 확보하는 것과 캐패시터 사이의 브릿지(bridge) 현상을 방지하는 것이다.In general, an important point in forming a storage node among the elements constituting a semiconductor device is to secure sufficient capacitance and to prevent a bridge between capacitors.

종래 기술에 따른 반도체 소자의 제조방법에 있어서 스토리지 노드를 형성하는 공정을 개략적으로 설명하면 다음과 같다.A process of forming a storage node in the method of manufacturing a semiconductor device according to the prior art will be described as follows.

먼저, 실리콘으로 이루어진 기판상에 옥사이드(oxide)를 증착(oxide deposition)한다. 이후, PR(포토레지스트) 선택비 및 스트라이에이션(striation)으로 인한 캐패시터간의 브릿지를 방지하기 위하여 하드마스크 폴리실리콘(hard mask polysilicon)을 증착한다. 그다음, 스토리지 노드 마스크(storage node mask)를 형성하는 단계를 거쳐 스토리지 노드를 형성한다.First, an oxide is deposited on a substrate made of silicon. Afterwards, hard mask polysilicon is deposited to prevent bridges between capacitors due to PR (photoresist) selectivity and striation. Next, a storage node mask is formed to form a storage node.

그러나, 종래 기술에 따른 반도체 소자의 제조방법에 있어서는 다음과 같은 문제점이 있다.However, the manufacturing method of the semiconductor device according to the prior art has the following problems.

종래 기술에 있어서는 스토리지 노드 형성 공정이 복잡할 뿐만 아니라 하드마스크 폴리실리콘 증착 시간이 상당히 길다. 또한, 증착후 표면이 돌출하는 결함이 많이 발생하여 공정 생산량(throughput) 및 소자특성에도 악영향을 끼치는 문제점이 있다.In the prior art, not only is the storage node formation process complicated, but the hard mask polysilicon deposition time is quite long. In addition, a large number of defects protruding from the surface after deposition may adversely affect the process throughput and device characteristics.

이에 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 PR 배리어(ARC SiON) 공정을 도입하고 FR 진동수(frequency) 감소 및 가우스(Gauss) 변화를 이용하여 스트라이에이션(striation)을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, and an object of the present invention is to introduce a PR barrier (ARC SiON) process and to use the FR frequency reduction and the Gaussian variation. The present invention provides a method for manufacturing a semiconductor device that can prevent (striation).

도 1 내지 도 4는 본 발명에 따른 반도체 소자의 제조방법을 도시한 공정별 단면도.1 to 4 are cross-sectional views showing processes for manufacturing a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100; 반도체 기판200; 산화막100; A semiconductor substrate 200; Oxide film

200a,200b; 산화막 패턴300,300a; ARC SiON막200a, 200b; Oxide film patterns 300 and 300a; ARC SiON Film

400,400A; PR 패턴500; 폴리머400,400A; PR pattern 500; Polymer

600,600a,600b; 홀600,600a, 600b; hall

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은, 반도체 기판상에 산화막과 ARC SiON막을 순차로 형성하는 제1단계; CHF3/CF4/Ar/O2가스와 1~10MHz의 RF 진동수 및 자력선속밀도가 0인 조건으로 상기 ARC SiON막을 선택적으로 제거하여 ARC SiON 패턴을 형성하는 제2단계; 상기 ARC SiON 패턴을 마스크로 하고, C4F8/CO/Ar/O2가스와 1~10MHz의 RF 진동수 및 자력선속밀도가 0인 조건으로 상기 기판이 노출되지 않을 정도로 상기 산화막을 선택적으로 일부 제거하여 산화막 패턴내에 홀을 형성하는 제3단계; 및 상기 기판이 노출되도록 상기 ARC SiON 패턴을 마스크로 하는 식각으로 상기 산화막 패턴을 선택적으로 제거하는 제4단계를 포함하는 것을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises a first step of sequentially forming an oxide film and an ARC SiON film on a semiconductor substrate; A second step of forming an ARC SiON pattern by selectively removing the ARC SiON film under the condition that a CHF 3 / CF 4 / Ar / O 2 gas and an RF frequency and magnetic flux flux density of 1 to 10 MHz are 0; The ARC SiON pattern is used as a mask, and the oxide film is selectively partially partially exposed so that the substrate is not exposed under the condition that the C 4 F 8 / CO / Ar / O 2 gas and the RF frequency and magnetic flux density of 1 to 10 MHz are 0. Removing and forming a hole in the oxide film pattern; And selectively removing the oxide layer pattern by etching using the ARC SiON pattern as a mask so that the substrate is exposed.

본 발명에 의하면, 일련의 공정이 모두 인시튜로 진행되기 때문에 지연시간(delay time) 차이는 거의 없고 이전 단계에서 스트라이에이션(striation)을 최소화시킨 후에 시각하기 때문에 캐패시터간의 브릿지가 방지된다.According to the present invention, there is almost no difference in delay time since a series of processes all proceed in situ, and the bridge between capacitors is prevented because it is visualized after minimizing the striation in the previous step.

이하, 본 발명에 따른 반도체 소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 4는 본 발명에 따른 반도체 소자의 제조방법을 도시한 공정별 단면도이다.1 to 4 are cross-sectional views of processes illustrating a method of manufacturing a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 제조방법은, 도 1에 도시된 바와 같이, 먼저 1단계로서 반도체 기판(100)상에 산화막(200)과 ARC SiON막(300;anti reflective coating SiON film)을 순차로 형성한다.In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, first, an oxide film 200 and an ARC SiON film 300 (anti reflective coating SiON film) are sequentially formed on the semiconductor substrate 100 in one step. Form.

상기 ARC SiON막(300)은 상기 산화막(200)의 증착후 마스크 공정을 용이하게 위하여 형성되는 PR 배리어(photoresist barrier) 역할을 한다.The ARC SiON film 300 serves as a PR barrier (photoresist barrier) formed to facilitate a mask process after deposition of the oxide film 200.

그런다음, 일정한 형태로 상기 산화막(200)을 패터닝하기 위하여 상기 ARC SiON막(300)상에 일정한 형태의 PR 패턴(400)을 형성한다.Then, in order to pattern the oxide film 200 in a constant shape, a PR pattern 400 having a certain shape is formed on the ARC SiON film 300.

이어서, 도 2에 도시된 바와 같이, 2단계로서 상기 ARC SiON막(300)을 선택적으로 제거하여 ARC SiON막 패턴(300a)을 형성한다.Subsequently, as shown in FIG. 2, the ARC SiON film 300 is selectively removed to form an ARC SiON film pattern 300a in two steps.

이때, 상기 ARC SiON막(300)에 대한 선택적 제거 공정은 MERIE(magnetron enhanced reactive ion etcher) 장비를 사용하여 진행하는데 그 진행조건은 CHF3/CF4/Ar/O2가스와 1~10MHz의 RF 진동수 및 자력선속밀도(Gauss)가 0으로 조정한다.At this time, the selective removal process for the ARC SiON film 300 is carried out using a magnetron enhanced reactive ion etcher (MERIE) equipment, the progress conditions are CHF 3 / CF 4 / Ar / O 2 gas and RF of 1 ~ 10MHz The frequency and magnetic flux density (Gauss) are adjusted to zero.

상기와 같이 낮은 RF 진동수와 자력선속밀도가 없는 상태이므로 이온 밀도(ion density)가 줄어 평균자유경로(mean free path)가 증가될 뿐 아니라 이온(ion)의 직진성이 높아지고 충격(bombardment)도 증가하여 상기 PR 패턴(400a) 및 ARC SiON막 패턴(300a) 측벽에의 폴리머(500) 형성이 용이해진다. 또한, 측면(lateral) 방향으로의 식각 특성이 거의 없고 PR 선택비도 좋아 스트라이에이션(striation; side roughness)를 방지하는데 매우 효과적이다.Since there is no low RF frequency and magnetic flux density as described above, the ion density is reduced and the mean free path is increased, the ion straightness is increased and the bombardment is also increased. Formation of the polymer 500 on the sidewalls of the PR pattern 400a and the ARC SiON film pattern 300a is facilitated. In addition, there is little etch characteristic in the lateral direction and good PR selectivity, which is very effective in preventing side roughness.

그다음, 도 3에 도시된 바와 같이, 3단계로서 상기 ARC SiON막 패턴(300a)을 마스크로 하는 식각으로 상기 기판(100)이 노출되지 않을 정도로 상기 산화막(200)을 선택적으로 일부 제거하여 산화막 패턴(200a)내에 홀(600a)을 형성한다.Next, as shown in FIG. 3, the oxide layer pattern may be selectively removed by partially removing the oxide layer 200 to the extent that the substrate 100 is not exposed by etching using the ARC SiON layer pattern 300a as a mask in three steps. The hole 600a is formed in 200a.

이때, 상기 산화막(200)에 대한 선택적 제거 공정은 C4F8/CO/Ar/O2가스와 1~10MHz의 RF 진동수 및 자력선속밀도가 0인 조건으로 전단계와 동일한 장비인 MERIE를 사용하여 인시튜(in-situ)로 예를 들어 약 1분 정도 진행한다.At this time, the selective removal process for the oxide film 200 is a C 4 F 8 / CO / Ar / O 2 gas and 1 ~ 10MHz RF frequency and magnetic flux flux density of 0 conditions using the same equipment as the previous step using MERIE Go on in-situ, for example, about 1 minute.

이어서, 도 4에 도시된 바와 같이, 4단계로서 상기 ARC SiON막 패턴(300a)을 마스크로 하는 식각 공정, 예를 들어, 분당 5,000Å 정도의 고식각률로 상기 산화막 패턴(200a)을 다시 한번 선택적으로 식각한다.Subsequently, as illustrated in FIG. 4, an etching process using the ARC SiON film pattern 300a as a mask as a fourth step, for example, selectively selecting the oxide film pattern 200a at a high etch rate of about 5,000 GPa / min. Etch to

그리하여, 재차 선택적으로 식각된 산화막 패턴(200b)을 관통하고 상기 기판(100) 일부 표면이 노출되는 홀(600b)을 완성한다. 이때의 식각 공정은 수십 MHz의 진동수를 갖는 RF 조건으로 인시튜(in-situ) 진행한다.Thus, the hole 600b penetrating through the selectively etched oxide film pattern 200b and exposing a part of the surface of the substrate 100 is completed. At this time, the etching process is performed in-situ at an RF condition having a frequency of several tens of MHz.

계속하여 예정된 후속공정을 진행하여 스토리지 노드를 포함한 반도체 소자를 완성한다.The next step is to proceed to complete the semiconductor device including the storage node.

상기 일련의 공정이 모두 인시튜로 진행되기 때문에 지연시간(delay time) 차이는 거의 없고 이전 단계에서 스트라이에이션(striation)을 최소화시킨 후에 시각하기 때문에 캐패시터간의 브릿지가 방지된다.Since all of the above processes are performed in situ, there is almost no difference in delay time and bridges between capacitors are prevented because they are visualized after minimizing striation in the previous step.

본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method according to the present invention has the following effects.

기존의 스토리지 노드 하드 마스크 폴리실리콘(storage node hard mask polysilicon) 공정을 적용한 스토리지 노드 형성시 공정의 복잡성 및 결함(defect)을 줄이고자 본 발명은 PR 배리어(ARC SiON) 공정을 도입하고 이의 진행시 발생되는 스트라이에이션(striation)을 RF 진동수(frequency)의 감소와 가우스(Gauss) 변화를 이용하는 것이다. 따라서, 본 발명은 소자 특성을 향상시키고 생산량도 증대시킬 수 있는 효과가 있는 것이다.The present invention introduces a PR barrier (ARC SiON) process to reduce the complexity and defects in forming a storage node applying a conventional storage node hard mask polysilicon process. The resulting striation is the reduction of RF frequency and Gaussian variation. Therefore, the present invention has the effect of improving the device characteristics and increase the yield.

Claims (3)

반도체 기판상에 산화막과 ARC SiON막을 순차로 형성하는 제1단계;A first step of sequentially forming an oxide film and an ARC SiON film on a semiconductor substrate; CHF3/CF4/Ar/O2가스와 1~10MHz의 RF 진동수 및 자력선속밀도가 0인 조건으로 상기 ARC SiON막을 선택적으로 제거하여 ARC SiON 패턴을 형성하는 제2단계;A second step of forming an ARC SiON pattern by selectively removing the ARC SiON film under the condition that a CHF 3 / CF 4 / Ar / O 2 gas and an RF frequency and magnetic flux flux density of 1 to 10 MHz are 0; 상기 ARC SiON 패턴을 마스크로 하고, C4F8/CO/Ar/O2가스와 1~10MHz의 RF 진동수 및 자력선속밀도가 0인 조건으로 상기 기판이 노출되지 않을 정도로 상기 산화막을 선택적으로 일부 제거하여 산화막 패턴내에 홀을 형성하는 제3단계; 및The ARC SiON pattern is used as a mask, and the oxide film is selectively partially partially exposed so that the substrate is not exposed under the condition that the C 4 F 8 / CO / Ar / O 2 gas and the RF frequency and magnetic flux density of 1 to 10 MHz are 0. Removing and forming a hole in the oxide film pattern; And 상기 기판이 노출되도록 상기 ARC SiON 패턴을 마스크로 하는 식각으로 상기 산화막 패턴을 선택적으로 제거하는 제4단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And selectively removing the oxide layer pattern by etching using the ARC SiON pattern as a mask so that the substrate is exposed. 제1항에 있어서,The method of claim 1, 상기 제1단계, 제2단계, 제3단계 및 제4단계는 인시튜(in situ)로 진행되는 것을 특징으로 하는 반도체 소자의 제조방법.The first step, the second step, the third step and the fourth step of manufacturing a semiconductor device, characterized in that proceed in situ (in situ). 제1항에 있어서,The method of claim 1, 상기 제2단계, 제3단계 및 제4단계는 MERIE (magnetron enhanced reactive ion etcher) 장비를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The second, third and fourth steps of manufacturing a semiconductor device, characterized in that using the magnetron enhanced reactive ion etcher (MERIE) equipment.
KR1020020036716A 2002-06-28 2002-06-28 Method for manufacturing semiconductor device KR20040001498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020036716A KR20040001498A (en) 2002-06-28 2002-06-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020036716A KR20040001498A (en) 2002-06-28 2002-06-28 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20040001498A true KR20040001498A (en) 2004-01-07

Family

ID=37313250

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020036716A KR20040001498A (en) 2002-06-28 2002-06-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20040001498A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100626743B1 (en) * 2004-07-29 2006-09-25 주식회사 하이닉스반도체 Forming method of pattern in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100626743B1 (en) * 2004-07-29 2006-09-25 주식회사 하이닉스반도체 Forming method of pattern in semiconductor device

Similar Documents

Publication Publication Date Title
US6559049B2 (en) All dual damascene oxide etch process steps in one confined plasma chamber
US6316169B1 (en) Methods for reducing profile variation in photoresist trimming
US5968844A (en) Method for etching nitride features in integrated circuit construction
US20050181604A1 (en) Method for structuring metal by means of a carbon mask
US7018780B2 (en) Methods for controlling and reducing profile variation in photoresist trimming
US5763327A (en) Integrated arc and polysilicon etching process
JPH09283503A (en) Formation of semiconductor slope contact hole using high-density plasma etching device
JPH0945633A (en) Method for forming fine hole of semiconductor integrated circuit device
US6027959A (en) Methods for in-situ removal of an anti-reflective coating during a nitride resistor protect etching process
US5968278A (en) High aspect ratio contact
US6066567A (en) Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process
KR20040001498A (en) Method for manufacturing semiconductor device
KR100741921B1 (en) Method of Etching Metal Layer in Semiconductor Device
US6613680B2 (en) Method of manufacturing a semiconductor device
KR100607761B1 (en) Seasoning method of etching chamber for fabricating semiconductor device
KR100791676B1 (en) Method for forming capacitor
KR100607760B1 (en) Method for cleanning etching chamber of semiconductor device
KR20000061225A (en) Method for fabricating trench of semiconductor device
KR100434312B1 (en) Method for making contact hole in semiconductor device
JPH05129253A (en) Production of semiconductor device
KR100188645B1 (en) Via plug forming method of semiconductor device
KR100255164B1 (en) Polysilicon/oxide of semiconductor material etching method
JPH07135198A (en) Etching
KR100576439B1 (en) Method for cleanning etching chamber of semiconductor device
KR100283409B1 (en) Etching method of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination