KR200309900Y1 - Vertical Chip Size Package - Google Patents
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- KR200309900Y1 KR200309900Y1 KR2019970045411U KR19970045411U KR200309900Y1 KR 200309900 Y1 KR200309900 Y1 KR 200309900Y1 KR 2019970045411 U KR2019970045411 U KR 2019970045411U KR 19970045411 U KR19970045411 U KR 19970045411U KR 200309900 Y1 KR200309900 Y1 KR 200309900Y1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 고안은 버티컬 칩 사이즈 패키지에 관한 것으로, 일반적인 반도체 패키지는 리드들이 몰딩부의 외측으로 돌출형성되어 경박단소화에 한계가 있고, 피시비 상면에 실장시 실장면적을 많이 차지하는 문제점이 있었다. 본 고안 버티컬 칩 사이즈 패키지는 칩(11)의 일측면 하단부에 다수개의 칩패드(12)를 형성하고, 그 칩패드(12)들에 리드(13)를 부착하며, 그 리드(13)들을 감싸도록 부분적으로 몰딩부(14)를 형성하고, 상기 리드(13)들에 접속되도록 패턴(15)이 내설된 받침대(16)를 몰딩부(14)의 하측에 설치하여, 외부단자가 되는 리드들을 일측면에 설치함으로써 패키지를 경박단소화시키는 효과가 있고, 피시비 기판에 실장시 수직방향으로 실장되어 종래 일반적인 패키지 보다 실장면적을 감소되는 효과가 있다.The present invention relates to a vertical chip size package, the general semiconductor package has a problem that the leads are formed to protrude to the outside of the molding portion has a limitation in light and short reduction, occupy a lot of the mounting area when mounted on the upper surface of the PCB. In the vertical chip size package of the present invention, a plurality of chip pads 12 are formed at a lower side of one side of the chip 11, the leads 13 are attached to the chip pads 12, and the leads 13 are wrapped. The molding part 14 is partially formed so as to be connected to the leads 13, and the pedestal 16 in which the pattern 15 is embedded is installed below the molding part 14 so as to connect the leads to the external terminals. By installing on one side, the package can be made light and small in size, and when mounted on a PCB substrate, it is mounted in a vertical direction, thereby reducing the mounting area than a conventional general package.
Description
본 고안은 버티컬 칩 사이즈 패키지(VCSP: VERTICAL CHIP SIZE PACKAGE)에 관한 것으로, 특히 패키지를 경박단소화 시킬뿐아니라, 실장면적을 감소시키도록하는데 적합한 버티컬 칩 사이즈 패키지에 관한 것이다.The present invention relates to a vertical chip size package (VCSP), and more particularly to a vertical chip size package suitable for reducing the package size and reducing the mounting area.
도 1은 일반적인 반도체 패키지의 구성을 보인 종단면도로서, 도시된 바와 같이, 일반적인 반도체 패키지는 리드 프레임(1)의 패들(1a) 상면에 반도체 칩(2)이 접착제(3)로 고정부착되어 있고, 그 칩(2)의 주변에는 다수개의 인너리드(1b)가 설치되어 있어서 상기 칩(2)의 상면에 형성되어 있는 칩패드(2a)들과 인너리드(1b)들은 각각 금속와이어(4)로 연결되어 있으며, 상기 칩(2), 금속와이어(4), 인너리드(1b)들의 일정부분을 감싸도록 칩(2)을 보호하기 위한 몰딩부(5)가 형성되어 있고, 몰딩부(5)의 외측으로는 상기 인너리드(1b)들에 연장되도록 아웃리드(1c)들이 소정형태로 절곡형성되어 있다.FIG. 1 is a vertical cross-sectional view showing a configuration of a general semiconductor package. As shown in the drawing, a semiconductor chip 2 is fixedly attached to an upper surface of a paddle 1a of a lead frame 1 with an adhesive 3. A plurality of inner leads 1b are provided around the chip 2 so that the chip pads 2a and the inner leads 1b formed on the upper surface of the chip 2 are metal wires 4, respectively. Is connected to the, the molding portion 5 for protecting the chip 2 to form a portion of the chip 2, the metal wire 4, the inner lead (1b) is formed, the molding part 5 The outer lead 1c is bent in a predetermined shape so as to extend to the inner leads 1b.
상기와 같이 구성되어 있는 일반적인 반도체 패키지는 패들(1a)의 상면에 접착제(3)로 반도체 칩(2)을 고정부착하는 다이본딩을 실시하고, 상기 반도체 칩(2)의 상면에 형성되어 있는 칩패드(2a)들과 인너리드(1b)들을 금속와이어(4)로 연결하는 와이어본딩를 실시하며, 상기 칩(2), 금속와이어(4), 인너리드(1b)들의 일정부분을 감싸도록 칩(2)을 보호하기 위한 몰딩부(5)를 형성하는 몰딩공정을 실시하고, 트리밍/포밍공정을 실시하여 패키지(6)를 완성한다.The general semiconductor package structured as described above is die-bonded to fix the semiconductor chip 2 with the adhesive 3 on the upper surface of the paddle 1a, and formed on the upper surface of the semiconductor chip 2. The wire bonding is performed to connect the pads 2a and the inner leads 1b with the metal wires 4, and the chip (2), the metal wires 4, and the chip to cover a portion of the inner leads 1b. 2) A molding process for forming the molding part 5 for protecting is performed, and a trimming / forming process is performed to complete the package 6.
상기와 같이 완성된 패키지(6)는 도 2에 도시된 바와 같이, 피시비(7)의 상면에 아웃리드(1c)들의 하단부를 납땜고정하는 방법으로 실장하여 사용하게 된다.As shown in FIG. 2, the completed package 6 is mounted and used by soldering and fixing lower ends of the outleads 1c on the upper surface of the PCB 7.
그러나, 상기와 같은 일반적인 반도체 패키지(6)는 수평방향으로 몰딩부(5)를 형성하고, 그 몰딩부(5)의 양측으로 아웃리드(1c)들을 돌출형성시킴으로써, 경박단소화에 한계가 있는 문제점이 있었다. 또한, 상기와 같은 패키지(6)를 실장하는 경우에 수평방향으로 피시비(7) 상면에 실장되기 때문에 실장면적을 넓게 차지하는 문제점이 있었다.However, the general semiconductor package 6 as described above forms a molding part 5 in the horizontal direction, and protrudes outleads 1c on both sides of the molding part 5, thereby limiting light and short reduction. There was a problem. In addition, when mounting the package 6 as described above is mounted on the upper surface of the PCB 7 in the horizontal direction, there is a problem that occupies a large mounting area.
상기와 같은 문제점을 감안하여 안출한 본 고안의 목적은 패키지를 경박단소화시킬뿐만 아니라, 실장면적을 감소시키도록 하는데 적합한 버티컬 칩 사이즈 패키지를 제공함에 있다.The object of the present invention devised in view of the above problems is to provide a vertical chip size package suitable for reducing the package size as well as reducing the size of the package.
도 1은 일반적인 반도체 패키지의 구성을 보인 종단면도.1 is a longitudinal sectional view showing a configuration of a general semiconductor package.
도 2는 일반적인 반도체 패키지가 실장된 상태를 보인 정면도.2 is a front view showing a state in which a general semiconductor package is mounted.
도 3은 본 고안 버티컬 칩 사이즈 패키지의 구성을 보인 정면도.Figure 3 is a front view showing the configuration of the vertical chip size package of the present invention.
도 4는 본 고안 버티컬 칩 사이즈 패키지의 구성을 보인 측면도.Figure 4 is a side view showing the configuration of the vertical chip size package of the present invention.
도 5는 본 고안 버티컬 칩 사이즈 패키지의 구성을 보인 평면도.Figure 5 is a plan view showing the configuration of the vertical chip size package of the present invention.
도 6은 도 5의 A-A'를 절취하여 보인 단면도.6 is a cross-sectional view taken along the line AA ′ of FIG. 5;
도 7은 본 고안 버티컬 칩 사이즈 패키지가 실장된 상태를 보인 정면도.7 is a front view showing a state in which the vertical chip size package of the present invention is mounted.
* * 도면의 주요 부분에 대한 부호의 설명 * ** * Explanation of symbols for the main parts of the drawing * *
11 : 칩 12 : 칩패드11 chip 12 chip pad
13 : 리드 14 : 몰딩부13 lead 14 molding part
15 : 패턴 16 : 받침대15 pattern 16: pedestal
상기와 같은 본 고안의 목적을 달성하기 위하여 수직으로 배치되는 반도체 칩과, 그 칩의 일측면 하단부에 형성되는 다수개의 칩패드와, 그 칩패드들에 각각 상단부가 연결설치되어 칩의 신호를 전달하는 다수개의 리드와, 그 리드들의 하면을 외부로 노출시킨 상태에서 리드들이 보호될수 있게 리드들을 감싸도록 형성되는 몰딩부와, 그 칩과 몰딩부를 지지될 수 있게 칩과 몰딩부의 하면에 접착되는 받침대와, 그 받침대의 내부에 형성되며 상기 리드의 하단부에 접촉되어 리드를 통해 전달되는 신호를 외부로 전달할 수 있도록 하는 다수개의 패턴들을 구비하여서 구성되는 것을 특징으로 하는 버티컬 칩 사이즈 패키지가 제공된다.In order to achieve the object of the present invention as described above, a vertically arranged semiconductor chip, a plurality of chip pads formed on one side of the lower side of the chip, and the upper end connected to each of the chip pads are installed to transfer the signal of the chip. A plurality of leads, a molding portion formed to surround the leads so that the leads are protected while the lower surfaces of the leads are exposed to the outside, and a pedestal bonded to the bottom surface of the chip and the molding portion so as to support the chip and the molding portion. And a plurality of patterns formed in the pedestal and having a plurality of patterns contacting the lower end of the lid to transmit a signal transmitted through the lid to the outside.
이하, 상기와 같이 구성되는 본 고안 버티컬 칩 사이즈 패키지를 첨부됨 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, a vertical chip size package of the present invention configured as described above will be described in more detail with reference to an embodiment of the accompanying drawings.
도 3은 본 고안 버티컬 칩 사이즈 패키지의 구성을 보인 정면도이고, 도 4는 본 고안 버티컬 칩 사이즈 패키지의 구성을 보인 측면도이며, 도 5는 본 고안 버티컬 칩 사이즈 패키지의 구성을 보인 평면도이고, 도 6은 도 5의 A-A'를 절취하여보인 단면도이다.Figure 3 is a front view showing the configuration of the vertical chip size package of the present invention, Figure 4 is a side view showing the configuration of the vertical chip size package of the present invention, Figure 5 is a plan view showing the configuration of the vertical chip size package of the present invention, Figure 6 Is a cross-sectional view taken along the line AA ′ of FIG. 5.
도시된 바와 같이, 본 고안 버티컬 칩 사이즈 패키지는 수직으로 배치되는 반도체 칩(11)의 일측면 하단부에 2열로 다수개의 칩패드(12)가 형성되어 있고, 그 칩 패드(12)들에는 각각 리드(13)의 상단부가 연결되어 있으며, 상기 칩(11)의 하단부 일측면에는 상기 리드(13)들을 감사도록 에폭시로 몰딩부(14)가 형성되어 있고, 상기 몰딩부(14)의 외측에는 상기 리드(13)들에 각각 연결되는 패턴(15)이 내설되어 있는 받침대(16)가 설치되어 있다.As shown, in the vertical chip size package of the present invention, a plurality of chip pads 12 are formed in two rows at a lower side of one side of a semiconductor chip 11 arranged vertically, and each of the chip pads 12 has a lead. An upper end portion of the 13 is connected, and a molding part 14 is formed of epoxy on one side of the lower end of the chip 11 to audit the leads 13, and the outer side of the molding part 14 The pedestal 16 is provided with a pattern 15 connected to the leads 13, respectively.
상기와 같이 구성되어 있는 본 고안 버티컬 칩 사이즈 패키지는 칩(11)의 일측면에 하단부에 형성된 다수개의 칩패드(12)들에 각각 리드(13)를 연결부착하고, 그 리드(13)들의 하단부를 노출시킴과 아울러 리드(13)들을 감싸도록 칩(11)의 일측면 하단부에 몰딩부(14)를 형성하며, 상기 리드(13)들의 외부 노출면에 패턴(15)이 접촉되도록 칩(11)의 하측에 받침대(16)를 접착고정하여 패키지(17)를 완성한다.The vertical chip size package of the present invention configured as described above attaches and attaches the leads 13 to the plurality of chip pads 12 formed on one side of the chip 11 at the lower end, and the lower ends of the leads 13. And a molding part 14 formed at the lower end of one side of the chip 11 to surround the leads 13, and the chip 11 to be in contact with the external exposed surface of the leads 13. Attach the pedestal 16 to the lower side of the) to complete the package 17.
상기와 같이 완성된 패키지(17)는 도 7과 같이 피시비(18)의 상면에 수직으로 실장된다.The completed package 17 as described above is mounted vertically on the upper surface of the PCB 18 as shown in FIG.
이상에서 상세히 설명한 바와 같이, 본 고안 버티컬 칩 사이즈 패키지는 칩의 일측면 하단부에 다수개의 칩패드를 형성하고, 그 칩패드들에 리드를 부착하며, 그 리드들을 감싸도록 부분적으로 몰딩부를 형성하고, 상기 리드들에 접속되도록 패턴이 내설된 받침대를 몰딩부의 하측에 설치하며, 외부단자가 되는 리드들을 일측면에 설치함으로써 패키지를 경박단소화시키는 효과가 있고, 피시비 기판에 실장시 수직방향으로 실장되어 종래 일반적인 패키지 보다 실장면적을 감소되는 효과가 있다.As described in detail above, the vertical chip size package of the present invention forms a plurality of chip pads on one side lower surface of the chip, attaches leads to the chip pads, and partially forms a molding part to surround the leads, A pedestal incorporating a pattern to be connected to the leads is provided below the molding part, and the leads are formed on one side of the external terminals, thereby reducing the thickness of the package. The package is mounted in the vertical direction when mounted on the PCB. The mounting area is reduced compared to the general package.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970045411U KR200309900Y1 (en) | 1997-12-31 | 1997-12-31 | Vertical Chip Size Package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970045411U KR200309900Y1 (en) | 1997-12-31 | 1997-12-31 | Vertical Chip Size Package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990032646U KR19990032646U (en) | 1999-07-26 |
| KR200309900Y1 true KR200309900Y1 (en) | 2003-06-19 |
Family
ID=49404456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970045411U KR200309900Y1 (en) | 1997-12-31 | 1997-12-31 | Vertical Chip Size Package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200309900Y1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112490237A (en) * | 2020-12-16 | 2021-03-12 | 咸阳振峰电子有限公司 | Multi-chip crystal group packaging structure and application thereof |
-
1997
- 1997-12-31 KR KR2019970045411U patent/KR200309900Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990032646U (en) | 1999-07-26 |
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