KR200303035Y1 - 2-phase register - Google Patents

Abstract

The present invention relates to a two-phase register, and in the prior art, by using a plurality of transfer gates and inverters, the design area becomes wider, the power consumption is severe, and a plurality of inputs when the clock enable signal is low potential Due to the low potential of the clock, the output signal of the transfer gate floats, causing a circuit malfunction. Therefore, the present invention has been devised to solve the conventional problems as described above, by using the NMOS transistor and the PMOS transistor to maintain the output signal of the inverter, to prevent the output signal is floated and the circuit malfunctions, In addition, the use of a small number of transistors has the effect of minimizing design area and power consumption.

Description

2-phase register

The present invention relates to a two-phase register, and more particularly, to a two-phase register with optimized design area by minimizing transistors used in designing two-phase registers that are used as microprocessors or digital signal processors become more efficient. will be.

1 is a circuit diagram of a conventional two-phase register, and as shown therein, a first inverter I1 for inverting and outputting a clock enable signal Id; A second inverter I2 inverting and outputting the first clock Phi1; A third inverter I3 for inverting and outputting the second clock Phi2; A first transfer gate S1 for receiving the clock enable signal Id through a non-inverting terminal and receiving an output signal of the first inverter I1 as an inverting terminal and outputting an input signal D; The second transfer gate S2 that receives the first clock Phi1 through the non-inverting terminal and the output signal of the second inverter I2 through the inverting terminal and outputs the output signal of the first transfer gate S1. )Wow; A fourth inverter I4 which receives the output signal of the second transfer gate S2 and inverts it and outputs it; A third transfer gate S3 that receives the second clock Phi2 as a non-inverting terminal, receives an output signal of the third inverter I3 as an inverting terminal, and outputs an output signal of the fourth inverter I4. Wow; A fifth inverter I5 for inverting the output signal of the third transfer gate S3 and outputting the inverted signal to the final output terminal Q; The output signal of the fifth inverter I5 is input to the second transfer gate S2 by receiving the output signal of the first inverter I1 through a non-inverting terminal and the clock enable signal Id through an inverting terminal. The fourth transmission gate (S4) for outputting to the input terminal of the, will be described in detail with reference to the waveform diagram of each part of FIG.

First, the first and second clocks Phi1 and Phi2 have the same frequency but are in opposite phases, and do not have overlapping portions, and also include the first, second and third inverters I1 and I2. I3 receives the clock enable signal Id and the first and second clocks Phi1 and Phi2, respectively, and inverts them to output them.

Here, when the first clock (Phi1), the clock enable signal (Id) and the input signal (D) is a high potential and the second clock (Phi2) is a low potential (section (a) of Fig. 2), The first transmission gate S1 receives the clock enable signal Id having a high potential as an inverting terminal and receives the low potential output signal of the first inverter I1 as an inverting terminal, but operates the high potential as an inverting terminal. Since the fourth transfer gate S4 that receives the clock enable signal Id and receives the low potential output signal of the first inverter I1 as the non-inverting terminal does not operate, the first transfer gate S1 does not operate. Outputs the high potential input signal D of the input terminal to the input terminal of the second transfer gate S2.

In this case, the second transfer gate S2 receiving the high potential first clock Phi1 as the non-inverting terminal and the low potential output signal of the first inverter I1 as the inverting terminal is input. The high potential output signal of the first transmission gate S1 is output, the high potential output signal of the first transmission gate S1 is input from the fourth inverter I4, and the low potential is output by inverting it.

In addition, the third transfer gate S3 that receives the low potential second clock Phi2 through the non-inverting terminal and the output signal of the third inverter I3 of high potential through the inverting terminal does not operate.

Subsequently, when the first clock Phi1 becomes low potential (section (b) of FIG. 2), the low potential first clock Phi1 is input to a non-inverting terminal and the second high potential is inverted to the inverting terminal. The second transfer gate S2 that receives the output signal of the inverter I2 does not operate.

When the second clock Phi2 becomes high potential (section (C) of FIG. 2), the second clock Phi2 having the high potential is input to the non-inverting terminal and the third inverter I3 is the inverting terminal. The third transfer gate S3, which has received the low potential output signal of the second output signal, outputs the low potential output signal of the fourth inverter I1 to the output terminal.

Accordingly, the fifth inverter I5 receives the low potential output signal of the third transfer gate S3 and inverts it to output the high potential to the final output terminal Q.

When the second clock Phi2 and the input signal D become low potential (section (D) of FIG. 2), since the third transfer gate S3 does not operate, the final output terminal Q is Maintain high potential.

Thereafter, when the first clock Phi1 becomes high potential (section (e) of FIG. 2), the second transfer gate S2 outputs the low potential input signal D, and transmits the signal. The input fourth inverter I4 outputs a high potential, but when the third transfer gate S3 is not operated and the first clock Phi1 becomes low, the second and third transfers are performed. Since the gates S2 and S3 are not operated, the final output terminal Q maintains the high potential output signal of the fifth inverter I5.

When the second clock Phi2 becomes high potential (section (bar) of FIG. 2), the second transfer gate S2 does not operate, and the third transfer gate S3 is the fourth inverter. The high potential output signal of I4 is output.

Accordingly, since the fifth inverter I5 receives the high potential output signal of the third transfer gate S3 and inverts it to output the low potential, the low potential is output to the final output terminal Q.

After that, when the clock enable signal Id becomes low potential (section 4 in FIG. 2), the first transfer gate S1 does not operate and the fourth transfer gate S4 operates. The output signal of the low potential fifth inverter I5 is transferred to the input terminal of the second transfer gate S2 through the fourth transfer gate S4.

Here, when the first clock Phi1 is at high potential, the second transfer gate S2 operates to output a low potential output signal of the fourth transfer gate S4, and the fourth inverter I4. Receives the low potential output signal of the second transfer gate S2 and inverts it to output a high potential.

In addition, when the third transfer gate S3 operates to output a high potential when the second clock Phi2 is at a low potential, the fifth inverter I5 may generate a high potential of the third transfer gate S3. The output signal is received and inverted to output the low potential to the final output terminal Q and the fourth transfer gate S4.

Therefore, when the clock enable signal Id has a low potential, the operation is repeatedly performed so that the low potential is output to the final output terminal Q regardless of the first and second clocks Phi1 and Phi2. .

By using a plurality of transfer gates and inverters in the related art as described above, the design area is widened, the power consumption is high, and when the clock enable signal is low potential, the plurality of input clocks becomes low potential. There is a problem that the circuit malfunctions because the output signal of the transmission gate is floating (floating).

Accordingly, an object of the present invention is to provide a two-phase resistor that minimizes the design area and power consumption by reducing the number of transistors used to solve the conventional problems as described above.

1 is a circuit diagram of a conventional two-phase register.

2 is a waveform diagram of each part in FIG.

3 is a circuit diagram of a two-phase register of the present invention.

4 is a waveform diagram of each part in FIG. 4.

*** Description of the symbols for the main parts of the drawings ***

10, 20: latch portion NM1 to NM3: NMOS transistor

PM1-PM3: PMOS transistors I1-I2: Inverter

In order to achieve the above object, a constitution of a two-phase register according to the present invention includes: a first NMOS transistor configured to electrically control an input signal by receiving a clock enable signal from a gate; A first PMOS transistor configured to conduct a conductive control of an output signal of the first NMOS transistor by receiving a clock from a gate; A first latch unit for inverting and outputting the output signal of the first PMOS transistor and maintaining the output signal at a high potential if the inverted output signal is at a high potential; A second NMOS transistor receiving the clock from a gate and conducting control of an output signal of the first latch unit; A second latch unit for inverting and outputting an output signal of the second NMOS transistor and maintaining the output signal at a low potential when the inverted output signal is at a low potential; And a second PMOS transistor configured to conduct conduction control by applying the clock enable signal to a gate and outputting the output signal of the second latch portion of the drain to the source of the first PMOS transistor.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

3 is a circuit diagram of a two-phase register of the present invention, and a first NMOS transistor NM1 for conducting and controlling the input signal D by applying a clock enable signal Id to a gate as shown in FIG. A first PMOS transistor PM1 for applying a clock CLK to a gate to conduct conduction control of the output signal of the first NMOS transistor NM1; A first latch unit 10 for inverting and outputting the output signal of the first PMOS transistor PM1 and maintaining the output signal at a high potential if the inverted output signal is high potential; A second NMOS transistor NM2 which receives the clock CLK from a gate and conducts and controls the output signal of the first latch unit 10; A second latch unit 20 for inverting and outputting the output signal of the second NMOS transistor NM2 and maintaining the output signal at a low potential when the inverted output signal is at a low potential; A second PMOS transistor configured to conduct conductive control so that the clock enable signal Id is applied to a gate to output an output signal of the second latch unit 20 of a drain to a source of the first PMOS transistor PM1; And a first inverter (I1) for inverting the output signal of the first PMOS transistor (PM1) and outputting the inverted output signal to the second NMOS transistor (NM2); The third NMOS transistor NM3 conducts and controls the output signal of the first inverter I1 to the gate to output the ground voltage VSS of the source to the input terminal of the first inverter I1.

The second latch unit 20 includes a second inverter I2 for inverting the output signal of the second NMOS transistor NM2 and outputting the inverted signal to the final output terminal Q; A third PMOS transistor (PM3) which conducts and controls the output signal of the second inverter (I2) to the gate to output the power supply voltage (VDD) of the source to the input terminal of the second inverter (I2), When described in detail with reference to the output waveform diagram of Figure 4 attached to the operation of an embodiment according to the present invention configured as described above.

First, when the clock CLK, the clock enable signal Id, and the input signal D have a high potential (section (a) of FIG. 4), the first NMOS transistor NM1 and the second PMOS transistor PM2. Since the high potential clock enable signal Id is applied to the gates of the Ns, the first NMOS transistor NM1 is turned on, but the second PMOS transistor PM2 is turned off.

Accordingly, the first NMOS transistor NM1 outputs the high potential input signal D of the drain as a source of the first PMOS transistor PM1, and at this time, the first PMOS transistor PM1 is high in the gate. The clock CLK is applied to turn it off.

Thereafter, when the clock CLK becomes low potential (section (b) of FIG. 4), the first PMOS transistor PM1 receiving the low potential clock CLK through a gate is turned on to generate the high potential zero. The high potential input signal D applied through the first NMOS transistor NM1 is applied to the first latch unit 10, but the second NMOS transistor NM2 having the low potential clock applied to the gate is turned off. As a result, the output of the first latch unit 10 is not transmitted to the second latch unit 20.

Here, the first inverter I1 in the first latch unit 10 receives a high potential signal through the first PMOS transistor PM1 and inverts the low potential to output a low potential. The low potential output signal is applied to the gate of the third NMOS transistor NM3 to turn off the third NMOS transistor NM3.

When the clock CLK becomes high potential and the input signal D becomes low potential (section (C) of FIG. 4), the second NMOS receives the high potential clock CLK to a gate. The transistor NM2 outputs the low potential output signal of the first latch unit 10 of the drain to the input terminal of the second latch unit 20, but receives the high potential clock CLK to the gate. The MOS transistor PM is turned off. At this time, the first NMOS transistor NM1 receiving the high potential clock enable signal Id at the gate outputs the low potential input signal D.

Accordingly, the second latch unit 20 receives an output signal of the low potential first latch unit 10 applied through the second NMOS transistor NM2 and inverts it in the second inverter I2. The high potential is output to the final output stage (Q).

After that, when the clock CLK becomes low potential (section (D) of FIG. 4), the second NMOS transistor NM2 receiving the low potential clock CLK to the gate is turned off, but the gate is turned off. The low potential clock CLK applied to turns on the first PMOS transistor PM1.

Accordingly, the first inverter I1 inverts the low potential input signal D applied through the first PMOS transistor PM1 to output a high potential, and outputs a high potential of the first inverter I1. Since the third NMOS transistor NM3 applied to the gate is turned on and outputs a ground voltage VSS to an input terminal of the first inverter I1, the third NMOS transistor NM3 may be connected to the first NMOS transistor NM3. The input signal D applied to the input terminal of the inverter I1 is kept at a low potential.

Thus, the first latch unit 10 maintains the high potential output signal.

Thereafter, when the clock enable signal Id becomes low potential (section (e) of FIG. 4), the first NMOS transistors receiving the low potential clock enable signal Id are respectively applied to gates. NM1 is turned off and the second PMOS transistor PM2 is turned on to feed back an output signal.

At this time, when the clock CLK becomes high potential, the second NMOS transistor NM2 receiving the high potential as a gate receives the high potential signal of the first latch unit 10 from the input terminal of the second latch unit 20. Since the second inverter I2 in the second latch unit 20 receives an output signal of the high potential first latch unit 10 and inverts the output signal, the second inverter I2 outputs a low potential.

Here, the third PMOS transistor PM3 receiving the low potential output signal of the second inverter I2 to the gate outputs the source voltage VCC to the input terminal of the second inverter I2. The two latch section 20 and the final output stage Q continue to hold the low potential output signal.

Thereafter, when the clock CLK becomes low potential, the first PMOS transistor PM1 applying the low potential to the gate is turned on, so that the first latch unit 10 may turn the second PMOS transistor PM2. The third NMOS transistor NM3, which inverts the low potential output signal of the second latch unit 20 input through the high potential and outputs the high potential to the gate, receives the ground voltage VSS of the source. Since the output to the input terminal of the first inverter (I1), the first latch unit 10 continues to maintain the high potential output signal.

When the clock CLK becomes the high potential, the third NMOS transistor NM3 having the high potential applied to the gate is turned on to receive the high potential output signal of the first latch unit 10. The second latch unit 20 inverts this to output a low potential, and the third PMOS transistor PM3 applied with the high potential to the gate supplies the source voltage VCC of the source to the second inverter I2. Since the output to the input terminal, the second latch unit 20 and the final output terminal (Q) continue to maintain the low potential output signal.

As described in detail above, the present invention uses an NMOS transistor and a PMOS transistor to maintain the output signal of the inverter, thereby preventing the output signal from floating and malfunctioning the circuit, and using a small number of transistors. It has the effect of minimizing the design area and power consumption.

Claims (3)

A first NMOS transistor configured to receive a clock enable signal from the gate and control conduction of the input signal; A first PMOS transistor configured to conduct a conductive control of an output signal of the first NMOS transistor by receiving a clock from a gate; A first latch unit for inverting and outputting the output signal of the first PMOS transistor and maintaining the output signal at a high potential if the inverted output signal is at a high potential; A second NMOS transistor receiving the clock from a gate and conducting control of an output signal of the first latch unit; A second latch unit for inverting and outputting an output signal of the second NMOS transistor and maintaining the output signal at a low potential when the inverted output signal is at a low potential; And a second PMOS transistor configured to conduct conduction control by applying the clock enable signal to a gate and outputting the output signal of the second latch portion of the drain to the source of the first PMOS transistor. . The display device of claim 1, wherein the first latch unit comprises: a first inverter for inverting and outputting an input signal; And a first NMOS transistor configured to apply an output signal of the first inverter to a gate and output a ground voltage of the source to an input terminal of the first inverter. The display device of claim 1, wherein the second latch unit comprises: a first inverter for inverting and outputting an input signal; And a first PMOS transistor configured to receive an output signal of the first inverter to a gate and output a power supply voltage of the source to an input terminal of the first inverter.