JPH05128862A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide the synchronous static type RAM of low power consumption by eliminating the power leak generated by the delay of a precharging signal and a write signal inputted from an external part, in the synchronous static type RAM. CONSTITUTION:To the data of a data latch circuit 19, a precharging signal 4 is inputted, and to the clock of the data latch circuit 19, a write signal 14 is inputted and the output of the data latch circuit 19 to synchronize the precharging signal 4 to the write signal 14 is inputted to a precharging circuit 15. The stable precharging signal 4 controlled by the write signal 14 can be communicated to the precharging circuit 15 of the synchronous static type RAM, the leak between powers due to the delay of the precharging signal 4 and the write signal 14 is eliminated and the low power consumption is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a precharge circuit for a synchronous static RAM (random access memory).

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, a semiconductor device of this type has a storage circuit 1 of a synchronous static RAM.
And an input circuit 16 and a precharge circuit 15 for charging the signal lines D17 and D18 connecting the input circuit 16 to one level (high potential).

Here, the precharge circuit 15 has P-channel type MOS transistors 2 and 3.

The input circuit 16 has N-channel type MOS transistors 7 and 8, NOR circuits 10 and 11, and an inverter circuit 13.

The operation of this circuit will be described with reference to the timing chart of FIG. The precharge circuit 15 that charges the signal line D17 and the signal line D18 to 1 level (high potential) uses a P-type MOS when the precharge signal 4 is 0 level (low potential).
The transistors (FETs) 2 and 3 are turned on (conductive state), the signal lines D17 and D18 and the power supply VDD (high potential) 5,
6 is connected and the signal lines D17 and D18 are charged to 1 level.

At this time, since the write signal 14 is at 1 level, the outputs of the NOR circuits 10 and 11 are at 0 level and N
The type MOSFETs 7 and 8 are OFF (non-conductive state).

Next, when the write signal 14 is at 0 level, the precharge signal 4 is at 1 level, so P
The type MOSFETs 2 and 3 are off. Data signal 1
Since 2 is 0 level, the inverted 1 level is input to the input of the NOR circuit 10 by the inverter circuit 13, and the output of the NOR circuit 10 is 0 level and the N-type MO
The SFET8 is off.

The NOR circuit 11 receives an input of a write signal 14
Depending on the 0 level of the data signal and the 0 level of the data signal 12
The output of the circuit 11 becomes 1 level and the N-type MOSFET
7 is turned on, and the signal line D17 is connected to the power supply VSS (low potential) 9
Is connected to the 0 level state, and then the write signal 1
4 changes from 0 level to 1 level, N-type MOSFET
At the same time that 7 and 8 are turned off, the precharge signal 4 becomes 1
Since the level changes from 0 to 0, P-type MOSFE
T2 and T3 are turned on, and the signal lines D17 and D18 are charged to 1 level again.

[0009]

In such a conventional semiconductor device, in order to shorten the operation time of the synchronous static RAM, the write signal 14 changes from 0 level to 1 level and the precharge signal 4 becomes 1. In many cases, the change timing from the level to the 0 level is changed at the same time.

When the write signal 14 is delayed by a parasitic element or the like, the write signal 14 and the precharge signal 4 are set to 1
It becomes a level state, P-type MOSFETs 2 and 3 and N-type M
The OSFET7 is turned on, and the power line VDD5 to the signal line D1
A large current flows to the power supply VSS9 through the line 7, and the influence is great for the synchronous static RAM characterized by low power consumption.

An object of the present invention is to solve the above problems and provide a semiconductor device in which a large current does not flow.

[0012]

SUMMARY OF THE INVENTION According to the structure of the present invention, an input circuit having a write signal for controlling data input to a storage circuit, and a signal line connecting the input / output of the storage circuit and the input circuit. In a semiconductor device having a precharge circuit for charging, a control circuit for controlling the operation of the precharge circuit according to a write signal of the input circuit is provided.

[0013]

1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

1 and 2, in this embodiment, a precharge signal 4 inputted from the outside is connected to a data input section IN of a data latch circuit 19. Write signal 14
Is a clock unit CK and NO of the data latch circuit 19.
It is connected to one end of the R circuits 10 and 11. The normal output OUT of the data latch circuit 19 is connected to the gates of the P-type MOSFETs 2 and 3.

The other precharge circuit 15, input circuit 16, storage circuit 1 and the like are the same as those in FIG.

In FIG. 2, when the write signal 14 is at the 1 level, the normal output OUT of the data latch circuit 19 is the 1 level of the precharge signal 4 as it is. When the write signal 14 changes from 1 level to 0 level, the data latch circuit 19 is held, and the normal output OUT of the data latch circuit 19 is held at 1 level.

Next, after the write signal 14 rises and changes from 0 level to 1 level, the data latch circuit 19 is released from the hold state, and the 0 level of the precharge signal 4 changes the normal output OUT of the data latch circuit 19. Is output from.

That is, since the change of the precharge signal 4 from the 1 level to the 0 level is synchronized with the change of the write signal 14 from the 0 level to the 1 level, even when the write signal 14 is delayed by a parasitic element or the like. , Write signal 14 is 0
Normal output OUT of the data latch circuit 19 in the level state
Does not change from 1 level to 0 level, and P-type MOSF
The timing at which the ET2 and the N-type MOSFET 7 are turned on does not occur.

As described above, in this embodiment, the input circuit having the write signal for controlling the data input to the memory circuit of the synchronous static RAM and the input / output terminal of the memory circuit of the synchronous static RAM are provided. A precharge circuit for charging a signal line connecting to the input circuit to one level (high potential), and a control circuit for controlling the operation of the precharge circuit by a write signal of the input circuit. To do.

That is, in the structure of the semiconductor device of this embodiment, the precharge signal 4 input from the outside to the synchronous static RAM is used as the data input of the data latch circuit 19, and the write signal 14 is used as the clock of the data latch circuit 19. Input it. The precharge signal 4 controlled by the clock of the write signal 14 is input from the output of the data latch circuit 19 to the precharge circuit 15 of the synchronous static RAM.

[0021]

As described above, according to the present invention, by using the control circuit, the stable precharge signal controlled by the write signal can be transmitted to the precharge circuit of the memory circuit, and the precharge signal can be transmitted. And, there is an effect that the power leakage due to the delay of the write signal is eliminated and the power consumption is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor device of an embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation state of the embodiment of FIG.

FIG. 3 is a circuit diagram showing a conventional semiconductor memory circuit.

FIG. 4 is a timing diagram showing an operation state of FIG.

[Explanation of symbols]

 1 memory circuit 2,3 P-type MOSFET 4 precharge signal 5,6 power supply VDD 7,8 N-type MOSFET 9 power supply VSS 10, 11 NOR circuit 12 data signal 13 inverter circuit 14 write signal 15 precharge circuit 16 input circuit D17, 17, D18, 17 Signal line 19 Data latch circuit

Claims (2)

[Claims] 1. An input circuit having a write signal for controlling data input to a memory circuit, and a precharge circuit for charging a signal line connecting the input / output of the memory circuit and the input circuit. The semiconductor device is provided with a control circuit for controlling the operation of the precharge circuit according to a write signal of the input circuit. 2. The semiconductor device according to claim 1, wherein the control circuit is a latch circuit whose input is a precharge signal, whose output is connected to the precharge circuit, and whose clock input is a write signal.