KR20030096887A - Method of semiconductor device having pads - Google Patents
Method of semiconductor device having pads Download PDFInfo
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- KR20030096887A KR20030096887A KR1020020033982A KR20020033982A KR20030096887A KR 20030096887 A KR20030096887 A KR 20030096887A KR 1020020033982 A KR1020020033982 A KR 1020020033982A KR 20020033982 A KR20020033982 A KR 20020033982A KR 20030096887 A KR20030096887 A KR 20030096887A
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/03009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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Abstract
Description
본 발명은 반도체소자의 형성방법에 관한 것으로, 특히 패드를 갖는 반도체소자의 형성방법에 관한 것이다.The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device having a pad.
반도체 소자 중 패드(pad)는 반도체 소자의 내부와 외부간의 전기적 신호를 주고 받는 역활을 한다. 즉, 반도체 소자는 패드를 통하여 동작을 위한 동작 전압 및 전기적 신호를 받아들이고, 패드를 통하여 데이타들을 출력시킨다. 패드는 반도체 칩을 형성하는 어셈블리공정(Assembly process)의 와이어 본딩(wire bonding) 공정시, 와이어에 연결되는 부분이다.Among the semiconductor devices, a pad plays a role of transmitting and receiving electrical signals between the inside and the outside of the semiconductor device. That is, the semiconductor device receives an operating voltage and an electrical signal for operation through a pad and outputs data through the pad. The pad is a part connected to the wire during a wire bonding process of an assembly process of forming a semiconductor chip.
한편, 일반적으로, 반도체 소자는 외부의 열악한 환경으로 부터 반도체 소자를 보호하기 위한 이중의 보호막들을 갖는다. 패시베이션막(passivation layer) 및 폴리이미드막(polyimide layer)이 그것이다. 패시베이션막은 습기, 압력등의 외부 환경으로 부터 반도체소자를 보호하기 위한 보호막이며, 폴리이미드막은 고온, 마찰, 방사선 및 화학약품으로 부터 반도체 소자를 보호하기 위한 보호막이다. 상술한 보호막들은 모두 패드를 노출시키는 패터닝 공정을 진행한다.On the other hand, in general, a semiconductor device has double protective films for protecting the semiconductor device from an external harsh environment. Passivation layers and polyimide layers are the same. The passivation film is a protective film for protecting the semiconductor device from external environment such as moisture and pressure, and the polyimide film is a protective film for protecting the semiconductor device from high temperature, friction, radiation and chemicals. All of the above-described passivation layers undergo a patterning process for exposing the pads.
도 1 및 도 2는 종래의 패드를 갖는 반도체 소자의 형성방법을 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a method of forming a semiconductor device having a conventional pad.
도 1 및 도 2를 참조하면, 반도체기판(1) 상에 층간절연막(2)을 형성하고, 상기 층간절연막(2) 상에 패드(3, pad)를 형성한다. 상기 패드(3)를 갖는 반도체기판(1) 전면에 패시베이션막(4)을 형성한다. 상기 패시베이션막(4)을 패터닝하여 상기 패드(3)의 소정영역을 노출시키는 패시베이션 콘텍홀(5)을 형성한다. 상기 패시베이션 콘텍홀(5) 내부를 포함하는 반도체기판(1) 전면에 폴리이미드막(6)을 형성하고, 상기 폴리이미드막(6)을 패터닝하여 상기 패시베이션 콘텍홀(5)에 노출되었던 패드(3)를 노출시킨다.1 and 2, an interlayer insulating film 2 is formed on a semiconductor substrate 1, and pads 3 are formed on the interlayer insulating film 2. The passivation film 4 is formed on the entire surface of the semiconductor substrate 1 having the pads 3. The passivation film 4 is patterned to form a passivation contact hole 5 exposing a predetermined region of the pad 3. The polyimide layer 6 is formed on the entire surface of the semiconductor substrate 1 including the inside of the passivation contact hole 5, and the polyimide layer 6 is patterned to expose the pads having been exposed to the passivation contact hole 5. 3) is exposed.
상기 폴리이미드막(6)을 패터닝하는 과정을 간략히 설명하면, 상기 폴리이미드막(6)에 선택적으로 노광공정을 진행한후, 현상공정을 진행한다. 상기 현상공정은 상기 노광된 폴리이미드막(6)과 현상액(develop solution)을 반응시키어 상기 노광된 폴리이미드막(6)을 제거한다. 그 결과, 상기 패드(3)가 노출된다. 이때, 상기 현상액은 금속막으로 형성된 상기 패드(3)를 식각할 수 있다. 이로 인하여, 상기 패드(3)의 두께가 감소하게 된다. 그 결과, 반도체소자를 반도체 칩으로 형성하기 위한 어셈블리공정에서 와이어본딩(wire bonding) 공정시 불량이 발생할 수 있다. 상기 현상액에 의하여 패드가 식각되는 현상은 상기 폴리이미드막(3)의 패터닝시 오정렬이 발생하여 상기 패터닝된 폴리이미드막(3)을 제거하고, 다시 폴리이드막(3)을 형성하는 재작업(rework)시 더욱 심화될 수 있다.The process of patterning the polyimide film 6 is briefly described. After the exposure process is selectively performed on the polyimide film 6, the developing process is performed. The developing process reacts the exposed polyimide film 6 with a developer solution to remove the exposed polyimide film 6. As a result, the pad 3 is exposed. In this case, the developer may etch the pad 3 formed of a metal film. As a result, the thickness of the pad 3 is reduced. As a result, a defect may occur in a wire bonding process in an assembly process for forming a semiconductor device into a semiconductor chip. The phenomenon in which the pads are etched by the developer may cause a misalignment during patterning of the polyimide film 3 to remove the patterned polyimide film 3, and then to form the polyid film 3 again. Can be further deepened during rework.
본 발명이 이루고자 하는 기술적 과제는 폴리이미드막의 패터닝시 사용되는 현상액이 패드를 식각하는 현상을 최소화할 수 있는 반도체소자의 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of forming a semiconductor device capable of minimizing a phenomenon in which a developer used to pattern a polyimide film etches a pad.
도 1 및 도 2는 종래의 패드를 갖는 반도체소자의 형성방법을 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a method of forming a semiconductor device having a conventional pad.
도 3 내지 도 7은 본 발명의 바람직한 실시예에 따른 패드를 가는 반도체소자의 형성방법을 설명하기 위한 단면도들이다.3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device having a pad according to a preferred embodiment of the present invention.
상술한 기술적 과제를 해결하기 위한 반도체소자의 형성방법을 제공한다. 이 방법은 상부에 패드(pad)를 갖는 반도체기판을 준비하는 단계를 포함한다. 상기 반도체기판 전면에 식각방지막을 형성하고, 상기 식각방지막 상에 패시베이션막(passivation layer)을 형성한다. 상기 패시베이션막을 패터닝하여 상기 패드 상에 위치하는 상기 식각방지막의 소정영역을 노출시키는 패시베이션 콘텍홀을 형성한다. 상기 패시베이션 콘텍홀 내부를 포함하는 반도체기판 전면에 폴리이미드(polyimide)막을 형성한다. 상기 폴리이미드막을 현상액(develop solution)으로 패터닝하여 상기 패시베이션 콘텍홀에 의해 노출된 식각방지막을 노출시키는 예비 패드홀(preliminary pad hole)을 형성한다. 상기 예비 패드홀에 노출된 식각방지막을 식각하여 상기 패드를 노출시키는 패드홀을 형성한다. 이때, 상기 식각방지막은 상기 패드에 비하여 상기 현상액에 의한 식각률이 느린 절연막으로 형성한다.Provided are a method of forming a semiconductor device for solving the above technical problem. The method includes preparing a semiconductor substrate having a pad thereon. An etch stop layer is formed on the entire surface of the semiconductor substrate, and a passivation layer is formed on the etch stop layer. The passivation layer is patterned to form a passivation contact hole that exposes a predetermined region of the etch stop layer positioned on the pad. A polyimide film is formed on the entire surface of the semiconductor substrate including the passivation contact hole. The polyimide layer is patterned with a developer solution to form a preliminary pad hole exposing the etch stop layer exposed by the passivation contact hole. An etch stop layer exposed to the preliminary pad hole is etched to form a pad hole exposing the pad. In this case, the etch stop layer is formed of an insulating film having a slow etching rate due to the developer compared to the pad.
구체적으로, 상기 식각방지막은 상기 패시베이션막에 대하여 식각선택비를 갖는 절연막으로 형성하는 것이 바람직하다. 상기 식각방지막은 실리콘질화막 또는 언도프드 비정질 실리콘막 중 선택된 적어도 하나로 형성할 수 있다.Specifically, the etch stop layer is preferably formed of an insulating film having an etch selectivity with respect to the passivation film. The etch stop layer may be formed of at least one selected from a silicon nitride layer and an undoped amorphous silicon layer.
이하, 첨부한 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명은 여기서 설명되어지는 실시예에 한정되지 않고 다른 형태로 구체화 될 수도 있다. 오히려, 여기서 소개되는 실시들은 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어 진 것이다. 또한, 층이 다른 층 또는 기판 "상"에 있다고 언급되어지는 경우는 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나 또는 그들 사이에 제 3의 층이 개재 될 수도 있다. 명세서 전체에 걸쳐서 동일한 참조 번호들은 동일한 구성요소들을 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the implementations introduced herein are provided so that the disclosure may be thorough and complete, and the spirit of the present invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.
도 3 내지 도 7은 본 발명의 바람직한 실시예에 따른 패드를 갖는 반도체소자의 형성방법을 설명하기 위한 단면도들이다.3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device having a pad according to a preferred embodiment of the present invention.
도 3을 참조하면, 반도체기판(101) 상에 하부 층간절연막(102)을 형성하고, 상기 하부층간절연막(102) 상에 버퍼 패턴(103)을 형성한다. 도시하지는 않았지만, 상기 하부 층간절연막(102) 형성전에, 반도체소자에 필요한 트랜지스터, 커패시터 또는 비트라인등을 형성한다. 상기 하부 층간절연막(102)은 일반적인 층간절연막으로 사용되는 CVD 실리콘산화막으로 형성하는 것이 바람직하다. 상기 버퍼패턴(103)은 도전막, 예컨대, 금속막으로 형성하는 것이 바람직하다. 상기 버퍼 패턴(103)을 갖는 반도체기판(101) 상에 상부 층간절연막(104)을 형성하고, 상기 상부 층간절연막(104)을 선택적으로 패터닝하여 상기 버퍼 패턴(103)의 소정영역을 노출시키는 콘텍홀(105)을 형성한다. 상기 콘텍홀(105) 내부를 포함하는 반도체기판(101) 전면에 패드 도전막(106)을 형성한다. 상기 상부 층간절연막(104)은 일반적인 층간절연막으로 사용하는 CVD 실리콘산화막으로 형성하는 것이 바람직하다. 상기 패드 도전막(106)은 도전막인 금속막으로 형성하는 것이 바람직하다. 예를 들면, 알루미늄막으로 형성하는 것이 바람직하다.Referring to FIG. 3, a lower interlayer insulating film 102 is formed on a semiconductor substrate 101, and a buffer pattern 103 is formed on the lower interlayer insulating film 102. Although not shown, a transistor, a capacitor, a bit line, or the like necessary for the semiconductor device is formed before the lower interlayer insulating film 102 is formed. The lower interlayer insulating film 102 is preferably formed of a CVD silicon oxide film used as a general interlayer insulating film. The buffer pattern 103 is preferably formed of a conductive film, for example, a metal film. The upper interlayer insulating film 104 is formed on the semiconductor substrate 101 having the buffer pattern 103, and the upper interlayer insulating film 104 is selectively patterned to expose a predetermined region of the buffer pattern 103. The technical hole 105 is formed. The pad conductive layer 106 is formed on the entire surface of the semiconductor substrate 101 including the contact hole 105. The upper interlayer insulating film 104 is preferably formed of a CVD silicon oxide film used as a general interlayer insulating film. The pad conductive film 106 is preferably formed of a metal film which is a conductive film. For example, it is preferable to form with an aluminum film.
도 4를 참조하면, 상기 패드 도전막(106)을 패터닝하여 패드(106a)를 형성한다. 상기 패드(106a)는 반도체 소자의 내부와 외부간의 전기적 신호를 주고 받는다. 즉, 반도체 소자는 패드를 통하여 동작을 위한 동작 전압 및 전기적 신호를 받아들이고, 패드를 통하여 데이타들을 출력시킨다.Referring to FIG. 4, the pad conductive layer 106 is patterned to form a pad 106a. The pad 106a exchanges electrical signals between the inside and the outside of the semiconductor device. That is, the semiconductor device receives an operating voltage and an electrical signal for operation through a pad and outputs data through the pad.
상기 패드(106a)를 갖는 반도체기판(101) 전면에 식각방지막(107) 및 패시베이션막(108)을 차례로 형성한다. 상기 식각방지막(107)은 일반적인 폴리이미드막을 패터닝시 사용되는 현상액(develop solution)에 의한 식각률이 상기 패드에 비하여 느린 절연막으로 형성한다. 이에 더하여, 상기 식각방지막(107)은 상기 패시베이션막(108)에 대하여 식각선택비를 갖는 절연막으로 형성하는 것이 바람직하다. 상기 식각방지막(107)의 형성온도는 상기 패드(106a)의 용융점(melting point) 보다 작은 것이 바람직하다. 상기 식각방지막(107)은 예컨대, 질화막 또는 언도프드 비정질 실리콘막(un-doped amorphous silicon layer)으로 형성하는 것이 바람직하다.상기 질화막은 실리콘질화막(SiN) 또는 실리콘산화질화막(SiON)으로 형성할 수 있다.An etch stop layer 107 and a passivation layer 108 are sequentially formed on the entire surface of the semiconductor substrate 101 having the pads 106a. The etch stop layer 107 is formed of an insulating layer having a slower etch rate due to a developer solution used for patterning a general polyimide layer than the pad. In addition, the etch stop layer 107 may be formed of an insulating layer having an etch selectivity with respect to the passivation layer 108. The formation temperature of the etch stop layer 107 is preferably smaller than the melting point (melting point) of the pad 106a. The etch stop layer 107 may be formed of, for example, a nitride layer or an undoped amorphous silicon layer. The nitride layer may be formed of a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON). have.
상기 패시베이션막(108)은 차례로 적층된 PE 실리콘산화막(Plasma Enhanced silicon oxide) 및 실리콘산화질화막으로 형성하는 것이 바람직하다. 이에 더하여, 상기 패시베이션막(108)은 차례로 적층된 PE 실리콘산화막 및 실리콘질화막으로 형성할 수 있다.The passivation film 108 may be formed of a PE enhanced oxide oxide and a silicon oxynitride layer that are sequentially stacked. In addition, the passivation film 108 may be formed of a PE silicon oxide film and a silicon nitride film sequentially stacked.
도 5, 도 6 및 도 7을 참조하면, 상기 패시베이션막(108)을 패터닝하여 상기 패드(106a) 상에 위치하는 상기 식각방지막의 소정영역을 노출시키는 패시베이션 콘텍홀(109)을 형성한다. 상기 패시베이션 콘텍홀(109)의 내부를 포함하는 반도체기판(101) 전면에 폴리이미드막(110)을 형성한다. 상기 폴리이미드막(110)은 외부의 높은 온도, 마찰, 방사선 또는 여러종류의 화학약품으로 부터 반도체소자를 보호하는 역활을 한다.5, 6, and 7, the passivation layer 108 is patterned to form a passivation contact hole 109 exposing a predetermined region of the etch stop layer positioned on the pad 106a. The polyimide layer 110 is formed on the entire surface of the semiconductor substrate 101 including the inside of the passivation contact hole 109. The polyimide film 110 serves to protect the semiconductor device from external high temperature, friction, radiation, or various kinds of chemicals.
상기 폴리이미드막(110)에 선택적으로 노광공정을 진행하고, 상기 노광된 폴리이미드막(110)을 현상액으로 제거하여 상기 패시베이션 콘텍홀(109)에 노출된 식각방지막(107)을 노출시키는 예비 패드홀(115)을 형성한다. 이때, 상기 식각방지막(107)으로 인하여, 상기 현상액이 상기 패드(106a)를 식각하는 현상을 최소화할 수 있다. 그 결과, 반도체 소자를 반도체 칩으로 형성하는 어셈블리 공정의 와이어 본딩 공정에서 발생하던 불량을 최소화할 수 있다. 이에 더하여, 상기 폴리이미드막(110)의 패터닝시, 오정렬이 발생하여 재작업이 진행될지라도 상기 현상액으로 부터 상기 패드(106a)가 식각되는 현상을 최소화할 수 있다.A preliminary pad for selectively exposing the polyimide film 110 and removing the exposed polyimide film 110 with a developer to expose the etch stop layer 107 exposed to the passivation contact hole 109. The hole 115 is formed. In this case, the phenomenon in which the developer etches the pad 106a may be minimized due to the etch stop layer 107. As a result, defects occurring in the wire bonding process of the assembly process of forming the semiconductor element into the semiconductor chip can be minimized. In addition, when the polyimide film 110 is patterned, the phenomenon that the pad 106a is etched from the developer may be minimized even when misalignment occurs and rework is performed.
상기 예비 패드홀(115)의 측벽은 상기 폴리이미드막(110) 및 상기 패시베이션 콘텍홀(109)의 측벽으로 형성된다.Sidewalls of the preliminary pad holes 115 are formed as sidewalls of the polyimide layer 110 and the passivation contact hole 109.
상기 예비 패드홀(115)에 노출된 상기 식각방지막(107)을 상기 패드(106a)가 노출될때까지 식각하여 상기 패드(106a)를 노출시키는 패드홀(120)을 형성한다. 상기 패드홀(120)의 측벽은 상기 폴리이미드막(110), 상기 패시베이션콘텍홀(109)의 측벽 및 상기 식각방지막(107)으로 형성된다.The etch stop layer 107 exposed in the preliminary pad hole 115 is etched until the pad 106a is exposed to form a pad hole 120 exposing the pad 106a. The sidewall of the pad hole 120 is formed of the polyimide film 110, the sidewall of the passivation contact hole 109, and the etch stop layer 107.
상술한 바와 같이, 본발명에 따르면, 반도체 소자의 외부와 전기적 접촉을 이루는 패드(pad)와 패시베이션막 사이에 식각방지막을 형성함으로써, 반도체소자의 최종 보호막인 폴리이미드막을 패터닝시 사용되는 현상액이 상기 패드를 식각하는 것을 최소화할 수 있다. 그 결과, 상기 현상액으로 부터 상기 패드가 식각되어 발생하던 어셈블리 공정의 불량을 최소화할 수 있다.As described above, according to the present invention, by forming an anti-etching film between the pad and the passivation film in electrical contact with the outside of the semiconductor device, the developer used when patterning the polyimide film, which is the final protective film of the semiconductor device Etching the pad can be minimized. As a result, defects in the assembly process caused by etching the pads from the developer can be minimized.
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| CN111162007B (en) * | 2018-11-08 | 2022-04-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
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