KR20030095568A - Method For Forming Gate Electrodes Of Semiconductor Devices - Google Patents

Abstract

PURPOSE: A method for forming a gate electrode of a semiconductor device is provided to be capable of easily forming a silicide layer of the gate electrode while restraining the electrical characteristic deterioration of a transistor, and reducing the contact resistance of a transistor driving circuit. CONSTITUTION: A gate isolating layer(20) is formed at the upper portion of an active region of a semiconductor substrate(10). After depositing a polycrystalline silicon layer(30) at the upper portion of the gate isolating layer, an amorphous polycrystalline silicon layer(40) is deposited on the polycrystalline silicon layer. A gate electrode pattern is formed by selectively etching the polycrystalline silicon layer and the amorphous polycrystalline silicon layer. A metal layer is deposited at the upper portion of the resultant structure. The amorphous polycrystalline silicon layer and the metal layer are transformed into a silicide layer.

Description

Method for forming a gate electrode of a semiconductor device {Method For Forming Gate Electrodes Of Semiconductor Devices}

The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, to a method of forming a gate electrode of a semiconductor device to reduce the contact resistance and improve electrical characteristics of a transistor by stacking an amorphous polycrystalline silicon layer. will be.

In general, as the integration of semiconductor devices increases, the design rules become finer, so that the source / drain size of the MOS transistor, the line width of the gate electrode, and the line width of the metal wiring are reduced. In particular, when the line width of the metal wiring is reduced, the size of the contact hole for contacting the gate electrode and the metal wiring or contacting the source / drain and the metal wiring is also reduced. In this case, since the contact resistance of the gate electrode and the metal wiring increases, the resistance of the metal wiring increases, and eventually, the operation speed of the semiconductor element becomes slow. Nevertheless, the demand for high speed as well as high integration of semiconductor devices is increasing.

Currently, in a field effect transistor (FET) of a general CMOS (Complementary Metal Oxide Silicon) transistor structure, a silicide having a low specific resistance as an upper layer of the gate electrode in order to reduce the contact resistance of the transistor driving circuit. Techniques for forming the film have been developed. In the initial stage of silicide, the process of forming silicide on the gate electrode and the process of forming silicide on the source / drain were performed as separate processes. However, in consideration of simplicity and cost reduction, the silicide is formed on the gate electrode and the source / drain. A Salicide (Salicide: Self Aligned Silicide) process has been developed in which the same process is performed.

In the salicide process, when a high melting point metal is laminated on a silicon exposed part and an insulator at the same time, and then heat treated, the silicon part undergoes a silicide reaction and is transformed into a silicide, and the high melting point metal on the insulator is not It exists as it is. Therefore, the unreacted high melting point metal must be selectively etched and removed to leave only silicide. The salicide process has begun to be applied to the manufacture of MOS transistors or non-memory devices, replacing the salicide formation process by the conventional chemical vapor deposition process.

In recent years, as the ultra-high integration of semiconductor devices has been reduced, the width of the polycrystalline silicon wiring and the size of the contact hole are further reduced, making it difficult to form a silicide layer, for example, a titanium silicide (TiSi ₂ ) layer in the contact hole. This is because when the titanium silicide layer is formed on the polycrystalline silicon layer, agglomeration of the titanium silicide layer is likely to occur due to diffusion of titanium atoms along the non-uniform grain boundary of the polycrystalline silicon layer. As a result, it becomes difficult to uniformly generate the titanium silicide layer, thereby increasing the contact resistance variation of the contact holes. To solve this problem, a method of amorphizing the polycrystalline silicon layer has begun to be used. One such method is the Pre-Amorphization-Implant (PAI) technique. The PAI technique amorphousizes the surface of the polycrystalline silicon layer by ion implanting an element of an N-type impurity such as arsenide (As) into the polycrystalline silicon layer before depositing the titanium layer on the polycrystalline silicon layer of the gate electrode. Therefore, since the polycrystalline silicon layer causes a phase shift from C49 to C54, the formation of the titanium silicide layer can be promoted. As a result, the contact resistance variation of the transistor driving circuit can be reduced, and further, the resistance of the metal wiring can be reduced.

By the way, the conventional PAI technique can easily form the silicide layer of a gate electrode by ion-injecting aceide (As) to the polycrystal silicon layer of a gate electrode.

However, when arsenide (As) is ion implanted into the polycrystalline silicon layer of the gate electrode, the arsenide (As) is also ion implanted in the source / drain (not shown), which is an N + / P + diffusion region. As a result, the current change of the transistor occurs, and further, the electrical characteristics deteriorate, so that the subthreshold leakage current is likely to increase.

Accordingly, it is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device, which is capable of easily forming a silicide layer of a gate electrode while suppressing deterioration of electrical characteristics of the transistor.

Another object of the present invention is to provide a method for forming a gate electrode of a semiconductor device to reduce the contact resistance of the transistor driving circuit.

1 to 6 are cross-sectional process diagrams showing a gate electrode forming method of a semiconductor device according to the present invention.

Gate electrode forming method of a semiconductor device according to the present invention for achieving the above object

Forming a gate insulating film on an active region of the semiconductor substrate; Stacking a polycrystalline silicon layer on the gate insulating film and then laminating an amorphous polycrystalline silicon layer on the polycrystalline silicon layer; Forming the amorphous polycrystalline silicon layer and the polycrystalline silicon layer in a pattern of the same gate electrode; Depositing a silicide metal layer on the semiconductor substrate including the amorphous polycrystalline silicon layer; And forming a silicide layer by silicifying the amorphous polycrystalline silicon layer and the metal layer.

Preferably, the amorphous polycrystalline silicon layer may be laminated at a temperature of 540 ° C to 580 ° C. In addition, it is preferable to deposit the amorphous polycrystalline silicon layer at a pressure of 400 to 500 mTorr.

Preferably, all of the amorphous polycrystalline silicon layers can be transformed into the silicide layer. It is preferable to laminate the amorphous polycrystalline silicon layer to a thickness of 500 to 600 kPa.

Preferably, the amorphous polycrystalline silicon layer can be laminated by a low pressure chemical vapor deposition process.

Hereinafter, a method of forming a gate electrode of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 6 are cross-sectional process diagrams illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.

Referring to FIG. 1, first, a gate insulating film 20, for example an oxide film, is grown on a active region of a semiconductor substrate 10 such as a P-type single crystal silicon substrate by a thermal oxidation process. Although not illustrated in the drawings for convenience of description, it is obvious that the isolation layer is formed in advance in a field region of the semiconductor substrate 10 by a conventional process in order to distinguish the active region of the semiconductor substrate 10.

Subsequently, the polycrystalline silicon layer 30, which is a lower conductive layer for the gate electrode, is formed on the gate insulating film 20 using a low pressure chemical vapor deposition (LPCVD) process, for example, at a temperature of 610 to 630 ° C. At a thickness of 2000 ~ 2100Å. Here, when the polycrystalline silicon layer 30 is stacked, the P-type impurity such as boron (B) or the N-type impurity such as phosphorus (P) is not doped.

Referring to FIG. 2, after lamination of the polycrystalline silicon layer 30 is completed, the amorphous polycrystalline silicon layer 40, which is an upper conductive layer for the gate electrode, may be formed on the polycrystalline silicon layer 30. Laminate at a temperature of 580 ° C. In this case, the amorphous polycrystalline silicon layer 40 is preferably laminated at a pressure of 400 to 500 mTorr. In addition, in order to deform the amorphous polycrystalline silicon layer 40 to the silicide layer 50 of FIG.

Thus, the amorphous polycrystalline silicon layer 40 facilitates the formation of the silicide layer in a subsequent process for forming the silicide layer of the gate electrode. Moreover, the amorphous polycrystalline silicon layer 40 is deposited by a low pressure chemical vapor deposition process, which has no effect on the source / drain (S / D) to be formed in subsequent processes.

Therefore, the present invention can easily form the silicide layer of the gate electrode, and can reduce the contact resistance of the transistor driving circuit and further suppress the deterioration of the electrical characteristics.

Meanwhile, the amorphous polycrystalline silicon layer 40 is stacked while being doped with a dopant gas of P-type impurities such as boron (B) or N-type impurities such as phosphorus (P), or the amorphous polycrystalline silicon layer. It is possible to ion-implant P-type impurities such as boron (B) or N-type impurities such as phosphorus (P) after laminating (40).

Referring to FIG. 3, after the deposition of the amorphous polycrystalline silicon layer 40 is completed, the amorphous polycrystalline silicon layer (on the gate insulating film 20 of the portion for the gate electrode using a photolithography process) 40 and the polycrystalline silicon layer 30 are formed in the same pattern.

Then, a nitride film having a high etching selectivity with respect to the insulating film for the spacer 50, for example, the oxide film, which is the gate insulating film 20, is laminated on the semiconductor substrate 10 having the resultant structure. Thereafter, the nitride layer is etched until the surface of the amorphous polycrystalline silicon layer 40 is exposed by an etch back process having anisotropic etching characteristics. At this time, the gate insulating film 20 on the active region of the substrate 10 is also exposed. Accordingly, spacers 50 are formed on left and right sidewalls of the amorphous polycrystalline silicon layer 40 and the polycrystalline silicon layer 30.

Referring to FIG. 4, after the spacers 5 are formed, impurities for source / drain (S / D), for example, N-type impurities, are implanted into the active region of the substrate 10 using an ion implantation process. Let's do it. Therefore, the source / drain S / D is formed in the active region of the substrate 10 with the gate electrode interposed therebetween.

Next, the source / drain S / D is exposed by etching the gate insulating film 20 on the source / drain S / D by a wet etching process. Then, a titanium layer for, for example, a titanium silicide layer is deposited by sputtering on the entire surface of the semiconductor substrate 10 including the amorphous polycrystalline silicon layer 40 and the source / drain (S / D). This is subjected to primary heat treatment, for example, by a rapid heat treatment process.

At this time, the amorphous polycrystalline silicon layer 40 and the titanium layer on the source / drain (S / D) cause a silicide reaction to deform into silicide layers 60 and 70 such as a titanium silicide layer, and the rest of the rest. The titanium layer on the region remains as it is without causing the silicide reaction. Then, the unreacted titanium layer is removed by a wet etching process using ammonia. Then, the silicide layers 60 and 70 are transformed into a complete silicide layer by secondary heat treatment, for example, by a rapid heat treatment process.

Referring to FIG. 6, once the silicide layers 60 and 70 are formed, the interlayer insulating film 80 is laminated and planarized on the resultant structure using a conventional process. Subsequently, a contact hole is formed in a part of the interlayer insulating film 80 for exposing the contact portions of the silicide layers 60 and 70 by using a photolithography process, and the metal layer 90 for metal wiring 90 is stacked, followed by photolithography. The metal layer 90 is formed in the pattern of a metal wiring by a process.

Accordingly, the present invention laminates the upper amorphous polycrystalline silicon layer on the lower polycrystalline silicon layer for the gate electrode using a low pressure chemical vapor deposition process. Subsequently, a silicide layer is formed on the amorphous polycrystalline silicon layer by laminating a silicide metal layer on the amorphous polycrystalline silicon layer and heat-treating it by a rapid heat treatment process.

Therefore, the present invention does not affect the source / drain even when the silicide layer of the gate electrode is formed, and thus it is easy to form the silicide layer of the gate electrode. As a result, the contact resistance of the transistor driving circuit is reduced. In addition, since the current change of the transistor is suppressed, deterioration of the electrical characteristics of the transistor can be suppressed, and an increase in leakage current of the subthreshold can be suppressed.

As described above, in the method for forming a gate electrode of a semiconductor device according to the present invention, a polycrystalline silicon layer for a gate electrode and an amorphous polycrystalline silicon layer are sequentially stacked on a gate insulating film of a semiconductor substrate. Then, the amorphous polycrystalline silicon layer and the polycrystalline silicon layer are formed in a pattern of the same gate electrode, and a source / drain (S / D) is formed in an active region of the substrate with the pattern of the gate electrode interposed therebetween. Forming a spacer on both sidewalls of the gate electrode and the left and right sides of the pattern of the gate electrode, laminating a metal layer for silicide on the amorphous polycrystalline silicon layer, and forming the amorphous polycrystalline silicon layer and a silicide layer of the metal layer. .

Thus, the present invention stacks the amorphous polycrystalline silicon layer by a low pressure chemical vapor deposition process and thus does not affect the source / drain to be formed in a subsequent process. As a result, the contact resistance of the transistor driving circuit can be reduced, the change in the current of the transistor can be suppressed, so that the electrical characteristics of the transistor can be improved and the leakage current increase of the subthreshold can be suppressed.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (6)

Forming a gate insulating film on an active region of the semiconductor substrate; Stacking a polycrystalline silicon layer on the gate insulating film and then laminating an amorphous polycrystalline silicon layer on the polycrystalline silicon layer; Forming the amorphous polycrystalline silicon layer and the polycrystalline silicon layer in a pattern of the same gate electrode; Depositing a silicide metal layer on the semiconductor substrate including the amorphous polycrystalline silicon layer; And Forming a silicide layer by silicifying the amorphous polycrystalline silicon layer and the metal layer. The method according to claim 1, wherein the amorphous polycrystalline silicon layer is laminated at a temperature of 540 ° C to 580 ° C. The method of claim 2, wherein the amorphous polycrystalline silicon layer is deposited at a pressure of 400 to 500 mTorr. The method according to claim 1, wherein all of the amorphous polycrystalline silicon layers are transformed into the silicide layer. 5. The method for forming a gate electrode of a semiconductor device according to claim 4, wherein the amorphous polycrystalline silicon layer is laminated to a thickness of 500 to 600 GPa. 2. The method of claim 1, wherein the amorphous polycrystalline silicon layer is laminated by a low pressure chemical vapor deposition process.