KR20030094721A - Method and apparatus for driving organic electroluminescence device - Google Patents

Abstract

PURPOSE: A method and an apparatus for driving an organic electro-luminescence device are provided to compensate a threshold voltage of a driving transistor by installing a diode between a column line and the driving transistor or on the column line. CONSTITUTION: An apparatus for driving an organic electro-luminescence device include a plurality of column lines(CL1-CLm), a plurality of row lines(RL0-RLn), a plurality of pixels((1,1)-(m,n)), a driving transistor, a switching transistor, and a diode. Data are supplied through the column lines(CL1-CLm). The row lines(RL0-RLn) are used for selecting scan lines. The pixels((1,1)-(m,n)) are formed at pixel regions between the column lines(CL1-CLm) and the row lines(RL0-RLn). The driving transistor is used for controlling the current supplied to the pixels((1,1)-(m,n)) in response to the data. The switching transistor is used for supplying the data of the column lines(CL1-CLm) to the driving transistor. The diode is used for compensating the threshold voltage of the driving transistor.

Description

TECHNICAL AND APPARATUS FOR DRIVING ORGANIC ELECTROLUMINESCENCE DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device, and more particularly, to a method and an apparatus for driving an organic light emitting display device to improve the uniformity of luminance by compensating the threshold voltage of a thin film transistor.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FED) plasma display panels (hereinafter referred to as "PDPs") and electroluminescence. And an electroluminescence device.

Among them, PDP is attracting attention as the most favorable display device for light and small size and large screen because of its simple structure and manufacturing process, but it has the disadvantages of low luminous efficiency, low luminance and high power consumption. On the other hand, active matrix LCDs with thin film transistors ("TFTs") as switching elements have difficulty in making large screens because they use semiconductor processes, but they are used as display elements in notebook computers. have. In contrast, the electroluminescent device is classified into an inorganic electroluminescent device and an organic electroluminescent device according to the material of the light emitting layer. The electroluminescent device is a self-light emitting device that emits light, and has a high response speed and high luminous efficiency, luminance, and viewing angle.

In the organic light emitting display device, the anode electrode 2 is formed on the glass substrate 1 using the transparent electrode pattern, and the hole injection layer 3, the light emitting layer 4, and the electron injection layer 5 are formed thereon. Are stacked. The cathode electrode 6 is formed on the electron injection layer 5 as a metal electrode.

When a driving voltage is applied to the anode electrode 2 and the cathode electrode 6, holes in the hole injection layer 3 and electrons in the electron injection layer 5 proceed toward the light emitting layer 33 to excite the light emitting layer 4. Causes the light emitting layer 4 to emit visible light. Thus, an image or an image is displayed by the visible light generated from the light emitting layer 4.

2 and 3, in the organic light emitting diode device, m column lines CL1 to CLm and n row lines RL1 to RLn are formed to cross the column lines CL1 to CLm. Thus, m × n pixels P are arranged in a matrix type.

In addition, the organic light emitting display device is formed at the intersection of the column lines CL1 to CLm and the row lines RL1 to RLn and serves as a switching element, the switch TFT SW_TFT, the cell driving voltage source VDD and the electric field. A driving TFT DRV_TFT is formed between the light emitting cells OLED to drive the electroluminescent cell OLED, and a capacitor Cst is connected between the switch TFT SW_TFT and the driving TFT DRV_TFT. The switch TFT (SW_TFT) and the driving TFT (DRV_TFT) are implemented with a P type MOS-FET.

The switch TFT SW_TFT is turned on in response to the negative scan voltages from the low lines RL1 to RLn to conduct a current path between its source terminal and the drain terminal, as well as on the low lines RL1 to RLn. When the voltage is below its threshold voltage (Vth), it is kept off. In the on-time period of the switch TFT SW_TFT, the data voltage Vcl from the column lines CL is applied to the gate terminal of the driving TFT DRV_TFT via the source terminal and the gate terminal of the switch TFT SW_TFT. . On the contrary, in the off time period of the switch TFT SW_TFT, the current path between the source terminal and the drain terminal of the switch TFT SW_TFT is opened so that the data voltage Vcl is not applied to the driving TFT DRV_TFT.

The driving TFT DRV_TFT adjusts the current between the source terminal and the drain terminal according to the data voltage Vcl supplied to its gate terminal to emit the electroluminescent cell OLED with brightness corresponding to the data voltage Vcl. do.

The capacitor Cst stores the difference voltage between the data voltage Vcl and the cell driving voltage VDD to maintain a constant voltage applied to the gate terminal of the driving TFT DRV_TFT for one frame period, and also to display the electroluminescent cell. The current applied to the OLED is kept constant for one frame period.

4 illustrates a scan voltage and a data voltage applied to the organic light emitting diode of FIG. 2.

Referring to FIG. 4, a negative scan pulse scan is sequentially applied to the row lines RL1 to RLn and a data voltage data is synchronized to the scan pulse scan to the column lines CL1 to CLn. This is applied at the same time.

However, the conventional organic light emitting diode device has a problem that the luminance of the organic light emitting diode device is lowered due to the threshold voltage Vth of the driving TFT DRV_TFT. This will be described in detail with reference to Equation 1 below.

Here, Vth means the threshold voltage of the driving TFT (DRV_TFT).

As can be seen from Equation 1, the current I _OLED applied to the electroluminescent cell OLED is lowered by the threshold voltage Vth of the driving TFT DRV_TFT. Accordingly, in order to increase the luminance of the organic light emitting diode device, a method for compensating the threshold voltage of the driving TFT (DRV_TFT) is required.

Accordingly, an object of the present invention is to provide a method and apparatus for driving an organic light emitting device to compensate for a threshold voltage of a TFT to increase luminance uniformity.

1 is a cross-sectional view schematically showing a cross-sectional structure of a conventional organic light emitting display device.

2 is a plan view schematically illustrating a pixel arrangement of a conventional organic light emitting display device.

3 is an equivalent circuit diagram of a pixel illustrated in FIG. 2.

4 is a waveform diagram illustrating signals supplied to column and row lines illustrated in FIGS. 2 and 3.

5 is a plan view illustrating a pixel arrangement of an organic light emitting display device according to a first exemplary embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of the pixel illustrated in FIG. 5.

FIG. 7 is a waveform diagram illustrating signals supplied to the column lines and the row lines shown in FIGS. 5 and 6.

8 is a block diagram illustrating a driving device of an organic light emitting display device according to a first exemplary embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating in detail a data / initialization voltage selection circuit installed in the column driver shown in FIG. 8.

10 is a plan view illustrating a pixel arrangement of an organic light emitting display device according to a second exemplary embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram of the pixel illustrated in FIG. 10.

FIG. 12 is a waveform diagram illustrating signals supplied to column and row lines shown in FIGS. 10 and 11.

13 is a block diagram illustrating a driving device of an organic light emitting display device according to a second exemplary embodiment of the present invention.

14 is an equivalent circuit diagram of a pixel illustrating a pixel configuration of an organic light emitting display device according to a third exemplary embodiment of the present invention.

15 is an equivalent circuit diagram of a pixel illustrating a pixel configuration of an organic light emitting display device according to a fourth exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1 glass substrate 2 anode electrode

3: hole injection layer 4: light emitting layer

5: electron injection layer 6: cathode electrode

81,131: video signal generator 82,132: interface

83,133: Timing controller 84,134: Gamma voltage generator

85,135: column driver 86,136: organic light emitting panel

87,137: Low driver D1, D11: Diode

DRV_TFT, DRV: Driving Thin Film Transistor OLED: Electroluminescent Cell

Cst: Capacitor RL: Lowline

CL: Column line B1, B2: Buffer

SW_TFT, SW1, SW2, SW3, SW11, SW12, SW31, SW32, SW33, SW41, SW42, SW43: Switch Thin Film Transistor

In order to achieve the above object, an organic light emitting display device according to an embodiment of the present invention, a plurality of column lines to which data is supplied, a plurality of row lines intersecting the column lines to select a scan line, and a column A cell formed in the pixel region between the lines and the row lines, a driving transistor for controlling a current supplied to the cell in response to the data, and an Nth of the row lines (where N is a positive integer greater than 0) And a switch transistor for supplying data from the column lines to the driving transistor in response to the voltage on the low line, and a diode for compensating the threshold voltage of the driving transistor with respect to the data supplied to the driving transistor.

In the organic light emitting device according to the embodiment of the present invention, the threshold voltage of the diode is characterized in that the same as the threshold voltage of the driving transistor.

In the organic light emitting device according to the embodiment of the present invention, the diode is characterized in that connected to the column line.

In the organic light emitting device according to the embodiment of the present invention, the diode is characterized in that connected between the switch transistor and the driving transistor.

An organic light emitting display device according to an exemplary embodiment of the present invention includes a driving voltage source for supplying a driving voltage to a cell, a capacitor installed between the driving transistor, the driving voltage source, and a switching transistor, and a capacitor for charging data; And a second switch transistor for controlling the voltage supplied to the capacitor in response to the voltage on the first low line.

The organic light emitting diode according to the embodiment of the present invention further includes a third switch transistor for controlling a current supplied to the cell in response to the voltage on the N−1th low line among the row lines.

The organic light emitting display device according to the embodiment of the present invention further includes an initialization voltage source for generating an initialization voltage different from the data.

In the organic light emitting device according to the embodiment of the present invention, the second switch transistor is connected between the N-th low line and the initialization voltage source, characterized in that for supplying data and other initialization voltage to the capacitor.

In the organic light emitting device according to the embodiment of the present invention, the capacitor is initialized by charging an initialization voltage before charging data by the control of the second switch transistor, the third switch transistor is the N-1 th low line It cuts off the current supplied to the cell in the initialization period of the capacitor in response to the voltage of the phase.

In the organic light emitting device according to the embodiment of the present invention, data and an initialization voltage are alternately supplied to the column line.

The organic light emitting diode according to the embodiment of the present invention further includes at least one initial voltage line formed between the initialization voltage source and the second switch transistor to supply the initialization voltage to the second switch transistor.

In the organic light emitting device according to the embodiment of the present invention, the initialization voltage is characterized in that the lower than the threshold voltage of the diode than the data.

A method of driving an organic light emitting display device according to an embodiment of the present invention includes compensating data with a threshold voltage of a diode formed on a signal transmission path of data supplied to a driving transistor, and supplying the compensated data to the driving transistor. Steps.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, the diode is characterized in that formed on the column line.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, the diode is formed between the switch transistor and the drive transistor.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, the threshold voltage of the diode is characterized in that the same as the threshold voltage of the driving transistor.

The method of driving an organic light emitting display device according to an embodiment of the present invention further includes supplying an initialization voltage different from data to a capacitor provided between the driving transistor and the switch transistor to initialize the capacitor.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, supplying data to the driving transistor is characterized in that the data is supplied to the driving transistor after the capacitor is initialized.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, supplying data and an initialization voltage to the column lines alternately, and N-1th (where N is a positive integer greater than 0) among the row lines. Supplying a scan voltage synchronized with an initialization voltage to a low line, and supplying a scan voltage synchronized with data to an Nth low line among the low lines.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, supplying an initializing voltage different from data to an initial voltage line, and the N-1 th of the row lines (where N is a positive integer greater than 0). Initializing a capacitor provided between the driving transistor and the switch transistor by supplying a scan voltage synchronized with the initialization voltage to the low line to turn on the second switch transistor connected to the N-th low line; And supplying a scan voltage synchronized with data to the Nth low line.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, the initialization voltage is lower than the threshold voltage of the diode than the data.

In the method of driving an organic light emitting display device according to an embodiment of the present invention, the third switch transistor disposed between the N-1 th low line, the cell and the driving transistor is turned on in response to the voltage on the N-1 th low line. Turning off to cut off the current supplied to the cell.

In the driving device of the organic light emitting display device according to an embodiment of the present invention, a plurality of column lines and a plurality of row lines intersect with each other, and a cell disposed in a pixel region between the column lines and the row lines is formed and responds to data. A display panel having a driving transistor for driving a cell, a switch transistor for supplying data to the driving transistor, and a diode for compensating threshold voltages of the driving transistor, a column driver for supplying data to the column lines, and a row; A row driver for sequentially supplying scan voltages to the lines and a controller for supplying data to the column driver and controlling the timing of operation of the column driver and the row driver are provided.

In the driving apparatus of the organic light emitting device according to the embodiment of the present invention, the threshold voltage of the diode is characterized in that the same as the threshold voltage of the driving transistor.

In the driving apparatus of the organic light emitting device according to the embodiment of the present invention, the diode is characterized in that connected to the column line.

In the driving apparatus of the organic light emitting device according to the embodiment of the present invention, the diode is characterized in that connected between the switch transistor and the driving transistor.

In the driving apparatus of the organic light emitting device according to the embodiment of the present invention, the switch transistor is to supply the data to the driving transistor in response to the scan voltage on the N (where N is a positive integer greater than zero). It features.

An apparatus for driving an organic light emitting display device according to an embodiment of the present invention includes a driving voltage source for supplying a driving voltage to a cell, a capacitor installed between the driving transistor, the driving voltage source, and a switch transistor to charge data, and N-1. And a second switch transistor for controlling a voltage supplied to the capacitor in response to the voltage on the first low line.

The driving device of the organic light emitting display device according to the embodiment of the present invention further includes a third switch transistor for controlling a current supplied to the cell in response to the voltage on the N−1th low line.

The driving device of the organic light emitting display device according to the embodiment of the present invention further includes an initialization voltage source for generating an initialization voltage different from the data.

In the driving apparatus of the organic light emitting device according to the embodiment of the present invention, the second switch transistor is connected between the N-1th low line and the initialization voltage source, characterized in that for supplying the initialization voltage to the capacitor.

In the driving device of the organic light emitting device according to the embodiment of the present invention, the capacitor is initialized by charging an initialization voltage before charging data by the control of the second switch transistor, the third switch transistor is N-1 And cuts off the current supplied to the cell in the initialization period of the capacitor in response to the voltage on the first low line.

In the driving device of the organic light emitting device according to the embodiment of the present invention, the column line is characterized in that the data and the initialization voltage are alternately supplied.

In the driving device of the organic light emitting display device according to the embodiment of the present invention, the display panel is formed between the initialization voltage source and the second switch transistor to provide at least one initial voltage line for supplying the initialization voltage to the second switch transistor. It is further provided.

In the driving device of the organic light emitting device according to the embodiment of the present invention, the initialization voltage is characterized in that lower than the threshold voltage of the diode than the data.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 15.

5 and 6, an organic light emitting display device according to a first embodiment of the present invention includes m column lines CL1 to CLm and n + 1 row lines RL0 to RLn. In the pixel region, m × n pixels ((1,1) to (m, n)) are formed in a matrix type.

Each of the pixels ((1,1) to (m, n)) includes the column lines CL1 to CLm and the Nth row line RL (N), where N is a positive integer greater than 0 and less than n. A first switch TFT (SW1) formed at the intersection of the &lt; RTI ID = 0.0 &gt;), &lt; / RTI &gt; a driving TFT (DRV) formed between the cell driving voltage source (VDD) and the electroluminescent cell (OLED) to drive the electroluminescent cell (OLED), The second switch TFT SW2 formed at the intersection of the column lines CL1 to CLm and the N-th low line RL (N-1), and the first switch TFT SW1 and the driving TFT DRV_TFT. Capacitor Cst connected between the plurality of transistors) and a diode D1 connected between the first switch TFT SW1 and the capacitor Cst. The switch TFTs SW1 and SW2, the driving TFT DRV_TFT and the diode D1 are implemented with a P type MOS-FET.

The source terminal of the first switch TFT SW1 is connected to the column lines CL1 to CLm, and the drain terminal is connected to the diode D1 via the first node n1. The gate terminal of the first switch TFT SW1 is connected to the Nth low line RL (N). The first switch TFT SW1 is turned on in response to the negative scan voltage from the Nth low line RL (N) to conduct a current path between its source terminal and the drain terminal as well as the Nth The OFF state is maintained when the voltage on the low line RL (N) is less than or equal to its threshold voltage. In the on-time period of the switch TFT SW1, the data voltage Vcl from the column lines CL1 to CLm is applied to the diode D1 via the source terminal and the drain terminal of the first switch TFT SW1. . On the contrary, in the off time period of the first switch TFT SW1, the current path between the source terminal and the drain terminal of the first switch TFT SW1 is opened so that the data voltage Vcl is not applied to the diode D1.

The source terminal of the driving TFT DRV is connected to the common voltage line VDDL, and is connected to one terminal of the capacitor Cst, and the drain terminal is connected to the anode electrode of the electroluminescent cell OLED. The gate terminal of the driving TFT DRV is connected to the drain terminal of the diode D1, the capacitor Cst, and the second switch TFT SW2 via the second node n2. The driving TFT DRV adjusts the current between the source terminal and the drain terminal in response to the gate voltage Vcl-Vth supplied to its gate terminal, thereby adjusting the current of the electroluminescent cell at a brightness corresponding to the gate voltage Vcl-Vth. OLED). Here, the gate voltage Vcl-Vth of the driving TFT DRV is a voltage subtracted by the threshold voltage Vth of the diode D1 from the data voltage Vcl from the column lines CL1 to CLm.

The capacitor Cst is initialized by charging the negative voltage supplied from the column lines CL1 to CLm in advance before the scan voltage is supplied to the N-th row line RL (N). The initializing of the capacitor Cst is such that the data voltage Vcl is supplied so that the data voltage Vcl on the first node n1 can be supplied to the second node n2 connected to the gate terminal of the driving TFT DRV. This is to charge the voltage on the second node n2 to a voltage lower than or equal to the threshold voltage of the diode D1 before the voltage is supplied to the first node n1. In other words, the capacitor Cst is initialized by supplying a voltage lower than the threshold voltage Vth of the diode D1 for a predetermined period before the data voltage Vcl is supplied. After the capacitor Cst is initialized and the data voltage Vcl is applied, the capacitor Cst stores the difference voltage between the gate voltage Vcl-Vth and the cell driving voltage VDD of the driving TFT DRV. The gate voltage Vcl-Vth of the driving TFT DRV is kept constant for one frame period, and the current applied to the electroluminescent cell OLED is kept constant for one frame period.

The source terminal of the second switch TFT SW2 is connected to the column lines CL1 to CLm, and the drain terminal of the second switch TFT SW2 is connected to the diode D1, the capacitor Cst, and the driving TFT DRV via the second node n2. Connected. The gate terminal of the second switch TFT SW2 is connected to the N-1th low line RL (N-1). The second switch TFT SW2 is turned on by the voltage on the N-1 th low line RL (N-1) before the data voltage Vcl is supplied to the capacitor Cst, and thus the column lines CL1 through. The capacitor Cst is initialized by supplying the initialization voltage on CLm to the capacitor Cst.

Diode D1 is implemented with a P-type MOS TFT. The source terminal of the diode TFT D1 is connected to the drain terminal of the first switch TFT SW1 via the first node n1. The drain terminal and the gate terminal of the TFT D1 are short-circuited via the second node n2. The drain terminal and the gate terminal of the diode TFT D1 are connected to the second switch TFT SW2, the capacitor Cst, and the driving TFT DRV via the second node n2. The diode D1 has the same threshold voltage Vth as that of the driving TFT DRV, thereby compensating the data voltage supplied to the gate terminal of the driving TFT DRV by the threshold voltage Vth of the driving TFT DRV. .

FIG. 7 illustrates a scan voltage and a data voltage applied to the organic light emitting display device illustrated in FIGS. 5 and 6.

Referring to FIG. 7, a negative scan voltage is applied to the uppermost dummy row line RL0 during the Ta period. In the Tc period included at the end of the Ta period, the voltage on the dummy low line RL0 maintains the negative scan voltage, and the initialization voltage VI for initializing the capacitor Cst in the column lines CL1 to CLm. Is supplied. During the Ta and Tc periods, the second switch TFT SW2 connected to the dummy low line RL0 is turned on. The initialization voltages VI on the column lines CL1 to CLm are pixels included in the first scan line via the second switch TFT SW2 by the second switch TFT SW2 that remains on for the period Tc. It is supplied to the second node n2 and the capacitor Cst of ((1,1), (2,1) ... (m-1, 1), (m, 1)). Meanwhile, additional dummy data may be supplied to the column lines CL1 to CLm within the Ta period.

At the time transition from the Ta period to the Tb period, the voltage on the dummy low line RL1 is inverted to a high logic voltage so that the pixels ((1,1), (2,1) ... ( The first switch TFT (SW1) of m-1,1) and (m, 1) is turned off.

During the Tb period, a negative scan voltage is applied to the first row line RL1 and data is supplied to the column lines CL1 to CLm at the same time. In this case, the pixels ((1,1), (2,1) ... (m-1,1), (m) included in the first scan line in response to the scan voltage on the first row line RL1 1), the first switch TFT SW1 is turned on to supply the data voltage Vcl to the first node n1. When the data voltage Vcl is applied, the diode D1 is turned on because the voltage on the second node n2 is lower by its threshold voltage Vth than the data voltage on the first node n1 by initialization. On, the data voltage Vcl on the first node n1 is supplied to the second node n2. At this time, the driving TFT DRV connected to the second node n2 supplies a current corresponding to the data value to the electroluminescent cell OLED by the data voltage Vcl supplied to its gate terminal. The capacitor Cst maintains the gate voltage of the driving TFT DRV. In the Tc period included in the later period of the Tb period, the voltage on the first low line RL1 maintains the negative scan voltage, and the initialization voltage VI for initializing the capacitor Cst in the column lines CL1 to CLm. ) Is supplied. Then, the initialization voltage VI on the column lines CL1 to CLm is transferred via the second switch TFT SW2 by the second switch TFT SW2 which is kept on during the Tc period included in the later period of the Tb period. The second node n2 of the pixels (1, 2), (2, 2) ... (m-1, 2), (m, 2) included in the first scan line is supplied.

As a result, the organic light emitting diode according to the first exemplary embodiment of the present invention has the second switch TFT SW2 connected to the N-1 th low line RL (N-1) corresponding to the previous scan line turned on. In the sustain period, the initialization voltage VI from the column lines CL1 to CLm is preliminarily supplied to the second node n2 and the capacitor Cst included in the pixels of the next scan line. After the second node n2 and the capacitor Cst are initialized as described above, when the scan pulse is supplied to the Nth row line RL (N) to the pixels of the next scan line, the column lines CL1 to CLm are separated from the column lines CL1 to CLm. The data voltage Vcl is supplied.

As described above, the organic light emitting diode according to the first embodiment of the present invention compensates the threshold voltage of the driving TFT DRV by using the threshold voltage of the diode D1, and thus applies the current applied to the electroluminescent cell OLED. I _OLED ) is prevented. This may be expressed as Equation 2 below.

Here, Vth means threshold voltages of the driving TFT DRV and the diode D1.

As can be seen from Equation 2, the current I _OLED applied to the electroluminescent cell OLED is compensated by the threshold voltage Vth of the driving TFT DRV by the threshold voltage Vth of the diode D1. The threshold voltage Vth of the driving TFT DRV is not lowered.

8 shows a driving apparatus for driving an organic light emitting display device according to a first embodiment of the present invention.

Referring to FIG. 8, an apparatus for driving an organic light emitting display device according to a first embodiment of the present invention includes an interface unit 82 receiving data and a synchronization signal from a video signal generator 81, and m column lines ( CL1 to CLm and n + 1 row lines RL0 to RLn intersect, and m × n pixels are matrixed in the pixel region between the column lines CL1 to CLm and the row lines RL0 to RLn. The organic light emitting panel 86 disposed thereon, the column driver 85 for supplying data to the column lines CL1 to CLm of the organic light emitting panel 86, and the row of the organic light emitting panel 86. A low driver 87 for supplying scan pulses to the lines RL0 to RLn, a gamma voltage generator 84 for supplying a gamma voltage Vγ to the column driver 85, and a color driver 85 And a timing controller 83 for controlling the low driver 87 and a panel driver 85 and 87 with the timing controller. And a multiple (83) the power generation portion 88 for generating a driving voltage and a cell driving voltage (VDD), and the initialization voltage (VI) required for.

The organic light emitting panel 86 includes an electroluminescent cell in which an anode electrode, a hole injection layer, a light emitting layer, and an electron injection layer are stacked, first and second switches SW1 and SW2, a diode D1, and a capacitor Cst. ) And the driving TFT (DRV) and the like are formed on the glass substrate.

The video signal generator 81 converts analog data from an input line (not shown) into digital data and supplies the vertical and horizontal synchronous signals and clock signals to the interface unit 82.

The interface unit 82 uses the LVDS (Low Voltage Differential Signaling), TMDS (Transition Minimized Differential Signaling), RSDS, and the like to synchronize data together with the data RGB from the video signal generator 81. The control signal TCS including the HV and the clock signal is supplied to the timing controller 83.

The timing controller 83 generates the column control signal CCS, samples the data RGB from the interface unit 83 in accordance with the control signal TCS, and the data RGB together with the column control signal CCS. Supply to the column driver (85). The column control signal CCS includes a shift clock, a latch signal, a multiplexer control signal, and the like of the column driver 85. In addition, the timing controller 83 generates a row control signal RCS including a start pulse for instructing the shift register to start operation, a shift clock of the shift register, and the like, and transmits the row control signal RCS to the low driver 87. Will be supplied.

The gamma voltage generator 84 divides the high potential common voltage and the low potential common voltage supplied from the power generator 88 to generate a gamma voltage Vγ corresponding to each gradation level of the data, and the gamma voltage Vγ. ) Is supplied to the column driver 85.

The column driver 85 supplies the data RGB to the column lines CL1 to CLm in response to the column control signal CCS supplied from the timing controller 83. After sampling the data RGB from the timing controller 83, the column driver 85 latches the data, decodes the latched data, and converts the gamma voltage Vγ corresponding to the data value into a data voltage ( Vcl). The data voltage Vcl generated from the column driver 85 is simultaneously supplied to the column lines CL1 to CLm in synchronization with the scan pulse generated from the low driver 87. In addition, the column driver 85 simultaneously supplies the initialization voltage VI to the column lines CL1 to CLm during the period allocated between the data supply periods.

The row driver 87 generates scan pulses falling to the negative scan voltage in response to the row control signal RCS supplied from the timing controller 83, and the scan pulses are output to the low line of the organic light emitting panel 86. To RL0 to RLn sequentially. The loud driver 87 includes a shift register that sequentially generates negative scan pulses, and a level shifter for shifting the swing width of the scan voltage to a level suitable for driving the switch TFTs SW1 and SW2.

The power generator 88 generates a high potential common voltage and a low potential common voltage, supplies the common voltages to the gamma voltage generator 84, and provides an integrated circuit (IC) of the column driver 85. The driving voltage, the initialization voltage VI, the cell driving voltage VDD, and the like are generated and the voltages are supplied to the column driver 85. In addition, the power generation unit 88 generates a negative scan voltage, and supplies the scan voltage to the low driver 87.

9 shows the data / initialization voltage selection circuit installed in the column driver 85 in detail.

Referring to FIG. 9, the data / initialization voltage selection circuit of the column driver 85 is switched under the control of the timing controller 83 to alternately convert the data voltages Vcl1 to Vclm and the initialization voltage VI to the column lines CL1. Switch SW3 for supplying to CLm). The initialization voltage VI is supplied to the first input terminal of the switch SW3, and the data voltages Vcl1 to Vclm are supplied to the second input terminal of the switch SW3 through the buffer B1. The switch SW3 may be implemented as a multiplexer that selects an input terminal in response to the multiplexer control signal included in the column control signal CCS of the timing controller 83. This switch SW3 selects the second input terminal in the data supply period such as the Ta period and the initial period of the Tb period in FIG. 7 to supply the data voltages Vcl1 to Vclm to the corresponding column lines CL1 to CLm. . In addition, the switch SW3 selects the first input terminal in the initialization period such as the Tc period in FIG. 7 to supply the initialization voltage VI to the column lines CL1 to CLm. The output voltages VI, Vcl1 to Vclm of the switch SW3 are supplied to the column lines CL1 to CLm through the output buffer B2.

10 to 13 illustrate an organic light emitting display device and a method and apparatus for driving the same according to a second embodiment of the present invention.

10 and 11, an organic light emitting display device according to a second exemplary embodiment of the present invention includes m column lines CL1 to CLm and n + 1 row lines RL0, RL1 to RLn orthogonal to each other. And m × n pixels ((1,1) to (m, n)) in a matrix type in the pixel area between the column lines CL1 to CLm and the row lines RL0 to RLn. And diodes D11 connected in series to each of the column lines CL1 to CLm.

Each of the pixels (1,1) to (m, n) may include a first switch TFT SW11 formed at an intersection of the column lines CL1 to CLm and the Nth row line RL (N). And a driving TFT DRV formed between the cell driving voltage source VDD and the electroluminescent cell OLED to drive the electroluminescent cell OLED, and between the first switch TFT SW1 and the driving TFT DRV_TFT. A second capacitor for supplying the connected capacitor Cst and the initialization voltage VI on the initial voltage line VIL to the capacitor Cst in response to the voltage on the N-th low line RL (N-1). The switch TFT SW12 is provided. The switch TFTs SW11 and SW12, the driving TFT DRV and the diode D11 are implemented with a P type MOS-FET.

The source terminal of the diode TFT D11 is connected to the output terminal of a column driver (not shown). The drain terminal and the gate terminal of this TFT D11 are shorted on the column lines CL1 to CLm. The diode D11 has the same threshold voltage Vth as the driving TFT DRV to compensate for the data voltage Vcl supplied to the column lines CL1 to CLm by the threshold voltage Vth of the driving TFT DRV. Done.

On the other hand, when the TFTs on the polysilicon substrate are directly formed, the TFTs in the vertical direction are generally formed in the same domain region and thus have the same characteristics. For this reason, the diodes D11 connected to the column lines CL1 to CLm one by one are vertical pixels such as (1,1), (1,2), (1,3), ..., (1, n- 1), the threshold voltage of the driving TFT DRV provided in each of the pixels of (1, n) can be compensated uniformly.

The source terminal of the first switch TFT SW11 is connected to the column lines CL1 to CLm, and the drain terminal is connected to the drain terminal of the second switch TFT SW12, the capacitor Cst and the gate terminal of the driving TFT DRV. Connected. The gate terminal of the first switch TFT SW11 is connected to the Nth low line RL (N). The first switch TFT SW11 is turned on in response to the negative scan voltage from the Nth low line RL (N) to conduct a current path between its source terminal and the drain terminal, as well as the Nth The OFF state is maintained when the voltage on the low line RL (N) is less than or equal to its threshold voltage. In the on-time period of the switch TFT SW11, the data voltage Vcl from the column lines CL1 to CLm is connected to the capacitor Cst and the driving TFT via the source terminal and the drain terminal of the first switch TFT SW11. Is applied to the gate terminal of (DRV). On the contrary, in the off-time period of the first switch TFT SW11, the current path between the source terminal and the drain terminal of the first switch TFT SW11 is opened so that the data voltage Vcl is applied to the capacitor Cst and the driving TFT DRV. Not applied).

The source terminal of the driving TFT DRV is connected to the common voltage line VDDL, and is connected to one terminal of the capacitor Cst, and the drain terminal is connected to the anode electrode of the electroluminescent cell OLED. The gate terminal of the driving TFT DRV is connected to the capacitor Cst and the drain terminals of the first and second switch TFTs SW11 and SW12. The driving TFT DRV adjusts the current between its source terminal and the drain terminal in response to the gate voltage Vcl-Vth supplied to its gate terminal, thereby electroluminescent at a brightness corresponding to the gate voltage Vcl-Vth. The cell OLED is made to emit light. The gate voltage Vcl-Vth of the driving TFT DRV is a voltage subtracted by the threshold voltage Vth of the diode D11 from the data voltage Vcl from the column lines CL1 to CLm.

The capacitor Cst is initialized by charging the negative initialization voltage VI supplied from the second switch TFT SW12 in advance before the scan voltage is supplied to the N-th low line RL (N). Initializing the capacitor Cst is driven before the data voltage Vcl is supplied so that the data voltages Vcl-Vth on the column lines CL1 to CLm can be supplied to the gate terminal of the driving TFT DRV. This is to charge the voltage of the gate terminal of the TFT DRV to a voltage lower than the voltage on the column lines CL1 to CLm. In other words, the capacitor Cst is initialized by supplying a voltage lower than the threshold voltage Vth of the diode D1 for a predetermined period before the data voltage Vcl is supplied. After the capacitor Cst is initialized and the data voltage Vcl is applied, the capacitor Cst stores the difference voltage between the gate voltage Vcl-Vth and the cell driving voltage VDD of the driving TFT DRV. The gate voltage Vcl-Vth of the driving TFT DRV is kept constant for one frame period, and the current applied to the electroluminescent cell OLED is kept constant for one frame period.

The source terminal of the second switch TFT SW12 is connected to the initial voltage line VIL, and the drain terminal is connected to the gate terminal of the diode D1, the capacitor Cst, and the driving TFT DRV. The gate terminal of the second switch TFT SW12 is connected to the N-1th low line RL (N-1). The second switch TFT SW12 is formed by the voltage on the N-1 th low line RL (N-1) before the voltage Vcl-Vth on the column lines CL1 to CLm is supplied to the capacitor Cst. The capacitor Cst is initialized by being turned on to supply the initialization voltage VI on the initial voltage line VIL to the capacitor Cst.

FIG. 12 illustrates a scan voltage and a data voltage applied to the organic light emitting display device illustrated in FIGS. 10 and 11.

Referring to FIG. 12, a negative dummy scan voltage is applied to the uppermost dummy row line RL0 during a Ta period. In this case, the pixels included in the first scan line ((1,1), (2,1) ... (m-1,1), (m) in response to the negative voltage on the dummy low line RL0. The second switch TFT SW12 of (1) is turned on to supply the initialization voltage VI on the initial voltage line VIL to the capacitor Cst and the driving TFT DRV. Meanwhile, additional dummy data may be supplied to the column lines CL1 to CLm within the Ta period.

During the Tb period, a negative scan voltage is applied to the first low line RL1 and a data voltage Vcl-Vth lowered by the threshold voltage Vth of the diode D11 is supplied to the column lines CL1 to CLm. do. In this case, in response to the negative voltage on the first row line RL1, the pixels ((1,1), (2,1) ... (m-1,1), ( m (1,2), (1,2), (2,2) ... (m-1,2) included in the second scan line while the first switch TFT SW11 of m, 1) is turned on. The second switch TFT SW12 of, (m, 2) is turned on. Further, during the Tb period, the voltage on the dummy low line RL0 is inverted to a high logic voltage so that the pixels ((1,1), (2,1) ... (m-1,1) included in the first scan line are inverted. ), (m, 1) turns off the second switch TFT (SW12). Therefore, the capacitor Cst and the driving of the pixels ((1,1), (2,1) ... (m-1,1), (m, 1)) included in the first scan line during the Tb period. The TFT DRV is supplied with the data voltages Vcl-Vth whose threshold voltages are compensated by the diode D11 to emit light of the electroluminescent cell OLED, and the pixels included in the second scan line ((1, 2), (2, 2) ... The capacitor Cst of (m-1, 2), (m, 2) charges the initialization voltage VI supplied via the second switch TFT SW12. Is initialized.

As a result, the organic light emitting diode according to the second embodiment of the present invention compensates the voltage supplied through the diode D11 on the column lines CL1 to CLm by the threshold voltage of the driving TFT DRV. In order to compensate the compensated voltage to be supplied to the driving TFT DRV and the capacitor Cst, the capacitor of the scan line to be currently scanned is initialized when scanning the N−1 th line corresponding to the previous scan line.

In the organic light emitting diode according to the second embodiment of the present invention, as described above, the diode D11 is installed to be connected to the column lines CL1 to CLm, and the driving TFT DRV is formed using the threshold voltage of the diode D11. By compensating the threshold voltage of the N), the current I _OLED of the electroluminescent cell OLED due to the threshold voltage of the driving TFT DRV is prevented. The current I _OLED supplied to the electroluminescent cell OLED is shown in Equation 2.

13 shows a driving apparatus for driving an organic light emitting display device according to a second embodiment of the present invention.

Referring to FIG. 13, an apparatus for driving an organic light emitting display device according to a second embodiment of the present invention includes an interface unit 132 that receives data and a synchronization signal from a video signal generator 131, and m column lines ( N + 1 row lines RL0 to RLn, which are connected to CL1 to CLm and the diode D11, intersect, and m × in the pixel region between the column lines CL1 to CLm and the row lines RL0 to RLn. An organic light emitting panel 136 in which n pixels are arranged in a matrix form, a column driver 135 for supplying data to column lines CL1 to CLm of the organic light emitting panel 136, and an organic light emitting display A low driver 137 for supplying scan pulses to the row lines RL0 to RLn of the panel 136, and a gamma voltage generator 134 for supplying a gamma voltage Vγ to the column driver 135. A timing controller 133 for controlling the color driver 135 and the low driver 137, Board and a power generation unit 138 for generating a driver (135 137) and the driving voltage and the cell voltage required for driving the timing controller (133) (VDD), and the initialization voltage (VI).

The organic light emitting panel 136 includes an electroluminescent cell (OLED) in which an anode electrode, a hole injection layer, a light emitting layer, and an electron injection layer are stacked, first and second switches SW1 and SW2, a capacitor Cst, and a driving TFT ( M × n pixels including DRV and the like are formed on the glass substrate, and a diode D11 is formed on each column line CL1 to CLm between the column driver 135 and the pixels.

The video signal generator 131 converts analog data from an input line (not shown) into digital data and supplies vertical and horizontal synchronization signals and clock signals to the interface unit 132.

The interface unit 132 uses a low voltage differential signaling (LVDS) method, a transition minimized differential signaling (TMDS) method, an RSDS method, and the like to synchronize data together with the data RGB from the video signal generator 131. The control signal TCS including the HV and the clock signal is supplied to the timing controller 133.

The timing controller 133 generates the column control signal CCS, and samples the data RGB from the interface unit 133 according to the control signal TCS, and the data RGB together with the column control signal CCS. Supply to the column driver 135. The column control signal CCS includes a shift clock, a latch signal, a multiplexer control signal, and the like of the column driver 135. In addition, the timing controller 133 generates a row control signal RCS including a start pulse for instructing the shift register to start operation, a shift clock of the shift register, and the like, and transmits the row control signal RCS to the low driver 137. Will be supplied.

The gamma voltage generator 134 divides the high potential common voltage and the low potential common voltage supplied from the power generator 138 to generate a gamma voltage Vγ corresponding to each gray level of the data, and the gamma voltage Vγ. ) Is supplied to the column driver 135.

The column driver 135 supplies the data RGB to the column lines CL1 to CLm in response to the column control signal CCS supplied from the timing controller 133. After sampling the data RGB from the timing controller 133, the column driver 135 latches the data, and then decodes the latched data to convert the gamma voltage Vγ corresponding to the data value into a data voltage ( Vcl). The data voltage Vcl generated from the column driver 85 is simultaneously supplied to the column lines CL1 to CLm in synchronization with the scan pulse generated from the low driver 137.

The row driver 137 generates scan pulses falling to the negative scan voltage in response to the row control signal RCS supplied from the timing controller 133, and the scan pulses are output to the low line of the organic light emitting panel 136. To RL0 to RLn sequentially. The low driver 137 includes a shift register that sequentially generates negative scan pulses, and a level shifter for shifting the swing width of the scan voltage to a level suitable for driving the switch TFTs SW11 and SW12.

The power generator 138 generates a high potential common voltage and a low potential common voltage, supplies the common voltages to the gamma voltage generator 134, and supplies an integrated circuit (IC) of the column driver 135. The driving voltage, the initialization voltage VI, and the cell driving voltage VDD are generated and the voltages are supplied to the column driver 135. In addition, the power generator 138 generates a negative scan voltage and supplies the scan voltage to the low driver 137.

14 illustrates an organic light emitting display device according to a third exemplary embodiment of the present invention.

Referring to FIG. 14, each pixel of the organic light emitting diode according to the third exemplary embodiment of the present invention is formed at an intersection of the Nth row line RL (N) and the column lines CL1 to CLm. The TFT SW31, the second switch TFT SW32 formed at the intersection of the N-1th low line RL (N-1) and the column lines CL1 to CLm, and the electroluminescent cell OLED A drive TFT (DRV) for driving, a capacitor (Cst) connected between the drive TFT (DRV) and the common voltage line (VDDL) and a drive connected between the first switch TFT (SW31) and the drive TFT (DRV). A diode D31 for compensating the threshold voltage of the TFT DRV, and a third switch TFT SW33 for cutting off the current supplied to the electroluminescent cell OLED during the initialization period of the capacitor Cst are provided. The first and second switch TFTs SW31 and 32, the diode D31 and the driving TFT DRV are implemented with a P type MOS-FET, and the third switch TFT SW33 is implemented with an N type MOS-FET.

The source terminal of the first switch TFT SW31 is connected to the column lines CL1 to CLm, and the drain terminal is connected to the diode D31 via the first node n1. The gate terminal of the first switch TFT SW31 is connected to the Nth low line RL (N). The first switch TFT SW31 is turned on in response to the negative scan voltage from the Nth low line RL (N) to conduct a current path between its source terminal and the drain terminal, as well as the Nth The OFF state is maintained when the voltage on the low line RL (N) is less than or equal to its threshold voltage. In the on-time period of the switch TFT SW31, the data voltage Vcl from the column lines CL1 to CLm is applied to the diode D31 via the source terminal and the drain terminal of the first switch TFT SW31. . On the contrary, in the off time period of the first switch TFT SW31, the current path between the source terminal and the drain terminal of the first switch TFT SW31 is opened so that the data voltage Vcl is not applied to the diode D31.

The source terminal of the second switch TFT SW32 is connected to the column lines CL1 to CLm, and the drain terminal of the second switch TFT SW32 is connected to the diode D31, the capacitor Cst, and the driving TFT DRV via the second node n2. Connected. The gate terminal of the second switch TFT SW32 is connected to the N-1th low line RL (N-1). The second switch TFT SW32 is turned on by the voltage on the N-1 th low line RL (N-1) before the data voltage Vcl is supplied to the capacitor Cst, and thus the column lines CL1 through. The capacitor Cst is initialized by supplying the initialization voltage VI on CLm to the capacitor Cst.

The source terminal of the driving TFT DRV is connected to the common voltage line VDDL, and is connected to one terminal of the capacitor Cst, and the drain terminal is connected to the anode electrode of the electroluminescent cell OLED. The gate terminal of the driving TFT DRV is connected to the drain terminal of the diode D31, the capacitor Cst, and the second switch TFT SW32 via the second node n2. The driving TFT DRV adjusts the current between the source terminal and the drain terminal in response to the gate voltage Vcl-Vth supplied to its gate terminal, thereby adjusting the current of the electroluminescent cell at a brightness corresponding to the gate voltage Vcl-Vth. OLED). Here, the gate voltage Vcl-Vth of the driving TFT DRV is a voltage subtracted by the threshold voltage Vth of the diode D31 from the data voltage Vcl from the column lines CL1 to CLm.

The capacitor Cst is initialized by precharging the negative voltage supplied from the column lines CL1 to CLm before the scan voltage is supplied to the Nth low line RL (N). In this way, the capacitor Cst is initialized. After the data voltage Vcl is applied to the capacitor Cst, the capacitor Cst stores the difference voltage between the gate voltage Vcl-Vth and the cell driving voltage VDD of the driving TFT DRV to drive the TFT. The gate voltage Vcl-Vth of the DRV is kept constant for one frame period, and the current applied to the electroluminescent cell OLED is kept constant for one frame period.

Diode D31 is implemented with a P-type MOS TFT. The source terminal of the diode TFT D31 is connected to the drain terminal of the first switch TFT SW31 via the first node n1. The drain terminal and the gate terminal of this TFT D31 are short-circuited via the second node n2. The drain terminal and the gate terminal of the diode TFT D31 are connected to the second switch TFT SW32, the capacitor Cst, and the driving TFT DRV via the second node n2. The diode D31 has the same threshold voltage Vth as that of the driving TFT DRV to compensate for the data voltage supplied to the gate terminal of the driving TFT DRV by the threshold voltage Vth of the driving TFT DRV. .

The source terminal of the third switch TFT SW33 is connected to the drain terminal of the driving TFT DRV, and the drain terminal is connected to the anode electrode of the electroluminescent cell OLED. The gate terminal of the third switch TFT SW33 is connected to the N-1th low line RL (N-1). The third switch TFT SW33 is turned off by the negative scan voltage supplied from the N-1 th low line RL (N-1) at the time of scanning the previous line and turned on in other periods. Keep it. Accordingly, the third switch TFT SW33 opens the current path between its source terminal and the drain terminal during the scanning of the previous line, and rises above the gate voltage of the driving TFT DRV by the initialization voltage. While blocking the current supplied to the current, a current path is formed between its source terminal and the drain terminal in the period where the data voltage Vcl is supplied so that the current is supplied to the electroluminescent cell OLED.

In the pixel of the organic light emitting diode according to the third exemplary embodiment of the present invention, a third switch TFT (SW33) for blocking a current input to the electroluminescent cell (OLED) during the initialization period is added to the pixel configuration shown in FIG. It is substantially the same as the configuration. The operation of the organic light emitting display device will be described with reference to FIG. 7.

7 and 14, a negative scan voltage is applied to the uppermost dummy row line RL0 during the Ta period. In the Tc period included at the end of the Ta period, the voltage on the dummy low line RL0 maintains the negative scan voltage, and the initialization voltage VI for initializing the capacitor Cst in the column lines CL1 to CLm. Is supplied. During the Ta and Tc periods, the second switch TFT SW32 connected to the dummy low line RL0 is turned on, while the third switch TFT SW33 is turned off. The initialization voltage VI on the column lines CL1 to CLm is included in the first scan line via the second switch TFT SW32 by the second switch TFT SW32 which remains on for the period Tc. It is supplied to the second node n2 and the capacitor Cst of ((1,1), (2,1) ... (m-1, 1), (m, 1)). At the same time, the third switch TFT SW33 is turned off in response to the negative scan voltage on the dummy row line RL0 to cut off the current applied to the electroluminescent cell OLED. Meanwhile, additional dummy data may be supplied to the column lines CL1 to CLm within the Ta period.

At the time transition from the Ta period to the Tb period, the voltage on the dummy low line RL1 is inverted to a high logic voltage to include the pixels ((1,1), (2,1) ... ( The first switch TFT SW31 of m-1,1) and (m, 1) is turned off, while the third switch TFT SW33 is turned on.

During the Tb period, a negative scan voltage is applied to the first row line RL1 and data is supplied to the column lines CL1 to CLm at the same time. In this case, the pixels ((1,1), (2,1) ... (m-1,1), (m) included in the first scan line in response to the scan voltage on the first row line RL1 1), the first switch TFT SW31 is turned on to supply the data voltage Vcl to the first node n1. When the data voltage Vcl is applied in this way, the diode D31 has a voltage on the second node n2 lower by its threshold voltage Vth than the data voltage Vcl on the first node n1 by initialization. As a result, it is turned on to supply the data voltage Vcl on the first node n1 to the second node n2. At this time, the driving TFT DRV connected to the second node n2 supplies a current corresponding to the data value to the electroluminescent cell OLED by the data voltage Vcl supplied to its gate terminal. The capacitor Cst maintains the gate voltage of the driving TFT DRV. In the Tc period included in the later period of the Tb period, the voltage on the first low line RL1 maintains the negative scan voltage, and the initialization voltage VI for initializing the capacitor Cst in the column lines CL1 to CLm. ) Is supplied. Then, the initialization voltage VI on the column lines CL1 to CLm is transferred via the second switch TFT SW32 by the second switch TFT SW32 which is kept on during the Tc period included in the later period of the Tb period. The second node n2 of the pixels ((1, 2), (2, 2) ... (m-1, 2), (m, 2) included in the first scan line is supplied.

15 shows an organic light emitting display device according to a fourth embodiment of the present invention.

Referring to FIG. 15, each of the pixels of the organic light emitting diode according to the fourth embodiment of the present invention may include a diode D41 connected to the column lines CL1 to CLm, a column line CL1 to CLm, and a plurality of pixels. The first switch TFT SW41 formed at the intersection of the Nth low line RL (N) and the cell driving voltage source VDD and the electroluminescent cell OLED are driven to drive the electroluminescent cell OLED. In response to the voltage on the driving TFT (DRV), the capacitor (Cst) connected between the first switch TFT (SW1) and the driving TFT (DRV_TFT), and the N-th low line (RL (N-1)). And a third switch TFT SW43 for controlling a current path for supplying current to the electroluminescent cell OLED. The first and second switch TFTs SW41 and SW42, the driving TFT DRV and the diode D41 are implemented with a P type MOS-FET, and the third switch TFT SW43 is implemented with an N type MOS-FET.

The source terminal of the diode TFT D41 is connected to the output terminal of a column driver (not shown). The drain terminal and the gate terminal of this TFT D41 are short-circuited on the column lines CL1 to CLm. The diode D41 has the same threshold voltage Vth as that of the driving TFT DRV to compensate for the data voltage Vcl supplied to the column lines CL1 to CLm by the threshold voltage Vth of the driving TFT DRV. Done.

The source terminal of the first switch TFT SW41 is connected to the column lines CL1 to CLm, and the drain terminal is connected to the drain terminal of the second switch TFT SW42, the capacitor Cst and the gate terminal of the driving TFT DRV. Connected. The gate terminal of the first switch TFT SW41 is connected to the Nth low line RL (N). The first switch TFT SW41 is turned on in response to the negative scan voltage from the Nth low line RL (N) to conduct a current path between its source terminal and the drain terminal, and also the Nth The OFF state is maintained when the voltage on the low line RL (N) is less than or equal to its threshold voltage. In the on-time period of the switch TFT SW41, the data voltage Vcl from the column lines CL1 to CLm is connected to the capacitor Cst and the driving TFT via the source and drain terminals of the first switch TFT SW41. Is applied to the gate terminal of (DRV). On the contrary, in the off-time period of the first switch TFT SW41, the current path between the source terminal and the drain terminal of the first switch TFT SW41 is opened so that the data voltage Vcl is applied to the capacitor Cst and the driving TFT DRV. Not applied).

The source terminal of the driving TFT DRV is connected to the common voltage line VDDL, and is connected to one terminal of the capacitor Cst, and the drain terminal is connected to the source terminal of the third switch TFT SW43. The gate terminal of the driving TFT DRV is connected to the capacitor Cst and the drain terminals of the first and second switch TFTs SW41 and SW42. The driving TFT DRV adjusts the current between its source terminal and the drain terminal in response to the gate voltage Vcl-Vth supplied to its gate terminal, thereby electroluminescent at a brightness corresponding to the gate voltage Vcl-Vth. The cell OLED is made to emit light. The gate voltage Vcl-Vth of the driving TFT DRV is a voltage subtracted by the threshold voltage Vth of the diode D11 from the data voltage Vcl from the column lines CL1 to CLm.

The capacitor Cst is initialized by charging the negative initialization voltage VI supplied from the second switch TFT SW42 in advance before the scan voltage is supplied to the N-th low line RL (N). After the capacitor Cst is initialized as described above, when the data voltage Vcl is applied to the capacitor Cst, the capacitor Cst becomes the difference between the gate voltage Vcl-Vth and the cell driving voltage VDD of the driving TFT DRV. The voltage is stored to keep the gate voltage Vcl-Vth of the driving TFT DRV constant for one frame period and to maintain the current applied to the electroluminescent cell OLED for one frame period.

The source terminal of the second switch TFT SW42 is connected to the initial voltage line VIL, and the drain terminal is connected to the gate terminal of the diode D1, the capacitor Cst and the driving TFT DRV. The gate terminal of the second switch TFT SW42 is connected to the N-1 th low line RL (N-1) and the third switch TFT 43. This second switch TFT SW42 is formed by the voltage on the N-1 th low line RL (N-1) before the voltage Vcl-Vth on the column lines CL1 to CLm is supplied to the capacitor Cst. The capacitor Cst is initialized by being turned on to supply the initialization voltage VI on the initial voltage line VIL to the capacitor Cst.

The source terminal of the third switch TFT SW43 is connected to the drain terminal of the driving TFT DRV, and the drain terminal is connected to the anode electrode of the electroluminescent cell OLED. The gate terminal of the third switch TFT SW33 is connected to the N-1 th low line RL (N-1) and the gate terminal of the second switch TFT SW42. This third switch TFT SW43 is turned off by the negative scan voltage supplied from the N-1 th low line RL (N-1) at the time of scanning the previous line and turned on in other periods. Keep it. Accordingly, the third switch TFT SW43 opens the current path between its source terminal and the drain terminal during scanning of the previous line and increases the gate voltage of the driving TFT DRV by the initialization voltage. On the other hand, while blocking the current supplied to the current, a current path is formed between its source terminal and the drain terminal during the period in which the data voltage Vcl is supplied, so that the current is supplied to the electroluminescent cell OLED.

In the pixel of the organic light emitting diode according to the fourth embodiment of the present invention, a third switch TFT (SW43) for blocking a current input to the electroluminescent cell (OLED) during the initialization period is added to the pixel configuration shown in FIG. It is substantially the same as the configuration. The operation of the organic light emitting display device will be described with reference to FIG.

15 and 12, a negative dummy scan voltage is applied to the uppermost dummy row line RL0 during the Ta period. In this case, the pixels included in the first scan line ((1,1), (2,1) ... (m-1,1), (m) in response to the negative voltage on the dummy low line RL0. The second switch TFT SW42 of (1) is turned on and the third switch TFT 43 is turned off at the same time. Then, the initialization voltage VI on the initial voltage line VIL is supplied to the capacitor Cst and the driving TFT DRV via the source terminal and the drain terminal of the second switch TFT SW42, and the driving TFT DRV The current flowing toward the electroluminescent cell OLED via the source terminal and the drain terminal is blocked by the third switch TFT SW43. Meanwhile, additional dummy data may be supplied to the column lines CL1 to CLm within the Ta period.

During the Tb period, a negative scan voltage is applied to the first low line RL1 and a data voltage Vcl-Vth lowered by the threshold voltage Vth of the diode D11 is supplied to the column lines CL1 to CLm. do. In this case, in response to the negative voltage on the first row line RL1, the pixels ((1,1), (2,1) ... (m-1,1), ( m, 1)), the first switch TFT SW11 is turned on. At the same time, the second switch TFT SW12 of the pixels ((1, 2), (2, 2) ... (m-1, 2), (m, 2) included in the second scan line is turned on. The third switch TFT SW43 of the pixels ((1, 2), (2, 2) ... (m-1, 2), (m, 2) included in the second scan line is turned on. Turn off. Further, during the Tb period, the voltage on the dummy low line RL0 is inverted to a high logic voltage so that the pixels ((1,1), (2,1) ... (m-1,1) included in the first scan line are inverted. ), the second switch TFT (SW42) of (m, 1) is turned off. Therefore, the capacitor Cst and the driving of the pixels ((1,1), (2,1) ... (m-1,1), (m, 1)) included in the first scan line during the Tb period. The data voltage Vcl-Vth whose threshold voltage is compensated by the diode D41 is supplied to the TFT DRV to emit light of the electroluminescent cell OLED. During the Tb period, the capacitor Cst of the pixels ((1,2), (2,2) ... (m-1,2), (m, 2)) included in the second scan line is initialized. The third switch TFT SW43 of the pixels ((1, 2), (2, 2) ... (m-1, 2), (m, 2) included in the second scan line is turned off. As a result, the current flowing to the electroluminescent cell OLED is blocked.

As described above, the method and apparatus for driving an organic light emitting device according to the present invention provide a diode for compensating the threshold voltage of the driving TFT between the column line and the driving TFT or on the column line. Accordingly, the method and apparatus for driving an organic light emitting device according to the present invention can compensate for the threshold voltage of the driving TFT by using a diode to reduce the drop in the data voltage to maintain a high level of current applied to the electroluminescent cell. Therefore, the luminance uniformity of the organic light emitting display device can be increased. Furthermore, the method and apparatus for driving an organic light emitting display device according to the present invention can supply the data voltage stably below the threshold voltage of the diode to the capacitor before data is supplied, thereby stably supplying the data voltage, and driving TFT in the initialization period. By forming a switch element between the driving TFT and the electroluminescent cell to cut off the current flowing to the electroluminescent cell via the device, the light emission of the non-display line can be suppressed to increase the contrast.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (33)

Multiple column lines to which data is supplied, A plurality of row lines intersecting the column lines and for selecting a scan line; A cell formed in the pixel region between the column lines and the row lines; A driving transistor for controlling a current supplied to the cell in response to the data; A switch transistor for supplying data from the column lines to the driving transistor in response to a voltage on an Nth row (where N is a positive integer greater than 0) of the row lines; And a diode for compensating the threshold voltage of the driving transistor with respect to data supplied to the driving transistor. The method of claim 1, The threshold voltage of the diode is the organic light emitting device, characterized in that the same as the threshold voltage of the driving transistor. The method of claim 1, And the diode is connected to the column line. The method of claim 1, And the diode is connected between the switch transistor and the driving transistor. The method of claim 1, A driving voltage source for supplying a driving voltage to the cell; A capacitor provided between the driving transistor, the driving voltage source, and the switch transistor to charge the data; And a second switch transistor configured to control a voltage supplied to the capacitor in response to a voltage on an N−1th low line among the low lines. The method of claim 5, And a third switch transistor configured to control a current supplied to the cell in response to a voltage on an N−1th low line among the low lines. The method of claim 5, And an initialization voltage source for generating an initialization voltage different from the data. And the second switch transistor is connected between the N-1th low line and the initialization voltage source to supply an initialization voltage different from the data to the capacitor. The method of claim 6, And an initialization voltage source for generating an initialization voltage different from the data. The capacitor is initialized by charging the initialization voltage before charging the data by the control of the second switch transistor, And the third switch transistor cuts off the current supplied to the cell in the initialization period of the capacitor in response to the voltage on the N−1th low line. The method of claim 1, And the data and an initialization voltage different from the data are alternately supplied to the column line. The method of claim 6, And at least one initial voltage line formed between the initialization voltage source and the second switch transistor to supply the initialization voltage to the second switch transistor. The method according to any one of claims 7 to 10, And the initialization voltage is lower than the threshold voltage of the diode by less than the data. A cell is formed in a pixel region between a plurality of column lines for supplying data and a plurality of row lines for selecting a scan line, and a driving transistor and the column for controlling a current supplied to the cell in response to the data. A method for driving an organic light emitting display device having a switch transistor for supplying data from lines to the driving transistor, the method comprising: Compensating the data with a threshold voltage of a diode formed on a signal transmission path of data supplied to the driving transistor; And supplying the compensated data to the driving transistor. The method of claim 12, And the diode is formed on the column line. The method of claim 12, And the diode is formed between the switch transistor and the driving transistor. The method of claim 12, And a threshold voltage of the diode is the same as a threshold voltage of the driving transistor. The method of claim 12, And supplying an initialization voltage different from the data to a capacitor provided between the driving transistor and the switch transistor to initialize the capacitor. The method of claim 12, Supplying data to the driving transistor, And the data is supplied to the driving transistor after the capacitor is initialized. The method of claim 12, Alternately supplying the data with an initialization voltage different from the data to the column lines; Supplying a scan voltage synchronized with the initialization voltage to an N−1th row (where N is a positive integer greater than 0) among the row lines; And supplying a scan voltage synchronized with the data to an Nth row among the row lines. The method of claim 12, Supplying an initializing voltage different from the data to an initial voltage line; The second switch transistor connected to the N-1 th low line is supplied by supplying a scan voltage synchronized with the initialization voltage to an N-1 th low line where N is a positive integer greater than 0. Initializing a capacitor provided between the driving transistor and the switch transistor by turning on, And supplying a scan voltage synchronized with the data to an Nth row among the row lines. The method of claim 18 or 19, And the initialization voltage is lower than the data by the threshold voltage of the diode. The method of claim 18 or 19, In response to the voltage on the N-th low line, turning off a third switch transistor provided between the N-th low line, the cell, and the driving transistor to cut off a current supplied to the cell. A method of driving an organic light emitting display device comprising: A plurality of column lines and a plurality of row lines intersect with each other, and a cell disposed in the pixel area between the column lines and the row lines is formed, and a driving transistor for driving the cell in response to data and the data is driven. A display panel having a switch transistor for supplying the transistor and a diode for compensating the threshold voltage of the driving transistor; A column driver for supplying the data to the column lines; A row driver for sequentially supplying scan voltages to the row lines; And a control unit for supplying the data to the column driving unit and controlling the timing of operation of the column driving unit and the row driving unit. The method of claim 22, And a threshold voltage of the diode is equal to a threshold voltage of the driving transistor. The method of claim 22, And the diode is connected to the column line. The method of claim 22, And the diode is connected between the switch transistor and the driving transistor. The method of claim 22, The switch transistor supplies the data to the driving transistor in response to the scan voltage on the Nth row (where N is a positive integer greater than 0) of the row lines. Drive system. The method of claim 26, A driving voltage source for supplying a driving voltage to the cell; A capacitor provided between the driving transistor, the driving voltage source, and the switch transistor to charge the data; And a second switch transistor configured to control a voltage supplied to the capacitor in response to a voltage on an N−1 th low line among the low lines. The method of claim 27, And a third switch transistor configured to control a current supplied to the cell in response to the voltage on the N−1th low line. The method of claim 27, And an initialization voltage source for generating an initialization voltage different from the data. And the second switch transistor is connected between the N-1th low line and the initialization voltage source to supply an initialization voltage different from the data to the capacitor. The method of claim 28, And an initialization voltage source for generating an initialization voltage different from the data. The capacitor is initialized by charging the initialization voltage before charging the data by the control of the second switch transistor, And the third switch transistor cuts off a current supplied to the cell during an initialization period of the capacitor in response to the voltage on the N−1th low line. The method of claim 22, And the data and the initialization voltage different from the data are alternately supplied to the column line. The method of claim 29, The display panel, And at least one initial voltage line formed between the initialization voltage source and the second switch transistor to supply the initialization voltage to the second switch transistor. The method according to any one of claims 29 to 32, And the initialization voltage is lower than the threshold voltage of the diode by less than the data.