KR20030092932A - Apparatus for preventing data error at time two-way access in a DPRAM - Google Patents

Abstract

PURPOSE: An apparatus for preventing a data error in accessing a dual port RAM bidirectionally is provided to previously prevent the data of a relevant address from being broken when write/read or write/write is executed at the same time in the case of accessing a dual port RAM bidirectionally in a digital mobile switching system. CONSTITUTION: An access arbitration part consists of inverters(301,305,308,315,316), OR elements(302,306,312,314), flip-flops(303,304), a buffer(307), a shift register(309), and AND elements(310,311,313). The first inverter(301) inverts the phase of an inputted reset signal. The first OR element(302) executes OR operation for the output signal of the first inverter(301) and a feedback signal. The first flip-flop(303) receives the output signal of the first OR element(302) as a reset signal, and latches an inputted dual port RAM chip selection signal. The second flip-flop(304), synchronized with a supplied clock, latches and outputs a busy signal inputted to a data block. The second OR element(306) executes OR operation for the output signal of the second inverter(305) and the output signal of the first flip-flop(303). The buffer(307) buffers the output signal of the second OR element(306) and outputs it as a dual port RAM chip selection signal. The third inverter(308) inverts the phase of the output signal of the second OR element(306). The shift register(309) sequentially shifts the output signals of the third inverter(308) and outputs them as the first through the eighth signal. The first AND element(310) executes AND operation for the first through the third output signal among the output signals of the shift register(309). The second AND element(311) executes AND operation for the first through the fourth output signal among the output signals of the shift register(309). The third OR element(312) executes OR operation for the output signals of the first and second AND elements(310,311). The third AND element(313) executes AND operation for the output signal of the second AND element(311) and the fifth output signal among the output signals of the shift register(309) and outputs the result signal as a feedback signal. The OR element(314) executes OR operation for the output signal of the third AND element(313) and the output signal of the first OR element(302) and outputs the result signal as a control signal to the shift register(309). The fourth and fifth inverters(315,316) respectively invert the phases of the output signals of the third OR element(312) and output them as access end signals.

Description

Apparatus for preventing data error at time two-way access in a DPRAM}

The present invention relates to a data error prevention device for bidirectional access of dual port RAM (DPRAM), and particularly, to write / read (WRITE / READ) or write / write for bidirectional access of dual port RAM in a digital mobile communication switch. At the same time, the present invention relates to a data error prevention device for bidirectional access of a dual port RAM, which prevents an error in which data at a corresponding address is broken.

Normal. Dual-Port RAM (DPRAM) is a bidirectional access memory that allows simultaneous writing and reading. That is, recording / reading or recording / recording is possible in both directions.

1 is a view for explaining a conventional dual port RAM access method.

Here, reference numeral 10 denotes a dual port RAM, A_Interrupt denotes an interrupt signal transmitted to the A side, and A_Address indicates data to be written or read data in a specific area of the dual port RAM 10 on the A side. The A_Data represents the data corresponding to the address, the A_CS represents the A side chip select signal, the A_R / W represents the A side write / read, and the B_Interrupt is transmitted to the B side. Indicates an interrupt signal, and B_Address indicates an address indicating the specific area when data is written to or read from a specific area of the dual port RAM 10 on the B side, and B_Data indicates data corresponding to the address. B_CS represents the B side chip select signal, and B_R / W represents the B side write / read.

That is, after recording data necessary for a specific area of the dual port RAM 10 and informing the counterpart to communicate, data to be transmitted as an interrupt is recorded in the dual port RAM 10.

This method does not have a problem such as data loss in communication with each other, but it informs by interrupt. Therefore, when the CPU is heavily used, it increases the load of the CPU and causes interruption. There was this.

In addition, another access method of the conventional dual port RAM is a method of viewing and accessing a state of a state register before accessing a specific area, that is, a state register. In this case, there is a disadvantage in that a periodic scanning routine must be executed on one side.

Accordingly, the present invention has been proposed to solve various problems occurring in the simultaneous access of the conventional dual port RAM,

SUMMARY OF THE INVENTION An object of the present invention is to provide a dual port that prevents an error in which data at a corresponding address is broken when WRITE / READ or WRITE / READ is simultaneously performed during bidirectional access of a dual port RAM in a digital mobile communication exchange. The present invention provides a device for preventing data error during RAM bidirectional access.

According to the present invention for achieving the above object, "dual port RAM bidirectional data error prevention device",

BUSY signal of the dual port RAM is used to extend the TA (Terminal Acknowledge) until the access cycle of the preferred side is finished, and then execute the opposite cycle to complete when the cycle of the preferred side is finished. do.

1 is a view for explaining a conventional DPRAM access method,

2 is a block diagram showing the configuration of an apparatus for preventing data error during bidirectional access of a dual port RAM according to the present invention;

FIG. 3 is a circuit diagram illustrating an embodiment configuration of the first and second arbitration units of FIG. 2;

4 is a timing diagram of the first and second arbitration units of FIG. 2.

<Explanation of symbols for the main parts of the drawings>

100 ..... Dual Port Ram

210, 220 ..... First and second access arbitration unit

301, 305, 308, 315, 316 ..... First to fifth inverters

302, 306, 312, 314 ..... 1st to 4th logic element

303, 304 ..... First and second flip-flops

307 ..... Buffer

309 ..... Shift register

310, 311, 313 ..... 1st to 3rd AND

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above.

2 is a block diagram illustrating a configuration of an apparatus for preventing data error during bidirectional access of a dual port RAM according to the present invention.

As shown in the figure, the dual port RAM 100 and the respective ports connected to both ends of the dual port RAM 100 are prioritized by using a busy signal of the corresponding side output from the dual port RAM 100. It comprises a first and second access arbitration unit 210 (220) which extends the terminal acknowledgment (TA) signal until the side's access cycle ends and mediates the opposite cycle upon completion of the preferred side's cycle.

Referring to the operation of the data error protection device in the bidirectional access of the dual port RAM according to the present invention configured as described above are as follows.

First, the dual port RAM 100 transmits a BUSY signal to the other side according to which side has first started access, thereby preventing data errors occurring at the same time.

For example, the A side and the B side access the dual port RAM 100 at about the same time, but in terms of timing, the A side first accesses the dual port RAM 100 and then the B side accesses the dual port RAM 100. In this case, in this case, B_BUSY on the B side asserts active low, and the second access arbitration unit 220 transmits the B_TA signal to the B side central processing unit for control (disable the B_CS signal). , Wait for the B_BUSY signal to be disabled).

In addition, when access to the dual port RAM 100 on the A side is completed, B_BUSY is segmented, and this signal drives the B_CS signal pre-asserted by the B side central processing unit (CPU) to the dual port RAM 100.

In addition, the B side access is terminated by activating a TA signal informing the CPU of the end of the dual port RAM 100 access cycle.

FIG. 3 is a circuit diagram illustrating an exemplary embodiment of the first and second access arbitration units 210 and 220 of FIG. 2.

FIG. 3 illustrates an embodiment of an access arbitration unit, and includes a first inverter 301 for phase inverting an input reset signal RESET_ and a first logic for ORing an output signal and a feedback signal of the first inverter 301. A first flip-flop that receives the logic sum element 302 and the output signal of the first logic sum element 302 as a reset signal, and latches the dual port RAM chip select signal DPRAMCS input in synchronization with a supplied clock; 303 and a second flip-flop 304 which receives an output signal of the first logical sum element 302 as a control signal and latches and outputs a busy signal LDBSY inputted to a data terminal in synchronization with a supplied clock. And a second inverter 305 for inverting the output signal of the second flip-flop 304, the output signal of the second inverter 305, and the output signal of the first flip-flop 303. The dual logic element 306 and the output signal of the second logic element 306 are buffered to form a dual port. A buffer 307 for outputting the tram chip select signal DP_CS, a third inverter 308 for phase reversing the output signal of the second logic element 306, and an output signal of the third inverter 308 A shift register 309 for sequentially shifting and outputting the first to eighth signals, a first logical element 310 for ANDing the first to third output signals among the output signals of the shift register 309, Logically sum the second logical multiplier element 311 which ANDs the first to fourth output signals among the output signals of the shift register 309 and the output signals of the first and second logical multiplication elements 310 and 311. And a third logical AND of the second logical signal 312, the output signal of the second logical element 311 and the fifth output signal of the output signal of the shift register 309, and outputting the resultant signal as a feedback signal. The logical AND element 313, the output signal of the third logical AND element 313, and the first logical OR element 3. The fourth logical sum element 314 and the third logic sum element 312, which perform a logical sum of the output signal of 02 and supply the result signal as a control signal to the shift register 309, respectively, are phase-inverted and accessed. The fourth and fifth inverters 315 and 316 output as the end signals DSACK0 and DSACK1.

An embodiment of the access arbitration unit configured as described above will be described in detail with reference to FIG. 4.

First, the reset signal RESET_ input from the first inverter 301 at the same timing as that of FIG. 4B is inverted and transferred to the first logic element 302.

The first logical sum element 302 logically sums the output signal of the first inverter 301 and the feedback signal and outputs the result signal. The first flip-flop 303 outputs the first logical sum element 302. The signal is input as a reset signal, and the dual port RAM chip select signal DPRAMCS inputted at the timing as shown in FIG. 4D is synchronized with the supplied clock to output the latched signal.

In addition, the second flip-flop 304 receives the output signal of the first logic element 302 as a control signal and latches and outputs the busy signal LDBSY inputted at the timing as shown in FIG. 4F in synchronization with the supplied clock. Done.

In addition, the second inverter 305 phase inverts the output signal of the second flip-flop 304, and the second logic element 306 outputs the output signal of the second inverter 305 and the first flip-flop ( The output signal of 303 is logically summed and output.

The buffer 307 buffers the output signal of the second logic element 306 to output the dual port RAM chip selection signal DP_CS as shown in FIG. 4E.

Next, the third inverter 308 phase-inverts the output signal of the second logic element 306, and the shift register 309 sequentially shifts the output signal of the third inverter 308 to form the first to the first to third ones. The eighth signal is output.

In addition, the first logical element 310 is logically multiplied by the first to third output signal of the output signal of the shift register 309, the second logical element 311 is output of the shift register 309 The first to fourth output signals of the signals are ANDed.

The second logical sum element 312 may OR the output signals of the first and second logical multiplication elements 310 and 311, and the third logical sum element 313 may be the second logical sum element 311. The output signal of and the fifth output signal of the output signal of the shift register 309 is ANDed, and the resulting signal is transmitted to the first logical sum element 302 and the fourth logical sum element 314 as a feedback signal, respectively.

The fourth logical sum element 314 combines the output signal of the third logical sum element 313 and the output signal of the first logic sum element 302 and converts the result signal into a control signal to the shift register 309. Will be supplied.

In addition, the fourth and fifth inverters 315 and 316 phase-invert the output signals of the third logical sum device 312, respectively, and output them as the access termination signals DSACK0 and DSACK1.

In other words, if the A side and the B side accessed the dual port RAM at about the same time, but the A side first accessed the dual port RAM and then the B side accessed the dual port RAM, in this case, B_BUSY is asserted active low, and the second access arbitration unit 220 transmits the B_TA signal to the B-side central processing unit for control (disables the B_CS signal and waits for the B_BUSY signal to be disabled). .

In addition, when access to the dual port RAM 100 on the A side is completed, B_BUSY is segmented, and this signal drives the B_CS signal pre-asserted by the B side central processing unit (CPU) to the dual port RAM 100.

In addition, the B side access is terminated by activating a TA signal informing the CPU of the end of the dual port RAM 100 access cycle.

According to the present invention described above, even when the write / read (WRITE / READ) or write / write at the same time when the dual port RAM bidirectional access in the digital mobile communication switch to prevent the error of the data of the address is broken in advance. There is an advantage to this.

Claims (2)

In a dual port RAM (DPRAM) bidirectional access device in a digital mobile communication switch, The terminal acknowledgment (TA) signal is extended until the access cycle of the preferred side is terminated by using the busy signal of the corresponding side connected to both ends of the dual port RAM and outputted from the dual port RAM. And a first and second access arbitration unit for arbitrating the control signal to execute the opposite cycle when the cycle of the side is finished. The method of claim 1, wherein the first and second access arbitration unit, A first inverter 301 for phase inverting the input reset signal RESET_, a first logical sum device 302 for ORing the output signal and the feedback signal of the first inverter 301, and the first logical sum device A first flip-flop 303 for receiving the output signal of the input signal 302 as a reset signal and latching the dual port RAM chip selection signal DPRAMCS inputted in synchronization with a supplied clock; and the first logic element 302. A second flip-flop 304 and a second flip-flop 304 for latching and outputting a busy signal LDBSY inputted to a data terminal in synchronization with a supplied clock. A second inverter 305 for inverting the phase of the signal, a second logical sum device 306 for ORing the output signal of the second inverter 305 and the output signal of the first flip-flop 303, and the second A buffer 307 for buffering the output signal of the logic element 306 and outputting the dual port RAM chip selection signal DP_CS. And a third inverter 308 for phase inverting the output signal of the second logic element 306 and a shift for sequentially outputting the output signal of the third inverter 308 as the first to eighth signals. A first logical element 310 which logically multiplies the register 309, the first to third output signals of the output signal of the shift register 309, and the first to fourth of the output signals of the shift register 309; A second logical multiplication element 311 for ANDing the second output signal, a second logical sum element 312 for ORing the output signals of the first and second logical multiplication elements 310 and 311, and the second logic A third logical element 313 for ANDing the output signal of the product element 311 and the fifth output signal of the output signal of the shift register 309 and outputting the resultant signal as a feedback signal, and the third logical element The output signal of 313 and the output signal of the first logical sum element 302 are ORed together and the resultant signal is returned. A fourth logic sum element 314 for supplying a control signal to the shift register 309 and a fourth logic sum for outputting the output signals of the third logic sum element 312 as access termination signals DSACK0 and DSACK1, respectively. And fifth inverters 315 and 316, respectively.