KR20030089458A - Method for manufacturing a semiconductor device - Google Patents

Abstract

In the formation process of the gate electrode of the line width area | region in which refinement | miniaturization was improved, the photolithography process of several times is unnecessary and the manufacturing method of the thin film transistor which can enlarge the margin of patterning is provided.

According to the manufacturing method of the present invention, the mask pattern of the first layer and the mask pattern of the second layer can be formed by self-alignment and as mask patterns having different dimensions in different shapes with only one photolithography step. Can be. The line width on the active layer is set to be Li in the mask pattern of the first layer and L 'in the mask pattern of the second layer, and anisotropic etching using the mask pattern of the second layer and the mask pattern of the first layer are used. By performing anisotropic etching sequentially, a hat shape gate can be formed in self-alignment. Therefore, the number of reticles used in the manufacturing process can be reduced, and the problem of complexity of the manufacturing method due to the miniaturization of the TFT can be solved.

Description

Method for manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter, abbreviated as TFT), and more particularly, to a mask forming method in an exposure step and an etching method using the mask.

Recently, an active matrix liquid crystal display device using TFT has attracted attention. In an active matrix liquid crystal display device, TFTs are provided as switching elements in each pixel.

In general, TFTs are formed of amorphous silicon or polycrystalline silicon to form channel formation regions. In particular, a TFT using polycrystalline silicon (hereinafter referred to as a polycrystalline silicon TFT) manufactured at a temperature of 600 ° C. or lower (hereinafter referred to as a low temperature process) can be formed on a glass substrate, so that the semiconductor device can be lowered in price and large in area. do. In addition, since polycrystalline silicon has high mobility, it becomes possible to realize a liquid crystal display device in which a pixel portion and a driver are integrally formed on a glass substrate.

However, when the polycrystalline silicon TFT is continuously driven, the mobility changes, the on current (current flowing when the TFT is on) decreases, or the off current (flow when the TFT is off). Current) may increase. This may be caused by deterioration due to hot carriers generated by the high electric field near the drain.

In order to alleviate high carriers near the drain and suppress hot carriers, it is useful to use an LDD (abbreviation for Lightly Doped Drain) structure for MOS transistors having a gate line width design rule of 1.5 m or less.

For example, in the case of an NMOS transistor, it is possible to form an LDD structure by providing a low concentration n-type region (n- region) at the drain end using a side wall that is a gate sidewall. The concentration of the electric field in the vicinity of the drain can be alleviated by the LDD structure in which the impurity concentration of the drain junction is inclined.

However, the LDD structure can improve the drain breakdown voltage as compared to the single drain structure, but has a disadvantage in that the drain current decreases because the resistance of the n-region is large. In addition, there is a high field region immediately below the sidewall, where the collision ionization is maximized, and hot electrons are injected into the sidewall, so that the n-region is depleted and further increases the resistance, The TFTs deteriorate.

In particular, as the channel length is shortened, the above problem is brought about. As a MOS transistor with a design rule of 0.5 mu m or less, a gate overlap LDD structure that forms an n- region by overlapping the end of the gate electrode is useful to overcome this problem.

In addition to the MOS transistors, the adoption of the Gate Overlap LDD structure has been considered in order to alleviate the high electric field near the drain in the polycrystalline silicon TFT. The polycrystalline silicon TFT having a gate overlap LDD structure has a low concentration overlapping with the gate electrode provided between the channel forming region, the source and drain regions which are high concentration regions (n + regions), and the channel forming region and the source and drain regions in the polycrystalline silicon layer. A region (n-region) is formed.

As a method for producing these structures, there are reports such as [Patent Document 1] Japanese Unexamined Patent Publication No. 2000-349297 and [Patent Document 2] Japanese Unexamined Patent Publication No. 07-202210.

In the manufacturing process of a TFT having a gate overlap LDD structure, in order to form a low concentration region (n-region) overlapping with the gate electrode, an impurity element is added before the gate electrode is formed or the impurity element is formed to penetrate through the gate electrode. It is necessary to add.

In the former method, it is necessary to use the mask for adding an impurity element and the mask for gate electrode formation in separate exposure processes. For this reason, the gate electrode and the n- region cannot be formed in self-alignment, and the number of masks cannot be suppressed.

In the latter method, on the other hand, after the impurity is not added to the channel region, it is necessary to add the impurity element only to the n- region. Therefore, when the impurity addition to the channel region is to be prevented by using the gate electrode itself as a mask, it is necessary to concentrate the design on the shape of the gate electrode such as thickening the gate electrode only on the channel region.

However, when the impurity addition to a channel region is prevented by devising a gate electrode shape, an exposure step is generally required a plurality of times. For this reason, it is difficult to precisely control the shape of the gate electrode due to the mask shift in each exposure step, and it is not possible to form the n- region self-aligned. In addition, the number of reticles used increases and the manufacturing process becomes complicated.

In general, the larger the dimension of the resist mask, the weaker the constraints on the patterning conditions such as the depth of focus and the uniformity of the resist film thickness, so the process margin of the patterning process is increased. However, in the conventional method, since the dimensional shape of the resist mask is about the same as the design dimension of the pattern, the process margin of the patterning process decreases as the miniaturization proceeds, and it becomes difficult to manufacture the TFT.

For example, in patent document 1, the gate electrode of a two-layer structure is used, the etching process of a gate electrode is provided twice, and the 1st layer of a gate electrode is longer in a channel length direction than a 2nd layer, and is called a hat shape A method of forming a hat shape gate is disclosed. Further, Japanese Laid-Open Patent Publication No. 07-202210 discloses an example of a method of forming a hat-shaped gate by self-alignment. The first layer of the gate electrode made of titanium or titanium nitride film and the second layer of the gate electrode made of aluminum or aluminum alloy film are formed by DC sputtering. Next, the method of etching the 1st layer and the 2nd layer of a gate electrode simultaneously by an etching process, and then retracting and processing only the gate electrode of a 2nd layer by side etching is disclosed.

In addition, in the technique disclosed in Patent Literature 2, unlike a gate electrode such as polycrystalline silicon having good heat resistance, aluminum is used for the second layer of the gate electrode, so that the heat treatment at high temperature causes defects due to aluminum spikes or migration. Since this occurs, there is a problem that the temperature management of the process is very difficult. Therefore, it is necessary to activate the impurities at a temperature at which aluminum does not deteriorate. However, since the activation treatment after ion implantation or ion doping is performed at 550 to 800 ° C, it is difficult to completely perform the activation treatment of impurities at a temperature lower than that. In addition, aluminum has a problem that it is susceptible to mechanical damage because it is recrystallized at low temperature and the surface is uneven or soft metal.

For the above reasons, it was difficult to manufacture a TFT having a Gate Overlap LDD structure with a design rule of about 1 to 2 m in channel length and 0.5 m or less in overlap width with the gate electrode in the LDD region. That is, the conventional method of manufacturing a gate overlap LDD structure,

1) A plurality of photolithography steps are required.

2) As refinement proceeds, the process margin of the patterning process decreases and manufacturing becomes more difficult.

3) In the method of manufacturing a hat-shaped gate electrode by one-time patterning as in the invention described in JP-A 07-202210, the second layer of the gate electrode is limited to an aluminum film or an aluminum alloy film. It has various problems such as being undesirable.

This invention makes it a subject to solve the said problem. Specifically, in the process of manufacturing a TFT having a gate overlap LDD structure, it is a problem to suppress the number of photolithography processes at the time of forming a gate electrode and to provide a technique capable of manufacturing the TFT with high precision even if the design rule is miniaturized. Shall be.

1 is a view showing a method of manufacturing a gate overlap LDD structure TFT according to the present invention;

2 is a diagram showing a method for manufacturing a TFT having only an Loff region according to the present invention;

3 is a diagram illustrating a method of manufacturing a CMOS circuit according to the present invention.

Fig. 4 is a diagram showing a first method of mixing and manufacturing a gate overlap LDD structure TFT and a single drain structure TFT according to the present invention.

FIG. 5 is a diagram showing a second method of mixing and manufacturing a gate overlap LDD structure TFT and a single drain structure TFT according to the present invention;

Fig. 6 is a view showing a manufacturing method of mixing and manufacturing a Gate Overlap LDD structure TFT having different Lov according to the present invention.

7 is a diagram showing a manufacturing method of a TFT having only an Loff region according to the present embodiment,

8 is a diagram illustrating a mask formation process;

9 is a diagram showing a gate forming step,

FIG. 10 is a diagram illustrating anisotropic dry etching treatment of only the second layer gate electrode film using the hard mask as a mask;

11 is a diagram illustrating a method of manufacturing a TFT array substrate,

12 is a diagram illustrating a state in which a TFT array substrate and an opposing substrate overlap with each other.

It is a figure which shows the top view of a liquid crystal panel.

In the process of enhanced miniaturization, it is necessary to solve the problems such as the necessity of multiple photolithography process, the reduction of patterning margin, and the reduction of the choice of gate material by forming the Gate Overlap LDD structure by self-alignment. It describes about a means.

In addition, in the present specification, in order to clearly explain a manufacturing method of a gate overlap LDD structure or the like, the following definitions are provided. A region not overlapping with the gate electrode in the LDD region is defined as a "Loff region", and a region overlapping with the gate electrode among the LDD regions is defined as a "Lov region". The length of the Loff region is defined as "Loff", the length of the Lov region is "Lov", and the length of the channel region is defined as "Li". In the present specification, unless otherwise specified, Lov regions corresponding to Lov are present on both sides of the channel region, and the length of the region where the channel region and the Lov region are combined, that is, the entire gate electrode on the active layer. The width "L '" is defined as "L' = Li + Lov x 2".

In the etching step or the doping step in the case of manufacturing the LSI or the TFT, a pretreatment for forming a protective film on a portion which is not usually subjected to an etching process or a doping process is performed. The protective film is generally formed by patterning, for example, projecting a pattern of a photomask onto a substrate coated with a photoresist. Therefore, in the following description, this protective film is defined as "mask" and the photomask is defined as "reticle". Moreover, you may form a mask using materials other than a photoresist. In addition, the mask formed using the photoresist as a material is defined as a "hard mask", and the mask formed using materials other than a photoresist is called a "hard mask."

As a means of solving the said subject, this invention forms the mask pattern of a two-layer structure, and uses this to manufacture a hat-shaped gate itself by self-alignment.

The main structure of this invention is a mask pattern formation process and a gate formation process, and a mask formation process and a gate formation process are demonstrated in detail below. Here, in order to distinguish each mask, the following definition is provided. The mask which covers the area which combined the channel formation area | region and Lov area | region used when forming a Gate Overlap LDD structure is defined as a "Gate Overlap LDD gate mask." When thinning the gate electrode on the Lov region, the mask covering the channel region is defined as a "channel mask." The channel mask is also used when forming the gate of the transistor having the Loff region. In the case of forming the Gate Overlap LDD structure, an etching for completely removing the gate material of the portion not covered by the Gate Overlap LDD gate mask and an etching for thinning the gate electrode on the Lov region using the channel mask are required. The former is defined as "Gate Overlap LDD gate etching" and the latter as "Lov region etching".

The mask formation process is shown to FIG. 8 (A). The active layer 809 is formed on the substrate 808, and the first layer gate electrode film 811a and the second layer gate electrode film 811b are formed with the gate insulating film 810 interposed therebetween. Subsequently, as a preparation of mask formation, the layer used as a material of a mask is formed. Since the normal mask formation step is only to form a resist mask by patterning, only the resist is applied. In FIG. 8, the hard mask layer 812 is formed in contact with the second layer gate electrode film 811b. Then, the resist 813 is apply | coated in contact with a hard mask layer.

FIG. 8B shows the process of forming the resist mask 815 and the hard mask 814, and after the resist mask 815 is formed by normal patterning, isotropy represented by wet etching. The hard mask (A1) 814 is formed by etching. In Fig. 8B, the upper resist mask 815 is formed as a Gate Overlap LDD gate mask by normal patterning. The lower hard mask 814 is formed as a channel mask by isotropic etching represented by wet etching using an upper resist mask. In addition, in the isotropic etching, the retraction amount (side etching amount) of the hard mask with respect to the resist mask, that is, Lov can be controlled by the thickness of the hard mask layer. When the Lov is large, the hard mask layer is formed thick, and when the Lov is small, the hard mask layer may be thin. Alternatively, the amount of retreat can be controlled by making the thickness of the hard mask layer constant and controlling the over etching time. In the case of forming by wet etching, it is not necessary to consider problems such as corrosion and defects in which a film remains during hard mask formation.

The material of this hard mask can freely select a material satisfying two conditions: an isotropic etching with a high selectivity between the gate electrode and a selectivity high enough to be used as a mask in the Lov region etching. If side etching is essential at the time of etching using a hard mask, it is necessary to remove the hard mask after etching since voids are necessarily formed under the hard mask, which may cause trouble in subsequent steps. However, in the present invention, as described later in the description of the gate forming step, side etching at the time of etching using a hard mask is not essential. Therefore, in this invention, the process of removing a hard mask after an etching is not necessarily essential. In the process of removing the hard mask after etching, when the gate insulating film is shaved during the removal of the hard mask, a condition is added that the etching of the gate insulating film and the high selectivity is possible with respect to the hard mask material. In the present invention, since the process can be left without removing the hard mask, the choice of hard mask material is widened. As a process of leaving a hard mask without removing it, the process of selecting a silicon oxide film as a hard mask material, and leaving a hard mask as a part of an interlayer insulation film is mentioned, for example. When a high melting point metal is selected as the hard mask material, it is also possible to leave the hard mask as part of the gate electrode.

In this way, the mask pattern of the 1st layer (pattern of a hard mask) is self-aligned with respect to the mask pattern (pattern of a resist mask) of a 2nd layer only by one photolithography process, and the mask pattern differs in dimension differently. It can be formed as. It is easy to set the line width on the active layer to be Li 'in the mask pattern of the first layer and L' in the mask pattern of the second layer. In the conventional method, a pattern of Li must also be produced as a resist mask. However, when the method according to the present invention is used, the line width on the active layer of the resist mask becomes Li + Lov × 2, which can be set larger than before. It is possible to cope with further miniaturization.

Moreover, even if the mask pattern of the 2nd layer which is a resist mask is peeled off, the mask pattern of the 1st layer which is a hard mask will remain. Therefore, it is possible to sequentially perform anisotropic etching using the mask pattern of the second layer and anisotropic etching using the mask pattern of the first layer. Since the mask pattern of the first layer and the mask pattern of the second layer are formed as different mask patterns having different shapes, the hat-shaped gates can be self-aligned by performing etching using these mask patterns sequentially. Can be. In this way, the number of reticles used in the manufacturing process can be reduced, and the problem of complexity of the manufacturing method accompanying the miniaturization of the TFT can be solved.

The gate forming process, which is one of the main parts of the present invention, will be described. Etching using a mask having a laminated structure composed of a resist mask 916 and a hard mask 917 is performed in two steps (see Figs. 9A and 9B). FIG. 9A shows the anisotropic dry etching process of the second layer gate electrode film 918. FIG. 9B shows the anisotropic dry etching process of the first layer gate electrode film 919. In the etching of the first step, Gate Overlap LDD gate etching is performed using a resist mask 916 corresponding to the Gate Overlap LDD gate mask. The Gate OverlapLDD gate etch is preferably a fully anisotropic etch. That is, the first layer gate electrode film 918 and the second layer gate electrode film 919 in portions not covered by the gate overlap LDD gate mask are completely removed. As a result, the first shape conductive layer 920 is formed. Thereafter, the resist mask 916 is peeled off and the hard mask 917 is exposed (FIG. 9C).

In the etching of the second step, an etching (Lov region etching) for thinning the gate electrode on the Lov region is performed using a hard mask corresponding to the channel mask. FIG. 10A illustrates anisotropic dry etching treatment of only the second layer gate electrode film 1024 using the hard mask 1023 as a mask. Thereafter, the hard mask 1023 is removed by isotropic etching represented by wet etching (see FIG. 10 (B)). As mentioned above, the 2nd shape conductive layer 1026 which is a hat-shaped gate is formed in self-alignment. Thereafter, impurities are added at high concentration to the source and drain, and impurities are added at low concentration to the Lov region.

In this manner, using a mask having a structure in which a resist mask is laminated on a hard mask as a main part of the present invention, the mask is set to be Li in a hard mask and L 'in a resist mask, and anisotropic etching and hard mask using a resist mask are performed. By sequentially performing anisotropic etching using, a hat-shaped gate can be formed in self-alignment. Therefore, the number of reticles used in the manufacturing process can be reduced, and the problem of complexity of the manufacturing method due to the miniaturization of the TFT can be solved.

In the above description, the electrically conductive film used as a gate electrode was made into the 2-layer structure of another material. Thereby, it becomes possible to make the electrically conductive film of a 1st layer (lower layer) into the etching stopper at the time of etching the electrically conductive film of a 2nd layer (upper layer). In this way, the range of selection of the conditions for etching the conductive film serving as the gate electrode can be expanded. The effect is particularly large at the time of etching the Lov region, making it possible to precisely control the gate film thickness on the Lov region, and as a result, to facilitate the control of the impurity concentration added to the Lov region in a later step.

Further, when the present invention is applied, it is possible to select a large number of combinations of the first conductive film and the second conductive film constituting the hat-shaped gate, and the second conductive film is not limited to the aluminum film. The first and second conductive films may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy material or compound material containing the element as a main component. Further, a semiconductor film represented by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of a Cu film. Also good. Since a high melting point metal can be selected as the gate material, it is possible to perform activation of impurities by ordinary heat treatment (550 to 800 ° C).

However, forming the gate electrode film in two layers is not a necessary condition. If the Lov region etching is precisely controlled, the gate electrode film can be constituted by a single layer film. Even when the gate electrode film is formed of a single layer film, the hat-shaped gate can be formed by the application of the present invention.

Typical values are Li = 1.0 to 2.0 µm and Lov = 0.25 to 0.5 µm. However, it is not necessarily limited to this range.

According to the manufacturing method of the present invention, the mask (hard mask) of the first layer is self-aligned with respect to the mask (resist mask) of the second layer only as one photolithography step, and as a mask pattern having different shapes but different dimensions. Can be formed. The line width on the active layer is set to be Li in the first layer mask pattern, and Li + Loff x 2 in the second layer mask pattern, and anisotropic etching using the mask pattern of the second layer and the mask pattern of the first layer are used. By sequentially performing anisotropic etching, the TFT having only the Loff region can be formed in self alignment. Therefore, the number of reticles used in the manufacturing process can be reduced, and the problem of complexity of the manufacturing method accompanying the miniaturization of the TFT can be solved. In addition, since a single layer or a stacked conductive film serving as the material of the gate electrode can be selected without being limited to aluminum, activation of impurities can be performed by ordinary heat treatment (550 to 800 ° C).

Moreover, typical values are Li = 1.0-2.0 micrometers and Loff = 0.25-0.5 micrometer. However, it is not necessarily limited to this range. As a result, the line width on the active layer of the resist mask is not miniaturized even in the manufacturing process of the TFT having only the Loff region where the miniaturization is enhanced, and the patterning margin can be enlarged.

The hard mask may be formed by a wet etching process using a resist mask. Thereby, in the manufacturing process of TFT which has only the Loff area | region which refine | miniaturization was improved, problems, such as a nonuniformity of a film thickness, an etching spot generation, corrosion, and a defect which a film | membrane remains, can be prevented.

The p-channel TFT may have a gate overlap LDD structure, and the n-channel TFT may have a gate overlap LDD structure. Both of them may have a Gate Overlap LDD structure.

Embodiment 1

First, the embodiment of FIG. 1 relating to a method of manufacturing a gate overlap LDD structure TFT will be described. A silicon layer 102 is formed on the substrate 101, the gate insulating film 103 is deposited thereon, and then the first layer gate electrode film 104 and the second layer as the first conductive film and the second conductive film. The gate electrode film 105 is laminated. Thereafter, the hard mask layer 106 is formed. Subsequently, a resist mask 107 is formed by patterning (see Fig. 1A). Then, an isotropic etching process is performed by wet etching using the resist mask 107 to form a hard mask 106 (see FIG. 1 (B)).

Subsequently, only the second layer gate electrode film 105 is anisotropic dry etched using the resist mask 107, that is, the Gate Overlap LDD gate mask (see FIG. 1C).

Subsequently, using the resist mask 107 and the second layer gate electrode film 105 as a mask, the first layer gate electrode film 104 is anisotropic dry-etched under different conditions to form a conductive layer 110 having a first shape. ) Is formed (see FIG. 1 (D)). The resist mask 107 is peeled off to expose the hard mask 106.

Thereafter, using the hard mask 106, the second layer gate electrode film 105 is anisotropic dry etched using the first layer gate electrode film 104 as an etching stopper, and the first region is subjected to an anisotropic dry etching process. Only the layer gate electrode film 104 is left. In this way, the second shape conductive layer 111 is formed (see FIG. 1 (E)).

Subsequently, the hard mask 106 is removed by wet etching (see FIG. 1 (F)). In this way, a hat-shaped gate is formed in self-alignment. Thereafter, a high concentration of impurities is added to form a first impurity region 108 serving as a source and a drain region outside the first shape conductive layer. Thereafter, the addition of the low concentration impurity forms the second impurity region 109 overlapping the second conductive layer. The second impurity region 109 corresponds to the Lov region (see Fig. 1G).

Thereafter, the TFT is completed through an interlayer insulating film forming step, an activation step, a contact hole forming step, and a wiring forming step. These processes are not shown.

In addition, the impurity addition to the first impurity region 108 serving as the source and drain regions is performed after the conductive layer 110 having the first shape is formed (a state in which the resist mask is removed from FIG. 1 (D) or FIG. 1 (D)). It is also possible to carry on. In this case, since the first layer gate electrode film 104 and the second layer gate electrode film 105 serve as masks for the Lov region, the restriction of impurity addition conditions to the first impurity region 108 is relaxed.

Embodiment 2

In the invention described in the present embodiment, in forming a TFT having an Loff region, the laminated structure mask of the hard mask and the resist mask is formed in a self-aligned manner by wet etching so that the line width of the hard mask is made smaller than the line width of the resist mask. It is possible to enlarge the patterning margin in the process by which refinement | miniaturization was improved, It is characterized by the above-mentioned. EMBODIMENT OF THE INVENTION Embodiment which concerns on the manufacturing method of TFT which has Loff area of this invention is described below.

The following three points are added to the method for forming the gate overlap overlap LDD structure by the self-alignment described in Embodiment 1, and can be changed by the method for forming the TFT structure having only the Loff region in the self-alignment.

(Change 1) Gate Overlap An impurity addition process to the source and the drain is added between the LDD gate etching and the Lov region etching.

(Change 2) The etching condition is changed to remove not only the gate upper layer W but also the gate lower layer TaN by anisotropic etching during the Lov region etching.

(Change 3) After the Lov region etching or after removing the hard mask, an impurity addition step to the LDD is added.

Here, embodiment of FIG. 2 which concerns on the manufacturing method of TFT which has Loff area is described. Basically, the manufacturing method of FIGS. 2A to 2D, which is from the resist mask pattern process to the process of etching only the second layer gate electrode film, is the same as the invention of FIG. It describes from a process. The resist mask 207 is peeled off to expose the hard mask 206. Thereafter, impurities are added. In the present embodiment, since the first layer gate electrode film 204 is left in the source and drain regions, impurities are added through the first layer gate electrode film 204 and the gate insulating film 203. When the first layer gate electrode film 204 is removed by etching using a gate Loff mask, impurities are added only through the gate insulating film 203. However, since the Loff region is masked by the second conductive film region 205 consisting of the first layer gate electrode film 204 and the second layer gate electrode film, impurities are not added at all. As a result, only the source and drain regions become high concentration impurity regions, and the first impurity regions 208 and 209 are formed (see Fig. 2D).

After that, using the hard mask 206, only the second conductive film region 205 is anisotropic dry-etched using the first layer gate electrode film 204 as an etching stopper, and the first layer gate electrode film ( Only 204 is anisotropic dry etch. In this manner, the first layer gate electrode film 204 and the second conductive film region 205 in the Loff region are completely removed (see FIG. 2E). As a result, the conductive layer 210 of the first shape is formed.

The hard mask 206 is then removed by wet etching (see FIG. 2 (F)). Thereafter, impurities are added to the Loff region and the source and drain regions. Impurities are added through the gate insulating film. In this manner, the source and drain regions become the first impurity regions 208 and 209, which are high concentration impurity regions, and the Loff region, becomes the second impurity regions 211 and 212, which are low concentration impurity regions (see Fig. 2F). ). Thereafter, the TFT is completed through an interlayer insulating film forming step, an activation step, a contact hole forming step, and a wiring forming step. The TFT is completed through such a process. These processes are not shown. The hard mask may be removed after the addition of impurities in the Loff region.

Example 1

A method of manufacturing a complementary device in which two Gate Overlap LDD structure transistors, which is an embodiment of the present invention, in combination, a control circuit using a so-called CMOS circuit, will be described with reference to FIG.

The substrate 301 may be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Moreover, you may use what formed the insulating film in the surface of a silicon substrate, a metal substrate, or a stainless substrate. Further, a plastic substrate having heat resistance that can withstand the processing temperature of the present embodiment may be used.

Subsequently, as shown in Fig. 3A, a base film 302 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 301. Although a single layer film is used as the base film 302 in this embodiment, a structure in which two or more layers of the insulating film are laminated may be used. In addition, the base film 302 is for preventing the diffusion of impurities from the substrate 301 (see Fig. 3A).

Next, an amorphous semiconductor film is formed. The amorphous semiconductor film is formed by known means (sputtering method, LPCVD method, plasma CVD method, or the like). The amorphous semiconductor film has a thickness of 30 to 60 nm. Although there is no limitation in the material of an amorphous semiconductor film, Preferably, what is necessary is just to form with silicon, a silicon germanium (SiGe) alloy, etc. (refer FIG. 3 (A)). Moreover, it is not limited to an amorphous semiconductor film, You may form a polycrystalline semiconductor film, a microcrystalline semiconductor film, etc.

Thereafter, dehydrogenation (500 ° C., 1 hour) of the amorphous semiconductor film is performed, followed by heat treatment (500 ° C., 4 hours) by furnace annealing. You may add a laser annealing after this as needed. The crystalline semiconductor film thus obtained is patterned into a desired shape by a photolithography process and an etching process as shown in Fig. 3B to form crystalline semiconductor layers 303 and 304 (see Fig. 3A).

Subsequently, a gate insulating film 305 covering the semiconductor layers 303 and 304 is formed. The gate insulating film 305 is formed by a plasma CVD method or a sputtering method, and is formed into an insulating film containing silicon with a thickness of 40 to 150 nm. The gate insulating film is not limited to the silicon oxynitride film, and an insulating film containing other silicon may be used as a single layer or a laminated structure (see Fig. 3A).

Next, a gate conductive film is formed on the gate insulating film 305. In this embodiment, the first layer gate electrode film 306 (TaN) is used as the first conductive film having a film thickness of 20 to 100 nm, and the second layer gate electrode film 307 is formed as the second conductive film having a film thickness of 100 to 400 nm ( W) is laminated. The gate conductive film may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy material or compound material containing the element as a main component. Further, a semiconductor film represented by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first layer gate electrode film is formed of a tantalum (Ta) film, the second layer gate electrode film is formed of a W film, the first layer gate electrode film is formed of a tantalum nitride (TaN) film, and the second layer gate electrode film is formed. It is good also as a combination made into a Cu film (refer FIG. 3 (A)).

Next, the hard mask layer 308 (Al) which becomes an etching mask is formed in the etching process of the gate electrode mentioned later. In this embodiment, the material of the hard mask is Al, but the material of the hard mask need not be limited to Al alone. The material of the hard mask can be freely selected from materials satisfying the two conditions of "isotropic etching with high selectivity of gate electrode and selectivity" and "high selectivity to the extent that it can be used as a mask in the etching of the LoV region". For example, an ITO thin film, an amorphous silicon film, or the like may be selected. The thickness of the hard mask will be described later.

Subsequently, resist masks 309 and 310 are formed on the hard mask layer 308. The hard masks 311 and 312 are formed by wet etching using the resist mask (see Fig. 3B). As the etchant, a mixed acid such as phosphoric acid, acetic acid, nitric acid, or the like is used. Further, an aqueous hydrochloric acid solution may be used. In dry etching, a carbon-based altered layer may be formed on the sidewalls of the resist mask layer and the etching film depending on the conditions. Corrosion is generated by reacting the altered layer with the remaining Cl ₂ and moisture in the air. Care must be taken because the state may become an uneven state. However, in this embodiment, since it is a wet etching, it is not necessary to consider corrosion or the like.

In later steps, the resist masks 309 and 310 are used as Gate Overlap LDD gate masks, and the hard masks 311 and 312 formed using the resist masks 309 and 310 are used as channel masks. Thus, the edge of the hard mask should be in a position retracted by Lov than the edge of the resist mask. If the thickness of the hard mask is set to be equal to the Lov width, the edge of the hard mask is located at a position retreating Lov from the edge of the resist mask at the time when Gate Overlap LDD gate etching is completed. In addition, the Lov width can be adjusted by setting the thickness of the hard mask to be smaller than Lov and then adjusting the over etching time.

Next, Gate Overlap LDD gate etching is performed using the resist masks 309 and 310, that is, the Gate Overlap LDD gate mask, and only the second layer gate electrode film 307 is anisotropic dry etching (etching of the first step) ( See FIG. 3 (C)). In this embodiment, the gate electrode is composed of two layers of tungsten (W) and tantalum nitride (TaN), and since the first layer gate electrode film TaN functions as an etching stopper at the time of etching the W film, the second layer gate The electrode film W and the first layer gate electrode film TaN are etched under different conditions.

In this embodiment, each gas flow rate is 24/12/24 (sccm) using SF ₆ , Cl _2, and O ₂ as the etching gas, and 700 W of RF (13.56 MHz) is applied to the coiled electrode at a pressure of 2 Pa. The electric power is input to generate plasma to perform etching. 10 W of RF (13.56 MHz) power is supplied to the substrate side (sample stage), and a lower self bias voltage is applied as compared with the first etching process. By etching under these conditions, the W film is anisotropically etched to form first conductive layers 313 and 314. At this time, since only the second layer gate electrode film 307 (W film) is etched, the first layer gate electrode film (TaN) 306 remains unetched (see Fig. 3C).

Subsequently, the first layer gate electrode film 306 is anisotropic dry-etched under different conditions using the second layer gate electrode films (W films) 313 and 314 as masks as the second etching conditions (FIG. 3 ( D)). CF ₄ and Cl ₂ are used as the etching gas, and the gas flow rate ratio is 30/30 (sccm), and 500W RF power is applied to the coil electrode at a pressure of 1.5 Pa to generate a plasma and perform etching. RF power of 10 W is also applied to the substrate side (sample stage), and a substantially negative self bias voltage is applied. As a result, the first layer gate electrode films TaN 315 and 316 are formed.

In addition, it is preferable to perform Gate Overlap LDD gate etching on the conditions which become a complete anisotropic etching. Fully anisotropic etching is not preferable because the gate electrode is etched down the resist mask. When the Gate Overlap LDD gate etching is performed under conditions slightly closer to the isotropic etching than the complete anisotropic etching, the completed line width of the gate electrode is smaller than the line width of the resist mask, but can be easily controlled by a known dimensional correction technique. For example, the line width of the resist mask may be increased by the amount of line width reduced by the modification of the pattern or patterning conditions on the reticle, and the amount of retreat during wet etching may be corrected so that the line width of the hard mask does not change. Since the selection ratio with the resist mask is insufficient, the same countermeasure may be applied to the case where numerical correction is necessary.

The resist masks 309 and 310 are peeled off to expose the hard masks 311 and 312.

Thereafter, Lov region etching is performed using the hard masks 311 and 312. The second layer gate electrode films 313 and 314 are anisotropic dry etched using the first layer gate electrode films 315 and 316 as etching stoppers, and the first layer gate electrode films 315 and 316 are formed in the Lov region. ) Only (see FIG. 3 (E)). Only the second layer gate electrode film is removed by anisotropic dry etching. In the case where the dimensional correction is necessary, the correction may be performed as in the case of the gate overlap LDD gate etching.

Next, the hard masks 311 and 312 are removed by wet etching (see FIG. 3 (F)). In this way, a hat-shaped gate is formed in self-alignment. In addition, although the hard mask is removed in this embodiment, it is not necessary to necessarily remove the hard mask. For example, it is possible to select a silicon oxide film as the hard mask material and to leave the hard mask as part of the interlayer insulating film. As another example, it is possible to select a high melting point metal such as Mo as the hard mask material and leave the hard mask as part of the gate electrode. In the case where the hard mask is not removed, the Lov region etching is preferably performed by fully anisotropic etching.

Thereafter, the doping process is performed. In this embodiment, the semiconductor region 317a (referred to as the first region) on the left side of Fig. 3G is referred to as the n-channel TFT, and the semiconductor region 317b (referred to as the second region) on the right side is referred to as the p-channel TFT. The case will be described. In the present embodiment, the doping process is performed in the order of the n-channel TFT and the p-channel TFT, but this order may be reversed. The first doping treatment is performed to add an impurity element imparting n-type to the semiconductor layer. The doping treatment may be performed by an ion doping method or an ion implantation method. For example, the conditions of the ion doping method are carried out with a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁵ atoms / cm 2 and an acceleration voltage of 60 to 100 kV (5% PH ₃ 40 sccm 60kv 5 k 4.0E15). An element belonging to group 15, typically phosphorus (P) or arsenic (As), is used as an impurity element imparting an n-type. In this case, the first layer gate electrode films 315 and 316 and the second layer gate electrode films 313 and 314 serve as masks for impurity elements imparting n-type, and the first impurity regions are formed by etching. 319 to 322 are formed. Impurity elements imparting n-type are added to the first impurity regions 319 to 322 in a concentration range of 1 × 10 ^{20 to} 1 × 10 ²¹ atons / cm 3. This area is referred to as the n + area (see FIG. 3 (G)).

Thereafter, a second doping process is performed. In this case, the dose amount is lower than that of the first doping treatment, and the impurity element imparting n-type is doped under the condition of a high acceleration voltage. For example, the acceleration voltage is 70-120 kV, in this embodiment, it is set to the acceleration voltage of 90 kV, and it carries out with the dose amount of 3.5 * 10 <^12> atoms / cm <2>, and is a semiconductor inside inner side of the 1st impurity region formed by the 1st doping process. A new impurity region is formed in the layer (5% PH ₃ 30sccm 90kv 0.5㎂ 1.0E14). Doping uses the first layer gate electrode films 315 and 316 and the second layer gate electrode films 313 and 314 as masks for the impurity element, and the lower portion of the first layer gate electrode films 315 and 316. Doped so that an impurity element is also added to the semiconductor layer in (refer FIG. 3 (G)).

In this way, second impurity regions 323 to 326 and first impurity regions 319 to 322 overlapping with the first layer gate electrode films 315 and 316 are formed. The impurity element imparting n-type is made to have a concentration of 1 × 10 ^{17 to} 1 × 10 ¹⁹ atoms / cm 3 in the second impurity region. The second impurity region becomes an n- region (see Fig. 3G). As described above, an n-channel TFT having a Gate Overlap LDD structure is formed. The first doping treatment may be performed after removing the resist mask and before etching the Lov region. In this case, since there is no fear that impurities are added to the Lov region during the first doping process, it is possible to widen the range in which the conditions for the first doping process can be set.

Subsequently, the left semiconductor region 317a is covered with the photoresist 318, and the p-type impurity is doped into the right semiconductor region 317b in that state. A doping process is performed by the same method as that for forming the n-channel TFT. That is, the third impurity regions are added by the third doping process to form third impurity regions 327 and 328, and the fourth impurity regions 329 and 330 to which impurities of lower concentration are added.

In this way, the third impurity region becomes a p + region, and the fourth impurity region becomes a p− region. In this embodiment, the impurity region is formed by ion doping using diborane (B ₂ H ₆ ) (5% B ₂ H ₆ 80 sccm 80kv 5 ㎂ 2.0E16). In the third doping process, the semiconductor region 317a forming the n-channel TFT is covered with the photoresist 318. Phosphorus is added to the impurity regions 327 to 330 at different concentrations by the first doping treatment and the second doping treatment, but the concentration of the impurity element imparting the p-type in any of the regions is 2 × 10 ²⁰ to 2. by doping process so that the × 10 ²¹ atoms / ㎤, does not cause any problem because it functions as a source region and a drain region of the p-channel TFT (refer to FIG. 3 (H)).

As described above, an n-channel TFT having a gate overlap LDD structure is formed. A method of covering either one of the n-channel TFT and the p-channel TFT with a resist mask, adding n-type impurities or p-type impurities, then covering the other with a resist mask, and adding n-type impurities or p-type impurities By this, a method of manufacturing an n-channel TFT and a p-channel TFT may be taken.

Thereafter, an interlayer insulating film is formed by using a plasma CVD method or a sputtering method. For example, a silicon nitride film or other insulating film may be used as a single layer or a laminated structure. Then, a process of activating the impurity element added to each semiconductor layer is performed. This activation process is carried out by heat treatment with annealing. The temperature of the heat treatment may be performed at 400 to 700 ° C, typically at 500 to 550 ° C. In addition to the thermal annealing method, it is also possible to apply the laser annealing method or the rapid thermal annealing method (RTA method). By this heat treatment, hydrogen contained in the interlayer insulating film is released, and it is possible to hydrogenate the semiconductor layer.

Thereafter, patterning is performed to form contact holes that reach the source wiring and contact holes that reach each impurity region. And the wiring which electrically connects with each impurity area | region is formed, respectively. As these wirings, a single layer or a laminated film of a Ti film or other alloy film is patterned and formed. The TFT is completed through such a process. These processes are not shown. As described above, it is possible to manufacture a CMOS circuit combining two Gate Overlap LDD structure transistors in the same substrate.

Example 2

The first embodiment has been described with reference to a manufacturing method of a control circuit using a so-called CMOS circuit, but this embodiment will be described with reference to a manufacturing method in which a Gate Overlap LDD structure TFT and a single drain structure TFT are mixed. It is a manufacturing method which added the patterning process once to the manufacturing method of Example 1. Two types of single-drain structures having different widths of the gate electrodes on the active layer can be manufactured in the order of adding the patterning process in the manufacturing process. Therefore, there are two methods of manufacturing a mixture of a TFT having a gate overlap LDD structure and a single drain structure TFT. Hereinafter, the first manufacturing method will be described in detail.

First, a first method of mixing and manufacturing a gate overlap LDD structure TFT and a single drain structure TFT, which is an embodiment of the present invention, will be described with reference to FIG. This embodiment applies a method of manufacturing two or more Gate Overlap LDD structure TFTs described in Embodiment 1 in the same substrate. Therefore, since the process from FIG. 3 (A) to FIG. 3 (E) basically demonstrated in Example 1 overlaps with the process of FIG. 4 (A)-FIG. 4 (E), description is abbreviate | omitted and it follows hereafter N A process of forming a resist mask covering the region 417a of the channel type TFT by patterning will be described (Fig. 4 (F)).

The resist mask 418 is formed so as to cover the region 417a of the N-channel TFT by a known patterning method (see Fig. 4F). Subsequently, an anisotropic etching process of the TaN film is performed on the region 417b of the p-channel TFT. The first layer gate electrode film 416f is anisotropic dry etched using the second layer gate electrode film (W film) 414f as a mask. As a result, a first layer gate electrode film (TaN film) 416g is formed (see Fig. 4G). In addition, it is preferable that etching of a TaN film is performed on conditions which become a complete anisotropic etching. At this time, since the N-channel TFT is covered with the resist mask 418, it is not etched. In the p-channel TFT, the channel region covered with the hard mask 412f is not etched, but the TaN film in the stripped Lov region is etched.

Next, the resist mask 418 is peeled off, and the hard mask 412f is peeled off. In this way, the gate electrode of the N-channel TFT 417a region becomes a hat-shaped gate shape having a two-layer structure, and the gate electrode of the p-channel TFT has a normal shape.

Furthermore, impurities of a predetermined condition are added to the source and drain regions, the Lov region, and the p-channel source and drain regions of the n-channel TFT through the same processes as those of FIGS. 3 (G) and 3 (H) described in the first embodiment. Is done. In this manner, the first impurity regions 419 and 420, which are high concentration impurity regions, and the second impurity regions 423 and 424, which are low concentration impurity regions, are formed in the n-channel TFT, and the source and drain regions are formed in the p-channel TFT. Normal high concentration impurity regions 421 and 422 are formed. Thereafter, an interlayer insulating film is formed, and a step of activating an impurity element added to each semiconductor layer is performed.

Thereafter, patterning is performed to form contact holes that reach the source wiring and contact holes that reach each impurity region. And the wiring which electrically connects with each impurity area | region is formed, respectively. The TFT is completed through such a process. These processes are not shown. As described above, it is possible to produce a mixture of an N-channel gate overlap LDD structure TFT and a p-channel single drain structure TFT in the same substrate.

Example 3

Next, a second method of mixing and manufacturing a gate overlap LDD structure TFT and a single drain structure TFT which is an embodiment of the present invention will be described with reference to FIG. This embodiment applies a method of manufacturing two or more Gate Overlap LDD structure TFTs described in Embodiment 1 in the same substrate. Therefore, since the process of FIG. 3 (A)-FIG. 3 (D) demonstrated by Example 1 overlaps with the process of FIG. 5 (A)-FIG. 5 (D) fundamentally, description is abbreviate | omitted and is p-channel type hereafter. A process of forming a resist mask covering the region 517b of the TFT by patterning (Fig. 5 (E)) will be described.

The resist mask 518 is formed so as to cover the region 517b of the P-channel TFT according to a known patterning method (see Fig. 5E).

Next, Lov region etching is performed using a channel mask. Anisotropic dry etching of the second layer gate electrode film 513d using the first layer gate electrode film 515e as an etching stopper leaves only the first layer gate electrode film 515e in the Lov region (Fig. 5 (E)). Reference). Only the second layer gate electrode film 507 at the time of Gate Overlap LDD gate etching is etched by the same method as in the case of anisotropic dry etching. In the case where dimensional correction is required, the correction may be performed in the same manner as in the case of Gate Overlap LDD gate etching. At this time, the p-channel TFT is covered with the resist mask 518 and thus is not etched. In the n-channel TFT, the channel region covered with the hard mask 511e is not etched, but the second layer gate electrode film W in the stripped Lov region is etched.

Next, the resist mask 518 is peeled off, and the hard masks 511f and 511g are peeled off. In this way, the gate electrode of the n-channel TFT becomes a hat-shaped gate, and the gate electrode of the n-channel TFT becomes a normal shape.

Also, impurities having predetermined conditions are applied to the source and drain regions, the Lov region, and the p-channel source and drain regions of the n-channel TFT through the same processes as those of FIGS. 3 (G) and 3 (H) described in the first embodiment. Addition is performed. In this way, the first impurity regions 519 and 520, which are high concentration impurity regions, and the second impurity regions 523 and 524, which are low concentration impurity regions, are formed in the n-channel TFT, and the source and drain regions are formed in the p-channel TFT. Normal high concentration impurity regions 521 and 522 are formed (see Fig. 5F). Thereafter, the TFT is completed through an interlayer insulating film forming step, an activation step, a contact hole forming step, and a wiring forming step. These processes are not shown. As described above, the n-channel gate overlap LDD structure TFT and the p-channel single drain structure can be mixed and manufactured in the same substrate.

Example 4

In this embodiment, a description will be given of a manufacturing method in which a Lov of different Gate Overlap LDD structure TFTs is mixed. Basically, it manufactures similarly to Example 1, but differs in the following point. A mask is formed for each type of Lov target value, that is, the length of the region overlapping with the gate electrode in the LDD region. Then, Gate Overlap LDD gate etching is performed separately. The thickness of the hard mask is controlled by setting the thickness of the hard mask to a value smaller than the minimum value of Lov and controlling the amount of over etching during wet etching.

A method in which Lov, which is an embodiment of the present invention, is produced by mixing different Gate Overlap LDD structure TFTs is described below. This embodiment applies a method of manufacturing two or more Gate Overlap LDD structure TFTs described in Embodiment 1 in the same substrate. Therefore, description common to the description in Example 1 will be omitted, and changes will be described in detail. In this embodiment, a method of forming Lov = 0.3 mu m TFT and Lov = 0.5 mu m TFT in the same substrate will be described with reference to FIG.

First, as shown in FIG. 6A, a base film 602, an active layer 603, a gate insulating film 604, and a first layer gate electrode film 605 as a first conductive film on the substrate 601. To the deposition of the second layer gate electrode film 606 and the hard mask layer 607 as the second conductive film. The thickness of the hard mask layer 607 should be 0.3 micrometer or less which is a value of the target Lov.

Next, a resist mask is formed. A region of the TFT having a Lov value of 0.3 µm forms a resist mask 608 to serve as a gate overlap LDD gate mask. The resist mask 609 is formed so as to cover the entire area of the TFT having a Lov value of 0.5 mu m. Such a resist mask can be easily formed by design change of the pattern on the patterning reticle used in Example 1. FIG.

Then, only the TFT having a Lov objective value of 0.3 µm is subjected to Gate Overlap LDD gate etching in the same manner as in FIGS. 3A to 3D in Example 1. FIG. Thereafter, the resist masks 608 and 609 are peeled off.

In addition, the dimension of the hard mask 607 is controlled by controlling the amount of over-etching at the time of wet etching, and makes the dimension difference with the resist mask 608 one side 0.3 micrometer.

In the state advanced to here, the TFT area | region of 0.3 micrometers of Lov values becomes the state of FIG. 6 (E), and the length from the edge of a gate electrode pattern to the edge of a hard mask is 0.3 micrometers, and corresponds to the target Lov value. do. On the other hand, in the TFT region having a desired Lov value of 0.5 mu m, the entire hard mask layer 607 is not etched and remains in the state of Fig. 6A.

Next, a resist mask is formed. A region of the TFT having a Lov value of 0.5 µm forms a resist mask 611 by patterning. This is the Gate Overlap LDD gate mask. At this time, a resist mask 610 is formed so as to cover the entire area of the TFT having a Lov value of 0.3 mu m. Such a resist mask can be easily formed by design change of the pattern on the patterning reticle used in Example 1. FIG. In addition, a hard mask is formed by wet etching using the resist masks 610 and 611. The dimension of the hard mask 607g controls the amount of over-etching at the time of wet etching, and makes the dimension difference with the resist mask 611 into 0.5 micrometer one side.

The above-described Gate Overlap LDD gate etching is performed only on the TFT region having a desired Lov value of 0.5 µm. This is performed by the same process as FIG. 3 (A)-FIG. 3 (D) in Example 1. FIG. Thereafter, the resist masks 610 and 611 are peeled off.

In the state advanced to here, the area | region of TFT of 0.5 micrometer of target Lov values becomes the state of FIG. 6 (F), and the length from the edge of a gate electrode pattern to the hard mask edge is 0.5 micrometer corresponded to a target Lov value. do. On the other hand, the TFT region having a desired Lov value of 0.3 μm was not etched without changing in the state of the previous process because the entire area was covered with the resist mask 610 during the Gate Overlap LDD gate etching of the Lov value of 0.5 μm. Do not. That is, in the state of FIG. 6E, the length from the edge of the gate electrode pattern to the edge of the hard mask corresponds to the desired Lov value at 0.3 μm.

Next, using the hard masks 607f and 607g which are channel masks, Lov area | region etching is performed with respect to two TFT area | regions whose target Lov values are 0.3 micrometer and 0.5 micrometer. Only the second layer gate electrode film is subjected to the anisotropic dry etching process by the same process as that in Fig. 3E in the first embodiment. Thereafter, the hard masks 607f and 607g are peeled off.

Thus, Lov becomes 0.3 micrometer in the area | region of TFT with a target Lov value of 0.5 micrometer, and 0.5 micrometer in the area | region of TFT which has a target Lov value of 0.5 micrometer. At the same time, obtain the desired Lov. In this manner, a hat-shaped gate having a desired Lov can be formed, and a TFT having a Gate Overlap LDD structure having a Lov of 0.3 μm and a TFT having a Gate Overlap LDD structure having a Lov of 0.5 μm are mixed in the same substrate. can do.

In addition, the source and drain regions of the n-channel TFT, the Lov region, the p-channel source and drain region, and Lov are subjected to the same processes as those in FIGS. 3 (G) to 3 (H) described in the first embodiment. Impurities under predetermined conditions are added to the region. In this manner, the first impurity regions 619 to 622 which are high concentration impurity regions and the second impurity regions 623 to 626 which are low concentration impurity regions are formed in the N-channel TFT and the P-channel TFT.

Thereafter, an interlayer insulating film is formed. And the process of activating the impurity element added to each semiconductor layer is performed.

Patterning is performed to form contact holes that reach the source wiring and contact holes that reach each impurity region. Wirings electrically connected to the respective impurity regions are formed. The TFT is completed through such a process. These processes are not shown. As described above, the n-channel Gate Overlap LDD structure TFT and the p-channel Gate Overlap LDD structure TFT having different Lov regions in the same substrate can be mixed.

Example 5

Next, the manufacturing method of the TFT structure which has only a Loff area is demonstrated by changing the manufacturing method of the Gate Overlap LDD structure transistor of Example 1. FIG.

In this embodiment, a manufacturing method of a TFT having an Loff region will be described with reference to FIG. Since the manufacturing method from FIG. 3 (A) to FIG. 3 (C) which is basically from a resist mask pattern process to the process of only etching a 2nd layer gate electrode film is the same as the invention of Example 1, it abbreviate | omits here. Since only the second layer gate electrode films (W films) 713 and 714 are etched by the etching conditions shown in FIG. 3C, the first layer gate electrode films (TaN) 706 remain unetched. . The reason for leaving the first layer gate electrode film TaN is to prevent the gate insulating film and the active layer of the source and drain regions from being lost during the channel etching described later. However, when etching the 2nd layer gate electrode film (W film) by the etching conditions which do not need to consider this, you may etch without leaving a 1st layer gate electrode film.

Moreover, it is preferable to perform this etching on the conditions which become a complete anisotropic etching. Fully isotropic etching is not preferable because the second layer gate electrode film (W film) is etched down to below the resist mask. When performing on the conditions somewhat closer to an isotropic etching than a complete anisotropic etching, dimension correction may be performed by the method demonstrated in Example 1. FIG.

Next, the resist masks 709 and 710 are peeled off to expose the hard masks 711 and 712. This process is not shown. Then, a resist mask 718 is formed so as to cover the region 717b of the p-channel TFT by a known patterning method (see Fig. 7D). Thereafter, n-type high concentration impurity is added to the source and drain regions of the n-channel TFT. In this embodiment, since the first layer gate electrode film is left in the source and drain regions, high concentration impurities are added through the first layer gate electrode film and the gate insulating film. In the case where the first layer gate electrode film is removed by etching using a gate Loff mask, high concentration impurities are added through only the gate insulating film. However, since the Loff region is masked by the first layer gate electrode film and the second layer gate electrode film, impurities are not added at all. As a result, only the source and drain regions become high concentration impurity regions, and the first impurity regions 719 and 720 are formed (see Fig. 7D).

Thereafter, the resist mask 718 is peeled off. Then, a resist mask 721 is formed to cover the n-channel TFT region 717a by a known patterning method (see Fig. 7E). Thereafter, p-type high concentration impurities are added to the source and drain regions of the p-channel TFT. Impurity addition conditions are similar to those of the n-channel TFT, and are omitted here. As a result, only the source and drain regions become high concentration impurity regions, and the first impurity regions 721 and 722 are formed (see Fig. 7E).

Next, after the addition of the impurity, the resist mask 721 is peeled off to expose the hard mask 711. Then, channel etching using hard masks 711 and 712, that is, channel masks, is performed. In this embodiment, since the first layer gate electrode film TaN is left as an etching stopper, the second layer gate electrode film W in the Loff region is etched and the first layer gate electrode film TaN is etched. In addition, etching conditions are based on Example 1. FIG. When the first layer gate electrode film TaN is removed without leaving by etching using a gate Loff mask (a mask covering a region in which the channel region and the Loff region are combined), the second layer gate electrode film W and the first layer of the Loff region are removed. The one-layer gate electrode film TaN is removed. In this manner, conductive layers 723a and 723b of the first shape are formed (FIG. 7F). Moreover, it is preferable to perform this etching also on the conditions used as a complete anisotropic etching. If necessary, dimension correction is performed.

The hard masks 711 and 712 are then removed by wet etching. Then, a resist mask 729 is formed so as to cover the region 717b of the p-channel TFT by a known patterning method (see Fig. 7G). Thereafter, an N-type low concentration impurity is added to the Loff region of the n-channel TFT. Impurities are added through the gate insulating film. The impurity addition to the Loff region may be added through the first layer gate electrode film and the gate insulating film before removing the first layer gate electrode film TaN in the Loff region.

Thereafter, the resist mask 729 is peeled off. Subsequently, a resist mask 724 is formed to cover the region 717a of the n-channel TFT by a known patterning method (see Fig. 7H). Thereafter, p-type low concentration impurities are added to the source and drain regions of the p-channel TFT. Impurity addition conditions are similar to those of the n-channel TFT, and are omitted here. As a result, the source and drain regions become high concentration impurity regions, and the Loff regions become low concentration impurity regions, thereby forming first impurity regions 719 to 722 and second impurity regions 725 to 728 (FIG. 7). (H)).

Thereafter, an interlayer insulating film is formed. And the process of activating the impurity element added to each semiconductor layer is performed.

Patterning is performed to form contact holes that reach the source wiring and contact holes that reach each impurity region. Wirings electrically connected to the respective impurity regions are formed. The TFT is completed through such a process. These processes are not shown. As described above, it is possible to produce a mixture of TFTs having only N-channel and P-channel Loff regions in the same substrate.

In this embodiment, although the Loff values of the two TFTs in the same substrate are constant, TFT or single-drain structures having different Loff values by forming a lamination mask and performing gate Loff etching for each Loff value (Loff = 0) It is good also as a manufacturing method of the semiconductor device which mixes TFT of on a same board | substrate.

Example 6

In this embodiment, a method of manufacturing a transmissive liquid crystal display device using a TFT having a Gate Overlap LDD structure will be described. In addition, since it manufactures by the method similar to the manufacturing method of Example 1, the overlapping description is abbreviate | omitted.

First, the manufacturing method of the TFT array substrate which is one of the structural requirements of a liquid crystal display device is demonstrated.

In Fig. 11, a substrate 1101 for TFT manufacturing is prepared. Subsequently, underlying insulating films 1102a and 1102b are formed in the substrate 1101 to prevent diffusion of impurities from the substrate. As the base insulating film 1102, an insulating film such as a silicon oxide film or a silicon nitride film is used.

The semiconductor layer 1103 is formed on the underlying insulating film 1102. After the amorphous silicon film is formed, the semiconductor layer 1103 forms a crystalline silicon film obtained by crystallizing the amorphous silicon film into a desired shape by photolithography and etching. An impurity for controlling the threshold voltage of the element is added to the semiconductor layer 1103. As the impurity, phosphorus or boron is used. The addition of the impurity is performed by doping after forming the amorphous silicon film, or after crystallizing the amorphous silicon film, or after forming the semiconductor layer 1103. In addition, you may use the amorphous silicon film which added the said impurity at the time of film-forming.

Subsequently, a gate insulating film 1104 is formed on the semiconductor layer 1103. The insulating film 1104 is formed by forming a silicon oxide film having a thickness of 100 nm to 120 nm. The thickness of the gate insulating film 1104 may be 100 nm or less or 120 nm or more as needed. In addition to the silicon oxide, an insulating film such as a silicon nitride film may be used.

Gate electrodes 1105a and 1105b are formed on the gate insulating film 1104. A conductive film 1105a having a thickness of 20 to 100 nm and a conductive film 1105b having a thickness of 100 to 400 nm are laminated on the gate insulating film 1104, and a gate electrode 1105 having a desired shape is formed by photolithography and etching. . In this embodiment, TaN is used for the conductive film 1105a and W is used for the conductive film 1105b.

n− forms region 1106. The n− region 1106 is formed by doping phosphorus on the entire surface of the semiconductor layer. Phosphorus is used in the present embodiment, but as long as it is an n-type impurity element, As may be used. In addition to ion doping, a method such as ion implantation may be used.

n-region 1107 and n + region 1108 are formed. After the resist mask is prevented from adding n-type impurities to regions other than the n- region 1107 and the n + region 1108, phosphorus is doped to form n- and n + regions. Phosphorus is doped in the n− region 1107 through the gate electrode 1105a. In addition, the n− region is doped through the insulating film remaining on the semiconductor layer 1103. In this embodiment, the doping for forming the n− region 1107 and the doping for forming the n + region 1108 are simultaneously performed. Alternatively, the doping conditions may be changed for forming the n− region and for forming the n + region. In addition to phosphorus, n-type impurities such as As may be used, and the addition method may be a method such as ion implantation in addition to ion doping.

p-region 1109 and p + region 1110 are formed. After the resist mask is prevented from adding p-type impurities to regions other than the p- region 1109 and the p + region 1110, phosphorus is doped to form the p- region and the p + region. Phosphorus is doped in the p− region 1109 through the gate electrode 1105a. In addition, the p− region is doped through the insulating film remaining on the semiconductor layer 1103. In this embodiment, the doping to form the p- region 1109 and the doping to form the p + region 1110 are performed simultaneously, but the doping conditions are used to form the p- region 1109 and to form the p + region 1110. You may change it. In addition to phosphorus, p-type impurities such as As may be used, and the addition method may be a method such as ion implantation in addition to ion doping.

The interlayer insulating films 1111a, 1111b, and 1111c are formed. The interlayer insulating film 1111 is formed of a first interlayer insulating film 1111a, which is an inorganic film, a second interlayer insulating film 1111b, and a third interlayer insulating film 1111c, which is an organic film.

A silicon oxide film with a thickness of 50 to 100 nm is used for the first interlayer insulating film 1111a. After the first interlayer insulating film 1111a is formed, impurities added to the semiconductor layer by heat are activated. The activation is carried out by a furnace at 550 ° C. for 1 to 12 hours in a nitrogen gas atmosphere. Although a furnace was used for activation in this embodiment, it may be performed using an RTA or a laser. The atmosphere, temperature, and time of the activation are not limited to the above. The interlayer insulating film 1111a may not be provided as long as the gate electrode 1105 is activated in an atmosphere not oxidized, such as activation by furnace or RTA in a low oxygen atmosphere. In addition, even when activation is performed by a laser, the interlayer insulation film 1111a may not be provided. In addition to the silicon oxide film, a material other than the silicon oxide film may be used as long as it is resistant to the activation temperature, prevents oxidation of the gate electrode 1105 during activation, and has good light transmittance.

A silicon nitride film having a thickness of 50 to 100 nm is used for the second interlayer insulating film 1111b. After the second interlayer insulating film 1111b is formed, a heat treatment at 350 ° C to 420 ° C is performed in a nitrogen atmosphere for 1 hour. In the present embodiment, heat treatment is performed in a nitrogen atmosphere, but may be performed in a hydrogen atmosphere of 3 to 100%. In addition, heat processing time is not limited to 1 hour. If the heat treatment is performed for 1 hour in a hydrogen atmosphere of 3 to 100% after the activation treatment after the formation of the first interlayer insulating film 1111a, the heat treatment after forming the second interlayer insulating film 1111b may not be necessary.

Acrylic having a thickness of 0.6 to 1.6 mu m is used for the third interlayer insulating film 1111c. In addition to acryl, materials, such as polyimide which has insulation, may be used. Moreover, you may use the inorganic membrane which has insulation. Although the thickness of an inorganic film differs also by the dielectric constant of the said inorganic film, it is normally 1-3 micrometers.

The pixel electrode 1112 is formed on the third interlayer insulating film 1111c. The pixel electrode 1112 is formed by photolithography and etching after forming Indium Tin Oxide (ITO). As long as it is a transparent conductive film, you may use tin oxide etc. other than ITO.

After the pixel electrode 1112 is formed, contact holes for connecting the heavily doped impurity regions 1108 and 1110 and the wiring 1113 are formed by photolithography and etching.

After the contact hole is formed, the wiring 1113 is formed. The wiring 1113 forms a first Ti film having a thickness of about 60 nm, and then forms a TiN film having a thickness of about 40 nm, and further forms an Al-Si (Al containing 2 wt% Si) film having a thickness of 350 nm. Finally, the laminated film on which the second Ti film is formed is formed by photolithography and etching. The first Ti film prevents Al in the Al-Si film from diffusing into the semiconductor layer, and the second Ti film prevents hilllock of the Al-Si film. In the present embodiment, a TiN film is formed. However, the TiN film is formed to enhance the diffusion preventing effect of Al. In addition, other low resistance conductive films such as Al-Ti (Al containing Ti) other than Al-Si may be used.

In this embodiment, an area in which the pixel electrode 1112 and the wiring 1113 are stacked is provided, and the electrical connection between the pixel electrode 1112 and the wiring 1113 is made without forming a contact hole.

Through the above steps, a drive circuit having an n-channel TFT having a Gate Overlap LDD structure and a p-channel TFT having a Gate Overlap LDD structure, a TFT array having a pixel TFT and a pixel portion having a storage capacitor and a pixel electrode on the same substrate Prepare the substrate.

Next, the manufacturing method of a counter substrate is demonstrated. As shown in FIG. 12, a light shielding film 1202 is formed on the substrate 1201. The light shielding film 1202 forms a metal chromium, and is formed by photoexposure and etching.

The pixel electrode 1205 is formed on the light shielding film 1202. The pixel electrode 1205 forms ITO, which is a transparent conductive film, and is formed by photolithography and etching.

When the color filter 1203 is provided between the light shielding film 1202 and the pixel electrode 1205, a colored resin of a desired color is applied on the light shielding film 1202 by spin coating, exposed and developed to form it. . The color filter forming process is repeated for each of the color filters 1203a to 1203c (not shown) of three colors of red, blue, and green.

The protective film 1204 is formed for the purpose of flattening by supplementing the level difference between the color filter 1203 and the light shielding layer 1202. The protective film 1204 is formed by applying acrylic on the color filter. In addition to acryl, a planarizable material may be used. When the color filter is not provided, the protective film 1204 may not be provided. The counter substrate is manufactured through the above process.

When the TFT array substrate 1209 and the opposing substrate 1210 are manufactured, the liquid crystal panel 1211 is manufactured using these substrates.

The alignment film 1208 is formed on the side where the TFT of the TFT array substrate 1209 is formed and on the side where the pixel electrode of the opposing substrate 1209 is formed, respectively. The formation of the alignment film 1208 uses an offset printing method. Although the polyimide resin is used for the material of the oriented film 1208, polyamide resin etc. may be used besides this.

The rubbing treatment is performed on the TFT substrate on which the alignment film 1208 is formed and on the side on which the alignment film on the opposite substrate is formed so that the liquid crystal molecules are aligned with a certain pre-tilt angle. After rubbing treatment. The TFT array substrate 1209 and the counter substrate 1210 are cleaned in order to remove hairs generated by the rubbing treatment or hair growth of the rubbing cloth.

After applying a sealing agent (not shown) to the opposing substrate side, the opposing substrate 1210 is heated in an oven to temporarily harden the sealing agent. After the temporary curing, the spacers of plastic spheres are scattered on the side where the pixel electrodes of the opposing substrate are formed.

The liquid crystal panel 1211 is manufactured by matching the two substrates with high precision so that the side on which the TFT of the TFT array substrate 1209 is formed and the side on which the pixel electrode 1205 of the opposing substrate 1210 are formed to face each other. . A filler (not shown) is mixed in the sealing agent, and both substrates can be aligned at uniform intervals by the filler and the spacer.

Unnecessary portions of the matched substrate are cut out to form a liquid crystal panel 1211 substrate having a desired size. The liquid crystal material 1206 is injected into the liquid crystal panel 1211. After the entire liquid crystal material 1206 is filled in the inside of the panel, it is completely sealed by an encapsulant (not shown).

13 is a top view of the liquid crystal panel 1211. The scan signal driver circuit 1302a and the image signal driver circuit 1302b are provided around the pixel portion 1301. In addition, a signal processing circuit 1302c such as a CPU or a memory may be provided. The drive circuit is connected to the external input / output terminal group 1304 by the connection wiring group 1303.

In the pixel portion 1301, a gate wiring group extending from the scan signal driving circuit 1302a and a data wiring group extending from the pixel signal driving circuit 1302b intersect in a matrix to form pixels, and pixel TFTs are formed in each pixel, respectively. And a storage capacitor and a pixel electrode are formed.

The sealant 1305 is outside the pixel portion 1301 and the scan signal driving circuit 1302a, the image signal driving circuit 1302b, and the signal processing circuit 1302c on the TFT array substrate 1307, and is an external input terminal. It forms in the part inside (1304).

On the outside of the liquid crystal panel 1211, a flexible printed circuit board (FPC) 1306 is connected to an external input terminal 1304, and is connected to each drive circuit by a connection wiring group 1303. . The external input terminal 1304 is formed of the same conductive film as the data wiring group. The flexible printed wiring board 1306 has copper wiring formed on an organic resin film such as polyimide, and is connected to the external input terminal 1304 with an anisotropic conductive adhesive.

On the opposite substrate side of the liquid crystal panel 1211, a polarizing plate and a retardation plate are mounted so that linearly polarized light in the same direction as the director direction of the liquid crystal molecules of the liquid crystal layer closest to the opposite substrate is incident. Further, a polarizing plate and a retarder are mounted on the TFT substrate side of the panel so that light in the same direction as the director direction of the liquid crystal molecules of the liquid crystal layer closest to the TFT substrate is emitted. In the above manner, it is possible to complete the liquid crystal display device of the present invention.

According to the manufacturing method of this invention, the mask pattern of a 1st layer can be formed in self-alignment with respect to the mask pattern of a 2nd layer, and as a mask pattern with a dimension different in a different form only by one photolithography process. The line width on the active layer is set to be Li in the mask pattern of the first layer and L 'in the mask pattern of the second layer, and anisotropic etching using the mask pattern of the second layer, and anisotropy using the mask pattern of the first layer By performing etching sequentially, a hat-shaped gate can be formed in self alignment. Therefore, the number of reticles used in the manufacturing process can be reduced, and the problem of complexity of the manufacturing method accompanying the miniaturization of the TFT having only the gate overlap LDD structure and the Loff region can be solved.

Further, even when the gate electrode film is formed of a single layer film, a hat-shaped gate can be formed by precisely controlling the thickness of the gate film on the Lov region by anisotropic etching using the mask pattern of the second layer.

In addition, according to the manufacturing method of the present invention, the conductive film of the first layer can be used as an etching stopper when the conductive film of the second layer is etched by making the conductive film have a two-layer structure of different material. We can expand choice of condition. Therefore, the combination of the 1st conductive film and the 2nd conductive film which comprise a hat-shaped gate is arbitrarily selected from the element chosen from Ta, W, Ti, Mo, Al, Cu, or the alloy material which has the said element as a main component. It is possible to do

As described above, in the present invention, the second layer gate electrode is not limited to an aluminum film or an aluminum alloy film, and thus, an excellent effect that is not available in the prior art is mentioned.

According to the present invention, since a high melting point metal such as tungsten (W) can be selected as the gate material, activation of impurities can be performed by ordinary heat treatment (550 to 800 ° C). For this reason, the activation step is not limited to the ion implantation method, and heat treatment may be performed after the heat treatment or the ion implantation method. In addition, by using a high melting point metal, it is possible to prevent deterioration of the characteristics of the electrically active region by heat treatment.

According to the present invention, since a metal film or a composite material film having a low resistance value can be used as a gate material, and miniaturization of these materials can be realized by a self-aligning process, the circuit operation speed can be increased even with a TFT of a minute region In addition, it is possible to cope with the increase in speed due to the recent progress of ultra-LSI.

In addition, according to the method for manufacturing a semiconductor device of the present invention, since the size of the resist mask (second layer mask pattern) can be set larger than that of the hard mask (first layer mask pattern), the line width of the resist mask on the active layer is increased. L ', so that it can be made larger than Li, even in the process of a gate-overlap LDD structure with enhanced miniaturization and a TFT having only an Loff region, the line width of the resist mask on the active layer is not reduced and the patterning margin can be enlarged. have. The expansion of the patterning margin is a great advantage when using large substrates that cannot ignore the effects of substrate warping.

In addition, the hard mask is formed by a wet etching process using a resist mask, thereby preventing irregularities in film thickness, etching spots, corrosion, and defects in which a film remains in the process of TFTs with enhanced micronization.

Claims (4)

A conductive film composed of a single layer or a plurality of layers is formed on the semiconductor film, Forming a hard mask layer on the conductive film, Forming a resist mask on the hard mask layer, The hard mask layer is etched using the resist mask to form a hard mask pattern having an end portion inside the resist mask, The conductive film is etched using the resist mask to form a conductive layer of a first shape, Partially etching the exposed portion of the first shape conductive layer using the hard mask pattern to form a second conductive layer having a thinner thickness than the portion covered with the hard mask pattern, By adding an impurity to the semiconductor film using the second shape conductive layer as a mask, the first impurity region sandwiching the channel formation region and the channel formation region and between the first impurity region and the channel formation region. A second impurity region having an impurity concentration lower than that of the first impurity region is provided. Forming a first conductive film on the semiconductor film, Forming a second conductive film on the first conductive film, Forming a hard mask layer on the second conductive film, Forming a resist mask on the hard mask layer, The hard mask layer is etched using the resist mask to form a hard mask pattern having an end portion inside the resist mask, The second conductive film and the first conductive film are etched using the resist mask to form a conductive layer of a first shape, By using the hard mask pattern, the second conductive film forming the first conductive layer is selectively etched so that the end of the first conductive film is positioned outside the end of the second conductive film. Form the A first impurity region overlapping the first conductive film and a second impurity region outside the first impurity region are formed in the semiconductor film by using the second shape conductive layer Method of preparation. Forming a first conductive film on the semiconductor film, Forming a second conductive film on the first conductive film, Forming a hard mask layer on the second conductive film, Forming a resist mask on the hard mask layer, The hard mask layer is etched using the resist mask to form a hard mask pattern having an end portion inside the resist mask, The second conductive film is etched using the resist mask to form a first conductive layer, A first impurity region is formed in the semiconductor film by using the first shape conductive layer, By using the hard mask pattern, the first conductive layer and the first conductive layer are etched to form a second conductive layer, A second impurity region is formed inside said first impurity region in said semiconductor film using said second shape conductive layer. Forming a semiconductor film in the first region and the second region, Forming a first conductive film on the semiconductor film, Forming a second conductive film on the first conductive film, Forming a hard mask layer on the second conductive film, Forming first and second resist masks on the hard mask layer in the first region and the second region, respectively, Etching the hard mask layer using the first and second resist masks to form first and second hard mask patterns having end portions inside the resist mask, Etching the second conductive film and the first conductive film using the first and second resist masks; In addition, a first gate electrode and a second gate electrode are formed in the first region and the second region, Forming a first low concentration impurity region overlapping the first conductive film and a first impurity region outside the first low concentration impurity region in the semiconductor film by using the first gate electrode, A second low concentration impurity region overlapping the second conductive film and a second impurity region outside the second low concentration impurity region are formed in the semiconductor film by using the second gate electrode; Way.