KR101061850B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Thin film transistor array panel and manufacturing method thereof Download PDF

Info

Publication number
KR101061850B1
KR101061850B1 KR20040071612A KR20040071612A KR101061850B1 KR 101061850 B1 KR101061850 B1 KR 101061850B1 KR 20040071612 A KR20040071612 A KR 20040071612A KR 20040071612 A KR20040071612 A KR 20040071612A KR 101061850 B1 KR101061850 B1 KR 101061850B1
Authority
KR
South Korea
Prior art keywords
formed
molybdenum
electrode
gate
layer
Prior art date
Application number
KR20040071612A
Other languages
Korean (ko)
Other versions
KR20060022839A (en
Inventor
배양호
이제훈
정창오
조범석
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR20040071612A priority Critical patent/KR101061850B1/en
Publication of KR20060022839A publication Critical patent/KR20060022839A/en
Application granted granted Critical
Publication of KR101061850B1 publication Critical patent/KR101061850B1/en

Links

Images

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3276Wiring lines
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F2001/13629Multi-layer wirings
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F2001/136295Materials; Compositions; Methods of manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/914Doping
    • Y10S438/924To facilitate selective etching

Abstract

A molybdenum alloy layer and an aluminum layer in which a predetermined amount of niobium (Nb), vanadium (V), or titanium (Ti) are added to molybdenum (Mo) as a wiring of a thin film transistor array panel for a liquid crystal display device or an organic light emitting display device. By forming a laminated structure of the semiconductor layer, undercut, overhang, and mouse bite are not formed during etching due to a decrease in the difference in the relative etching rates between the molybdenum alloy layer and the aluminum layer than in the case of using pure molybdenum (Mo). The present invention also relates to a thin film transistor array panel having both low resistance and chemical resistance, and a method of manufacturing the same, wherein contact characteristics with the pixel electrode are also improved.
Molybdenum Alloy, Niobium, Vanadium, Titanium, Resistivity, Etch Rate, Undercut

Description

Thin film transistor array panel and method for manufacturing same {Thin film transistor array panel and method for manufacturing the same}

1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ',

3A, 4A, 5A, and 6A are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to the first embodiment of the present invention. Are listed accordingly,

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

7 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along the line VIII-VIII ′ of FIG. 7;

9 to 13B are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

14A is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention.

FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb ′ ′ of FIG. 14A;

15A to 16 are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to a third exemplary embodiment.

17 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to a fourth exemplary embodiment.

18 and 19 are cross-sectional views taken along the lines XVIII-XVIII 'and XIX-XIX' of FIG. 17, respectively.

20 and 21 are cross-sectional views taken along the lines XX-XX 'and XXI-XXI' of FIG. 17.

22, 24, 26, 28, 30, 32, and 34 are layout views illustrating intermediate steps in the method of manufacturing the thin film transistor array panel of FIGS. 17 to 21.

23A, 23B and 23C are cross-sectional views taken along the lines XXIIIa-XXIIIa ', XXIIIb-XXIIIb', and XXIIIc-XXIIIc 'in FIG. 22,

25A, 25B and 25C are cross-sectional views taken along the lines XXVa-XXVa ', XXVb-XXVb', and XXVc-XXVc 'in FIG. 24,

27A, 27B, 27C, and 27D are cross-sectional views taken along lines XXVIIa-XXVIIa ', XXVIIb-XXVIIb', XXVIIc-XXVIIc ', and XXVIId-XXVIId' in FIG. 26,

29A, 29B, 29C, and 29D are cross-sectional views taken along the lines XXIXa-XXIXa ', XXIXb-XXIXb', XXIXc-XXIXc ', and XXIXd-XXIXd' in FIG. 28,

31A, 31B, 31C, and 31D are cross-sectional views taken along lines XXXIa-XXXIa ', XXXIb-XXXIb', XXXIc-XXXIc ', and XXXId-XXXId' in FIG. 30;

33A and 33B are cross-sectional views taken along the lines XXXIIIa-XXXIIIa 'and XXXIIIb-XXXIIIb' in FIG. 32,

35 and 36 are cross-sectional views of the thin film transistor array panel of FIG. 34 taken along lines XXXV-XXXV 'and XXXVI-XXXVI',

37 is a graph showing a change in specific resistance according to the deposition pressure of molybdenum alloy (MoNb),

38 is a graph showing a change in specific resistance according to niobium (Nb) addition amount,

39 is data showing the etching rate of pure molybdenum (Mo), niobium-added molybdenum alloy (MoNb), aluminum (Al) and neodymium-added aluminum alloy (AlNd),

40 is a photograph showing an etching state of a molybdenum (Mo) / aluminum (Al) / molybdenum (Mo) laminated film,

FIG. 41 is a photograph showing an etching state of a molybdenum alloy (MoNb) / aluminum (Al) / molybdenum (Mo) laminated film to which niobium is added.

<Code Description of Main Parts of Drawing>                 

110: insulating substrate 121: gate line

124: gate electrode 131: sustain electrode line

140: gate insulating film 150: intrinsic amorphous silicon layer

160: impurity amorphous silicon layer 171: data line

173: source electrode 175: drain electrode

177: conductor for holding capacitor 180: protective film

182, 185, 187, 189: contact 901: pixel electrode

906, 908: contact aid member

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel used in a thin film transistor liquid crystal display (TFT-LCD), an organic light emitting diode display (OLED), and the like, and more particularly, to a gate electrode in a stacked structure of a thin film transistor array panel. A thin film transistor array panel using a molybdenum alloy (Mo-alloy) having excellent low resistance and chemical resistance as a material of a data line including a gate line or a source electrode.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. The display device controls the amount of light transmitted by applying and rearranging liquid crystal molecules of the liquid crystal layer.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, the main structure is a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel, and one common electrode covers the entire surface of the display panel on another display panel. The display of an image in such a liquid crystal display is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. It is formed on the display panel. The thin film transistor serves as a switching element that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line. Such a thin film transistor also serves as a switching element for individually controlling each light emitting element in an active organic light emitting diode (AM-OLED) which is a self-luminous element.

In such a thin film transistor, chromium (Cr) has been mainly used as a material such as a gate line including a gate electrode, a data line including a source electrode, and a drain electrode.

However, chromium (Cr) has a high stress, and as the area of the liquid crystal display device becomes larger, the lengths of the gate lines and the data lines become longer, and thus the wirings need to be formed of a material having a low specific resistance. Chrome has high resistivity and is not suitable for use in large area liquid crystal displays.

Therefore, in order to overcome the above problem, although aluminum (Al) having a low specific resistance is known as a suitable metal to be applied to a large area liquid crystal display device, when the wiring is formed of aluminum, a hillock phenomenon occurs in a high temperature process. There is a problem. In addition, when aluminum is used as a data line, there is a problem that the characteristics of the thin film transistor are degraded due to a poor contact with the pixel electrode which is in contact with the semiconductor layer under the data line and diffuses into the semiconductor layer or contacts the data line. have.

Accordingly, an object of the present invention is to provide a thin film transistor array panel and a method for manufacturing the same, including wiring having low resistance and no problem in contact with a pixel electrode or a semiconductor layer.

In order to solve the above problems, at least one component selected from niobium (Nb), vanadium (V), and titanium (Ti) is added to molybdenum as a material of a gate line or a data line in a stacked structure of a display panel of a thin film transistor. Molybdenum alloy (Mo-alloy) is characterized by remarkably improving the low resistance and chemical resistance.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A method of manufacturing a liquid crystal display device or a thin film transistor array panel for an organic light emitting diode display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

Example 1

First, the structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line 121 protrudes downward to form a plurality of expansions 127.

The gate line 121 is formed on the first metal layer 124a made of aluminum (Al) or aluminum alloy (AlNd) in which neodymium (Nd) is added to aluminum, and is formed on the first metal layer 124a and molybdenum (Mo). And a second metal layer 124b made of molybdenum alloy to which at least one component selected from niobium (Nb), vanadium (V), and titanium (Ti) is added. The second metal layer 124b made of molybdenum alloy is laminated on the first metal layer 124a made of aluminum or an aluminum alloy to prevent hillock that may occur in the aluminum layer during a high temperature process. Here, niobium, vanadium or titanium in the molybdenum alloy is preferably added in an amount of about 0.1 to 10 at%, more preferably 3 to 8 at%. When the content of the additives is increased, it is possible to improve the adhesion or chemical resistance with other layers, but because it involves a problem of increasing the specific resistance, it is used by appropriate addition within the above range. Representatively, in FIG. 38, a change in specific resistance according to niobium (Nb) addition amount is shown. This shows that the resistivity gradually increases as the amount of niobium added increases. Therefore, it is preferable to use the molybdenum alloy of the said range in consideration of specific resistance, adhesiveness, and chemical resistance.

As such, when a predetermined amount of niobium, vanadium, or titanium, which forms a solid solution in molybdenum, is added, not only the chemical resistance (etch rate) is significantly improved, but also aluminum or aluminum formed at the bottom of the molybdenum (Mo). Due to the reduced chemical resistance difference with the alloy there is an advantage that undercut, overhang and mouse bite, etc. are not formed during etching. 39 shows molybdenum (Mo), molybdenum alloy (MoNb) in which a predetermined amount of niobium (Nb) is added to molybdenum, aluminum (Al), and aluminum alloy (AlNd) in which a small amount of neodymium (Nd) is added to aluminum. It is a result of measuring the etching rate (chemical resistance) at the time of etching using the same etching liquid. Looking at this, under the same conditions, the pure molybdenum metal layer (Mo) has an etching rate of about 170 kW / s, while the molybdenum alloy layer (MoNb) has an etching rate of about 44 kW / s, the about etch rate is about 1 / It can be seen that the decrease to 4. The etching rate of the molybdenum alloy (MoNb) layer is less than the etching rate of the aluminum metal layer (Al) (77 Å / s) and aluminum alloy layer (AlNd) (60 Å / s) than the pure molybdenum (Mo) As a result, problems such as undercuts and overhangs caused by etching differences can be remarkably improved than in the case of using a conventional pure molybdenum metal layer.

These results can be seen in FIGS. 40 and 41 observed with a scanning electron microscope (SEM).

FIG. 40 shows a profile obtained by etching a molybdenum (Mo) / aluminum (Al) / molybdenum (Mo) layer with an etchant, (a) shows 67% phosphoric acid, 6% nitric acid, 10% acetic acid, and demineralized water. In case of etching with integrated etching solution containing 17%, (b) is etching with Al etching solution containing 67% phosphoric acid, 13% nitric acid, 15% acetic acid and 5% demineralized water. FIG. 41 shows a profile obtained by etching a molybdenum alloy (MoNb) / aluminum (Al) / molybdenum alloy (MoNb) layer with an etchant, (a) shows 67% phosphoric acid, 13% nitric acid, 15% acetic acid, and demineralized water 5 In case of etching with Al etching solution containing%, (b) is etching with integrated etching solution containing 67% phosphoric acid, 6% nitric acid, 10% acetic acid and 17% demineralized water.

Comparing FIGS. 40 and 41, it can be seen that the undercut shown in FIG. 40 does not appear in FIG. 41. As shown in FIG. 39, the difference in the etching rates of niobium-containing molybdenum alloys (MoNb) and aluminum (Al, AlNd) was significantly higher than that of pure molybdenum (Mo) and aluminum (Al, AlNd). This is a result due to the reduction.

Side surfaces of the first metal layer 124a and the second metal layer 124b are inclined, respectively, and the inclination angle is about 30 to 80 degrees with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140. The linear semiconductor layer 151 extends in the vertical direction, from which a plurality of extensions 154 extend toward the gate electrode 124. Further, the linear semiconductor layer 151 increases in width near the point where the linear semiconductor layer 151 meets the gate line 121 to cover a large area of the gate line 121.

A plurality of island-like ohmic contacts 163 and 165 formed of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor layer 151. . The ohmic contacts 163 and 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151. Side surfaces of the semiconductor layer 151 and the ohmic contacts 163 and 165 are also inclined, and the inclination angle is 30 to 80 ° with respect to the substrate 110.

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitors are disposed on the ohmic contacts 163 and 165 and the gate insulating layer 140, respectively. conductor 177 is formed.

The data line 171 extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124.

The data lines 171 and 175 and the drain electrode 175 including the source electrode 173 include first metal layers 171b and 175b including aluminum and molybdenum formed under and over the first metal layer. It is formed of a plurality of layers consisting of second metal layers 171a and 175a and third metal layers 171c and 175c, and the second metal layers 171a and 175a and the third metal layers 171c and 175c are formed of niobium (Nb) in molybdenum. And at least one component selected from vanadium (V) and titanium (Ti) is formed of molybdenum alloys (Mo-Nd, Mo-V, Mo-Ti) to which a predetermined amount is added. Here, niobium, vanadium or titanium in the molybdenum alloy is preferably added in an amount of about 0.1 to 10 at%, more preferably 3 to 8 at%. Increasing the content of the additive components may improve the adhesion or chemical resistance with other layers, but because it involves a problem of increasing the specific resistance, it is appropriately added within the above range.

As described above, using a molybdenum alloy in which at least one of niobium (Nb), vanadium (V) and titanium (Ti) forming a molybdenum and an electrolytic solid solution is added to molybdenum, a structure is laminated on the upper and / or lower part of the aluminum. By forming, not only the chemical resistance (etching speed) is significantly improved compared to the case of using molybdenum (Mo), but also the difference in chemical resistance with aluminum or aluminum alloy is reduced to form undercut, overhang, and mouse bite during etching. There is no advantage. 39 shows molybdenum (Mo), molybdenum alloy (MoNb) in which niobium (Nb) is added to molybdenum, aluminum (Al), and aluminum alloy (AlNd) in which a small amount of neodymium (Nd) is added to aluminum. In the case of etching using the same etching solution, the etching rate (chemical resistance) is measured. In view of this, under the same conditions, the pure molybdenum metal layer (Al) has an etching rate of about 170 kW / s, while the molybdenum alloy layer (MoNd) has an etching rate of about 44 kW / s, and thus decreases to about 1/4. It can be seen. Since the molybdenum alloy layer reduces the etching rate difference with the aluminum metal layer (Al) (77 kW / s) or the aluminum alloy layer (AlNd) (60 kW / s) than the pure molybdenum metal layer, the conventional pure molybdenum metal layer Compared to the case of using, it is possible to significantly improve problems such as undercuts and overhangs caused by etching differences. These results can be seen in FIGS. 40 and 41, which is due to the remarkable improvement in the etching rate difference between the molybdenum alloy and aluminum to which niobium is added, compared to the etching rate difference between pure molybdenum metal and aluminum.

In addition, the aluminum or aluminum alloy layer having a low specific resistance is interposed between the molybdenum alloy layers, so that the aluminum layer interposed therebetween is directly connected with the lower semiconductor layer and the upper pixel electrode while maintaining the low specific resistance. There is also an advantage that can prevent the degradation of the characteristics of the thin film transistor due to poor contact by not contacting.

The gate electrode 124, the source electrode 173, and the drain electrode 175 together with the protrusion 154 of the semiconductor 151 form a thin film transistor (TFT), and a channel of the thin film transistor The protrusion 154 is formed between the source electrode 173 and the drain electrode 175. The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

Similarly to the gate line 121, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are also inclined at an angle of about 30 to 80 ° with respect to the substrate 110.

The ohmic contacts 163 and 165 exist only between the semiconductor layer 154 below and the source electrode 173 and the drain electrode 175 thereon, and serve to lower the contact resistance. The linear semiconductor layer 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and is not covered by the data line 171 and the drain electrode 175, and in most regions, the linear semiconductor layer ( Although the width of the 151 is smaller than the width of the data line 171, as described above, the width of the 151 is increased at the portion where the gate line 121 meets, thereby increasing the insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, the conductive capacitor 177 for the storage capacitor, and the exposed semiconductor layer 151, an organic material having excellent planarization characteristics and photosensitivity, plasma chemical vapor deposition ( Plasma Enhanced Chemical Vapor Deposition (PECVD), a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or a passivation layer 180 made of an inorganic material such as silicon nitride It is formed of a single layer or a plurality of layers. For example, when formed of an organic material, a portion of the semiconductor layer 154 between the source electrode 173 and the drain electrode 175 is exposed to prevent the organic material of the passivation layer 180 from contacting the lower portion of the organic layer. An insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO 2 ) may be further formed.

In the passivation layer 180, a plurality of contact holes 185, 187, and 182 exposing end portions of the drain electrode 175, the storage capacitor conductor 177, and the data line 171 are formed. .

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive the data voltage from the drain electrode 175 and to maintain the storage capacitor. The data voltage is transmitted to the existing conductor 177.                     

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a liquid crystal capacitor to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with the capacitor, which is called the "storage electrode". The storage capacitor is formed by overlapping the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a "previous gate line"), and the like, to increase the capacitance of the storage capacitor, that is, the storage capacitor. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer.

When the passivation layer 180 is formed of a low dielectric constant organic material, the aperture ratio may be increased by overlapping the pixel electrode 190 with the neighboring gate line 121 and the data line 171.

The contact auxiliary members 82 are connected to ends of the data line 171 through the contact holes 182, respectively. The contact assisting member 82 compensates for and protects the adhesion between the end portion of the data line 171 and an external device such as a driving integrated circuit.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display shown in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 6B and FIGS. 1 and 2.

3A, 4A, 5A, and 6A are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to the first embodiment of the present invention. 3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 3A, FIG. 4B is a cross-sectional view taken along the line IVb-IVb' of FIG. 4A, and FIG. 5B is a line taken along the line Vb-Vb 'of FIG. 5A. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A.

First, as shown in FIGS. 3A and 3B, a metal layer is formed on an insulating substrate 110 such as transparent glass.

The metal layer is formed by co-sputtering. In the embodiment of the present invention, as a target of the cavity sputtering, an aluminum alloy in which neodymium (Nd) is added to aluminum or aluminum and a molybdenum alloy in which niobium, vanadium or titanium is added to molybdenum are used. Herein, the aluminum alloy preferably uses an Al-Nd sputtering target containing about 2 at% of Nd, and the molybdenum alloy preferably contains niobium, vanadium or titanium, preferably about 0.1 to 10 at%, and more preferably 3 to 8 at%. Mo-Nd, Mo-V or Mo-Ti sputtering targets added in the content of are used. In the case of increasing the content of the additives in the molybdenum alloy, although the adhesion or chemical resistance with other layers may be improved, it is accompanied by the problem of increasing the specific resistance, so that the appropriately added within the above range is used.                     

The joint sputtering proceeds in the following manner.

Initially, no power is applied to the molybdenum alloy target, and only power is applied to the aluminum or aluminum alloy target to form a first metal layer 124a made of aluminum or an aluminum alloy on the substrate. In this case, it is desirable to have a thickness of about 2,500 kPa. Then, after the power applied to the aluminum target is turned off, the power applied to the molybdenum alloy is applied to form the second metal layer 124b.

Thereafter, the first metal layer 124a and the second metal layer 124b are etched at once to form the gate line 121 including the plurality of gate electrodes 124 and the plurality of extension parts 127. At this time, an etchant containing phosphoric acid, nitric acid, acetic acid, and demineralized water in an appropriate ratio is suitable. Specifically, 63-70% phosphoric acid, 4-8% nitric acid, 8-11% acetic acid, and residual demineralized water are used. An integrated etchant including or an etchant containing an acetic acid content of about 4-8% increased than the etchant may be used.

Next, as illustrated in FIGS. 4A and 4B, the gate insulating layer 140 is formed by depositing silicon nitride (SiNx) or silicon oxide (SiO 2 ) to cover the gate line 121 and the gate electrode 124. The stacking temperature of the gate insulating layer 140 is preferably about 250-500 ° C., and the thickness is about 2,000-5,000 Pa.

A three-layer film of intrinsic amorphous silicon and an impurity doped amorphous silicon layer is sequentially stacked on the gate insulating layer 140, and an amorphous silicon layer and an intrinsic amorphous silicon layer doped with impurities are formed. Photolithography is performed to form the linear intrinsic semiconductor layer 151 each including a plurality of protrusions 154 and a plurality of impurity semiconductor patterns 164.

Next, as shown in FIGS. 5A and 5B, the first metal layers 171a, 173a, 175a, and 177a including molybdenum may be formed on the amorphous silicon layer 161 doped with impurities by sputtering or the like. Third metal layers 171c, 173c, 175c, and 177c including second metal layers 171b, 173b, 175b, and 177b and molybdenum are sequentially deposited, and the first metal layers 171a, 173a, 175a, and 177a and the third metal layer are deposited. The metal layers 171c, 173c, 175c, and 177c are formed of a molybdenum alloy to which molybdenum is added at least one component selected from niobium (Nb), vanadium (V), and titanium (Ti). Here, one of the second metal layer and the third metal layer may be made of another material. The metal layer is formed to have a thickness of about 3000 Pa by combining all of the first metal layer, the second metal layer, and the third metal layer, and the sputtering temperature is preferably about 150 ° C.

Next, the laminated film is patterned with an etchant to form a source electrode 173, a drain electrode 175, and a storage capacitor conductor 177. Here, preferably, an etching solution containing phosphoric acid, nitric acid, acetic acid, and demineralized water in an appropriate ratio is used, and more preferably, 63-70% phosphoric acid, 4-8% nitric acid, 8-11% acetic acid, and a residual amount of demineralized water. An integrated etchant or an Al etchant having an acetic acid content of about 4-8% increased than the etchant may be used.

Subsequently, portions of the impurity semiconductor layers 161163 and 165 that are not covered by the source electrode 173, the drain electrode 175, and the storage capacitor conductor 177 are removed to include the plurality of protrusions 163, respectively. The plurality of linear ohmic contacts 161163 and the plurality of island resistive contact layers 165 are completed, while the portion of the intrinsic semiconductor 154 beneath it is exposed. In this case, it is preferable to perform oxygen (O 2 ) plasma to stabilize the surface of the exposed intrinsic semiconductor 154.

Next, as illustrated in FIGS. 6A and 6B, organic materials having excellent planarization characteristics and photosensitivity, a-Si: C: O, a formed by plasma enhanced chemical vapor deposition (PECVD) A low dielectric constant insulating material such as Si: O: F, or silicon nitride (SiNx), which is an inorganic material, is formed in a single layer or in a plurality of layers to form a passivation layer.

Then, after the photoresist is coated on the passivation layer 180, the photoresist is irradiated with light through a photomask and developed to form a plurality of contact holes 185, 187, and 182. In this case, in the case of the organic film having photosensitivity, the contact hole may be formed only by a photolithography process, and the gate opening 140 and the passivation layer 180 may be formed under etching conditions having substantially the same etching ratio.

Next, as shown in FIGS. 1 and 2, ITO or IZO is stacked on the substrate by sputtering, and a plurality of pixel electrodes 190 and a plurality of contact assistants 82 are formed by a photolithography process.

In the present embodiment, only the case where the gate line 121 and the data line 171 are formed of a plurality of layers made of a layer containing aluminum and a layer containing molybdenum is shown, but the gate line 121 and the data line 171 It can also form in multiple layers only in any one layer.

[Example 2]

In Example 1, a method of forming the semiconductor layer and the data line by a photolithography process using different masks has been described. It applies to the manufacturing method of the thin film transistor array panel for liquid crystal display devices formed by a photolithography process. This will be described in detail with reference to the drawings.

FIG. 7 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 8 is a cross-sectional view taken along the line VIII-VIII ′ of FIG. 7.

As shown in Fig. 7 and Fig. 8, the layer structure of the thin film transistor array panel for the liquid crystal display device according to the present embodiment is almost the same as the layer structure of the thin film transistor array panel for the liquid crystal display device shown in Figs. . That is, the first metal layers 121a and 124a including aluminum on the insulating substrate 110 and a second metal layer made of a molybdenum alloy in which niobium (Nb), vanadium (V), or titanium (Ti) is added to molybdenum in a predetermined amount ( A plurality of gate lines 121 including 121b and 124b are formed, a plurality of linear semiconductor layers 151 including a gate insulating layer 140, a plurality of protrusions 154, and a plurality of protrusions 163 thereon. A plurality of linear ohmic contact layers 161163 and a plurality of island-type ohmic contact layers 165 each including N-A are sequentially formed. The first metal layers 171b and 175b including aluminum and the second metal layers 171a and 175a including molybdenum formed below and on the first metal layer are formed on the ohmic contacts 161163 and 165 and the gate insulating layer 140. And a plurality of data lines 171 and drain electrodes 175 formed of third metal layers 171c and 175c, and a passivation layer 180 formed thereon. A plurality of contact holes 182 and 185 are formed in the passivation layer 180 and / or the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact assistants 82 are formed on the passivation layer 180. It is.

However, unlike the thin film transistor array panel shown in FIGS. 1 and 2, the thin film transistor array panel according to the present exemplary embodiment has the gate line 121 and the gate line 121 on the same layer as the gate line 121 instead of the extension part on the gate line 121. A plurality of electrically separated storage electrode lines 131 are provided to overlap the drain electrode 175 to form a storage capacitor. The storage electrode line 131 receives a predetermined voltage such as a common voltage from the outside, and the storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap of the pixel electrode 190 and the gate line 121 is sufficient. In order to maximize the aperture ratio of the pixel, the pixel may be disposed at an edge of the pixel area.

The semiconductor layer 151 has a planar shape substantially the same as the data line 171, the drain electrode 175, and the ohmic contact layers 161163 and 165 except the protrusion 154 where the thin film transistor is located. have. Specifically, the linear semiconductor layer 151 may include the source electrode 173 and the drain electrode (aside from the data line 171 and the drain electrode 175 and the portions below the ohmic contacts 161163 and 165 below). 175) has exposed portions between them.

Next, a method of manufacturing the thin film transistor array panel according to the present embodiment will be described in detail with reference to FIGS. 9A to 13B and FIGS. 7 and 8.                     

First, the metal layers 121b and 124b including the aluminum or aluminum alloy layers 121a and 124a on the insulating substrate 110 made of transparent glass and a molybdenum alloy layer in which niobium, vanadium or titanium is added to molybdenum or molybdenum in a predetermined amount. Are formed by a sputtering method and then patterned to form a gate line 121 including a plurality of gate electrodes 124, and a plurality of sustain electrode lines 131 electrically separated from the gate line 121.

Next, as shown in FIG. 10, an insulating material such as silicon nitride (SiNx) covering the gate line 121 is deposited to form the gate insulating layer 140. Then, an intrinsic amorphous silicon (a-Si) without impurities and an amorphous silicon (n + a-Si) doped with impurities are deposited on the gate insulating layer 140 to form an intrinsic amorphous silicon layer 151 and doped with impurities. The amorphous silicon layer 161 is sequentially stacked. The intrinsic amorphous silicon layer 151 is formed of hydrogenated amorphous silicon, and the like, and the doped amorphous silicon layer 161 is made of amorphous silicon or silicide doped with a high concentration of n-type impurities such as phosphorus (P). Form.

Then, on the amorphous silicon layer 161 doped with impurities, a first metal layer 171a including molybdenum, a second metal layer 171b including aluminum, and a third metal layer 171c including molybdenum by sputtering or the like. The first metal layer 171a and the third metal layer 171c are sequentially formed of a molybdenum alloy in which at least one component selected from niobium (Nb), vanadium (V), and titanium (Ti) is added to molybdenum. do. Here, one of the first metal layer and the third metal layer may be formed of molybdenum (Mo) alone or another material. Then, the layered film is patterned with an etchant, preferably an etchant containing phosphoric acid, nitric acid, acetic acid and demineralized water in an appropriate ratio, more preferably 63-70% phosphoric acid, 4-8% nitric acid, 8-acetic acid An integrated etchant including 11% and residual demineralized water or an Al etchant having an acetic acid content of about 4-8% increased from the etchant may be used.

Thereafter, a photoresist film is formed on the third metal layer 171c, followed by exposure and development to form photoresist patterns 52 and 54 having different thicknesses.

For convenience of description, the metal layer 171 of the portion where the wiring is to be formed, the amorphous silicon layer 160 doped with impurities, and the intrinsic amorphous silicon layer 150 without doping impurities are referred to as the wiring portion A, and the channel The portions of the impurity doped amorphous silicon layer 161 and the intrinsic amorphous silicon layer 151 located at the portion where the portions are formed are referred to as channel portions B, and the amorphous silicon doped with impurities located in regions other than the channel and wiring portions are referred to as channel portions B. The portion of layer 161 and intrinsic amorphous silicon layer 151 is referred to as the other portion (C).

The first portion 54 of the photoresist patterns 52 and 54 positioned in the channel portion B of the thin film transistor is smaller in thickness than the portion positioned in the portion A in which the data line is to be formed. Remove all photoresist. At this time, the ratio of the thickness of the photoresist film 54 remaining in the channel portion B and the thickness of the photoresist film 52 remaining in the portion A should be different depending on the process conditions in the etching process, which will be described later. It is preferable to make the thickness of 54) 1/2 or less of the thickness of the second part 52.

As described above, there may be various methods of varying the thickness of the photoresist layer according to the position, and the semi-transparent area as well as the transparent area and the light blocking area in the exposure mask. For example. The semi-transmissive region includes a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Given the appropriate process conditions, the lower layers may be selectively etched due to the difference in thickness of the photoresist patterns 52 and 54. Accordingly, a plurality of data lines 171 and a plurality of drain electrodes 175 each including a plurality of source electrodes 173 as shown in FIGS. 12A and 12B are formed through a series of etching steps, and a plurality of protrusions ( A plurality of linear ohmic contacts 161 each including 163, a plurality of island-like ohmic contacts 165, and a plurality of linear semiconductor layers 151 including a plurality of protrusions 154 are formed.

An example of the procedure for forming such a structure is as follows.

As shown in FIG. 11, the metal layer 171 exposed to the other region C is removed by wet etching or dry etching to remove the other portion C of the amorphous silicon layer 161 doped with impurities thereunder. Expose

Next, the amorphous silicon layer 161 doped with impurities located in the other portion C and the intrinsic amorphous silicon layer 151 thereunder are removed, and the photoresist film 54 of the channel portion B is removed to remove the lower portion. The metal layer 174 is exposed.

Removal of the photoresist of the channel portion B may be performed simultaneously with or separately from the removal of the amorphous silicon layer 161 and the intrinsic amorphous silicon layer 151 doped with impurities of the other region C. Residue of the photoresist film 54 remaining in the channel region B is removed by ashing. In this step, the semiconductor layers 151 and 154 are completed.

Here, when the metal layer 171 is a material capable of dry etching, the manufacturing process may be simplified by continuously dry etching the amorphous silicon layer 161 and the intrinsic amorphous silicon layer 151 doped with impurities thereunder. In this case, the same etching chamber may be performed by an in-situ method of continuously performing dry etching on the three layers 171, 161, and 151, but it is not necessary to continuously perform the etching.

12A and 12B, the metal layer 174 located in the channel portion B and the amorphous silicon layer 164 doped with impurities are etched away. In addition, the photosensitive film 52 of the remaining wiring portion A is also removed.

In this case, the upper portion of the intrinsic amorphous silicon layer 154 positioned in the channel portion B may be partially removed to reduce the thickness, and the photosensitive film 52 of the wiring portion A may be etched to some extent.

In this case, each of the metal layers 174 is completed while being separated into one data line 171 including the source electrode 173 and the plurality of drain electrodes 175, and the amorphous silicon layer 164 doped with impurities is also linearly resistive. The contact layer 161 and the island-like resistive contact layer 165 are divided and completed.

Next, as shown in FIGS. 13A and 13B, the passivation layer 180 is formed to cover the semiconductor layer 154 that is not covered by the data lines 171 and 173 and the drain electrode 175. In this case, the passivation layer 180 may be formed of a-Si: C: O, a-Si: O: organic material having excellent planarization characteristics, photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). A low dielectric constant insulating material, such as F, or silicon nitride, which is an inorganic material, is formed in a single layer or a plurality of layers to form a passivation layer.

Then, the passivation layer 180 is formed by a photolithography process to form a plurality of contact holes 185 and 182. In this case, in the case of the organic film having photosensitivity, the contact hole may be formed only by a photographic process.

7 and 8, a transparent conductive material such as ITO or IZO is deposited on the substrate 110 and etched by a photolithography process using a mask to form a gate line through the contact holes 185 and 182. And a pixel electrode 190 connected to the drain electrode 175 through a contact auxiliary member 82 and a contact hole 185 respectively connected to one end of the data line.

In the present embodiment, only the case where the gate line 121 and the data line 171 are formed of a plurality of layers made of a layer containing aluminum and a layer containing molybdenum is shown, but the gate line 121 and the data line 171 It can also form in multiple layers only in any one layer.                     

Example 3

In this embodiment, a color filter is further added to the above-described embodiment of the thin film transistor array panel.

14A is a layout view of a thin film transistor array panel according to the exemplary embodiment, and FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb ′ of FIG. 14A.

A plurality of gate lines 121 for transmitting a gate signal are formed on the insulating substrate 110. The gate line 121 extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124.

The gate line 121 is formed on the first metal layer 124a made of aluminum (Al) or aluminum alloy (AlNd) in which neodymium (Nd) is added to aluminum, and is formed on the first metal layer 124a and molybdenum (Mo). It is composed of a second metal layer 124b made of molybdenum alloys (Mo-Nb, Mo-V, Mo-Ti) to which at least one component selected from niobium (Nb), vanadium (V), and titanium (Ti) is added. . As described above, when the molybdenum alloy in which niobium, vanadium, or titanium is added to molybdenum is formed on the first metal layer 124a, the etching rate difference between the molybdenum alloy and aluminum is smaller than that of the pure molybdenum metal layer. Undercut or overhang does not occur (see FIGS. 40 and 41), and a hillock phenomenon that may occur in the aluminum layer during a high temperature process may be prevented. Here, niobium, vanadium or titanium in the molybdenum alloy is preferably added in an amount of about 0.1 to 10 at%, more preferably 3 to 8 at%. In the case of increasing the content of the additives, although the adhesion or chemical resistance with other layers may be improved, it is accompanied by the problem of increasing the specific resistance, so that the appropriately added within the above range is used. Typically, FIG. 38 shows the correlation between niobium (Nb) addition amount and specific resistance. It can be seen that the specific resistance is almost linearly proportional to the amount of niobium added. Therefore, it is preferable to use the molybdenum alloy of the said range in consideration of specific resistance, adhesiveness, and chemical resistance.

Next, the first metal layer 124a and the second metal layer 124b are etched at once.

Side surfaces of the first metal layer 124a and the second metal layer 124b are inclined, respectively, and the inclination angle is about 30 to 80 degrees with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140. The linear semiconductor layer 151 extends in the vertical direction, from which a plurality of extensions 154 extend toward the gate electrode 124. In addition, the linear semiconductor layer 151 increases in width near the point where it meets the gate line 121 to cover a large area of the gate line 121.

A plurality of island type ohmic contact layers 163 and 165 formed of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor layer 151. The ohmic contacts 163 and 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151. Side surfaces of the semiconductor layer 151 and the ohmic contacts 163 and 165 are also inclined, and the inclination angle is 30 to 80 ° with respect to the substrate 110.

A plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of storage capacitor conductors 177 are formed on the ohmic contacts 163 and 165 and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 to transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms the source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124.

The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175. The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor may be formed of a metal layer such as an aluminum-based metal such as chromium, titanium, silver, molybdenum tantalum, aluminum (Al), or an aluminum alloy. In addition to these metal layers, metal layers such as aluminum and aluminum alloys, such as aluminum and aluminum alloys, may be used in addition to chromium (Cr), titanium (Ti), tantalum (Ta), which have good physical, chemical and electrical contact with other materials, especially ITO or IZO. A multi-layered film structure composed of molybdenum (Mo) and alloys thereof may be formed to have a mixed layer like a gate line. However, preferably, as in the first and second embodiments, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 include the first metal layers 171b, 175b, and 177b including aluminum. And second metal layers 171a, 175a, and 177a including molybdenum formed on the lower and upper portions of the first metal layers 171b, 175b, and 177b, and a third metal layer 171c, 175c, and 177c. In this case, the second metal layers 171a, 175a, and 177a and the third metal layers 171c, 175c, and 177c may include at least one of niobium (Nb), vanadium (V), and titanium (Ti) in molybdenum. It can be formed from molybdenum alloys (Mo-Nb, Mo-V, Mo-Ti) added in a predetermined content. Here, one of the second metal layer and the third metal layer may be formed of molybdenum only or made of another material. Niobium, vanadium or titanium in the molybdenum alloy is preferably added in an amount of about 0.1 to 10 at%, more preferably 3 to 8 at%. Increasing the content of the additives may improve the adhesion or chemical resistance with other layers, but the use of an appropriately added within the above range because it involves a problem of increasing the specific resistance. Molybdenum is formed by forming a structure in which at least one of niobium (Nb), vanadium (V), and titanium (Ti) forming molybdenum and an electrolytic solid solution is laminated on the upper and lower portions of the aluminum by using a molybdenum alloy added to molybdenum. The chemical resistance (etching speed) is significantly improved compared to the case of using (Mo), and the difference in chemical resistance with aluminum or aluminum alloy is reduced, so that undercut, overhang, and mouth bite are not formed during etching.

Similar to the gate line 121, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are also inclined with respect to the substrate 110 at an angle of about 30 to 80 °.

The ohmic contacts 163 and 165 exist only between the semiconductor layer 154 below and the source electrode 173 and the drain electrode 175 thereon, and serve to lower the contact resistance. The linear semiconductor layer 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and is not covered by the data line 171 and the drain electrode 175, and in most regions, the linear semiconductor layer ( Although the width of the 151 is smaller than the width of the data line 171, as described above, the width of the 151 is increased at the portion where the gate line 121 meets, thereby increasing the insulation between the gate line 121 and the data line 171.

Unlike the first and second embodiments, the color filters 230R, 230G, and 230B are formed on the data line 171, the drain electrode 175, and the storage capacitor conductor 177. The color filters 230R, 230G, and 230B extend the red, green, and blue color filters 230R, 230G, and 230B in a direction parallel to the data line 171 along the pixel column defined by the data line 171. Are alternately formed in the pixel column.

Here, the red, green, and blue color filters 230R, 230G, and 230B are not formed at the end of the gate line 121 or the data line 171 to be connected to the external circuit. The edges of the color filters 230R, 230G, and 230B overlap the upper portion of the data line 171. As such, the edges of the color filters 230R, 230G, and 230B are formed to overlap each other to block light leakage between the pixel areas, and the red, green, and blue color filters are combined at the upper portion of the data line 171. It can also be arranged in an overlap.

Further, interlayer insulating films 801 and 802 are further formed below or above the color filters 230R, 230G, and 230B. The interlayer insulating films 801 and 802 prevent the pigments of the color filters 230R, 230G, and 230B from entering the semiconductor layer 154 or the pixel electrode 190.

The interlayer insulating films 801 and 802 may be formed of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic nitride such as silicon nitride formed by plasma chemical vapor deposition.

As such, when the color filter is formed on the thin film transistor array panel, a black matrix may be formed only on the thin film transistor array panel on the upper panel, so that the aperture ratio of the pixel may be increased.

The upper interlayer insulating layer 802 is provided with a plurality of contact holes 185, 187, and 182 that expose the drain electrode 175, the storage capacitor conductor 177, and the ends of the data line 171, respectively.

In addition, a plurality of pixel electrodes 190 made of ITO or IZO and a plurality of contact assistants 82 are formed on the upper interlayer insulating layer 180 to form drain electrodes through the contact holes 185, 187, and 182. 175 is in contact with the storage capacitor conductor 177 and the data line 171.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive the data voltage from the drain electrode 175 and to maintain the storage capacitor. The data voltage is transmitted to the existing conductor 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which the common voltage is applied.

The contact auxiliary members 82 are connected to ends of the data line 171 through the contact holes 182, respectively. The contact assisting member 82 compensates for and protects the adhesion between the end portion of the data line 171 and an external device such as a driving integrated circuit.

Hereinafter, a method of manufacturing the thin film transistor array panel according to the present embodiment will be described.

First, as shown in FIGS. 15A and 15B, a gate made of a molybdenum alloy layer 124b to which a predetermined amount of aluminum or aluminum alloy layer 124a, niobium, vanadium, or titanium is added on an insulating substrate 110 made of transparent glass. A line 121 is formed. The gate insulating layer 140, the semiconductor layers 151 and 154, the ohmic contact layers 161, 163 and 165, the data line 171 and the drain electrode 175 are formed on the gate lines 121 and 124.

Then, the photosensitive organic materials including red, green, and blue pigments are applied in turn, and the red, green, and blue color filters 230R, 230G, and 230B are sequentially formed through respective photographic processes. In this case, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiO 2 ) may be stacked to form an interlayer insulating film 801, and then a color filter may be formed. The interlayer insulating layer 801 serves to protect the semiconductor layers 151 and 154 from the pigment of the color filter.

When the red, green, and blue color filters 230R, 230G, and 230B are formed by a photo process using a mask, openings 235 and 237 are formed in portions corresponding to the drain electrode 175 and the conductive capacitor conductor 177. Form.

Thereafter, as shown in FIGS. 16A and 16B, an interlayer insulating film 802 is formed by applying an organic material having a low dielectric constant of 4.0 or less on the color filters 230R, 230G, and 230B.

Then, the interlayer insulating layer 802 is patterned by a photolithography process using a mask to form contact holes 182, 185, and 187 exposing the openings 235 and 237.

14B, a transparent conductive material such as ITO or IZO is deposited on the substrate 110, and the drain electrode 175 is formed through the openings 235 and 237 and the contact holes 185 and 187 by a photolithography process. The pixel electrode 190 is connected to the pixel electrode 190.

In the present embodiment, only the case where the gate line 121 and the data line 171 are formed of a plurality of layers made of a layer containing aluminum and a layer containing molybdenum is shown, but the gate line 121 and the data line 171 It can also form in multiple layers only in any one layer.

Example 4

In the present embodiment, a thin film transistor array panel for an active organic light emitting display (AM-OLED) will be described.

17 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment, and FIGS. 18 and 19 are cross-sectional views taken along lines XVIII-XVIII 'and XIX-XIX' of FIG. 17, respectively. 20 and 21 are cross-sectional views taken along the lines XX-XX 'and XXI-XXI' of FIG. 17.                     

A plurality of gate lines 121 for transmitting a gate signal are formed on the insulating substrate 110. The gate line 121 extends in the horizontal direction, and a portion of each gate line 121 protrudes to form a plurality of first gate electrodes 124a. In addition, the second gate electrode 124b is formed on the same layer as the gate line 121, and the storage electrode 133 extending in the vertical direction is connected to the second gate electrode 124b.

The gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133 may be formed of two films having different physical properties. The lower metal layers 124a 'and 124b' are aluminum series such as aluminum alloys having low resistivity, such as aluminum (Al) or metal alloys such as neodymium (Nd), which can reduce the delay or voltage drop of the gate signal. It is preferable that it consists of a metal. The upper metal layers 124a "and 124b" have an excellent electrical contact with other materials, particularly ITO or IZO, from the lower metal layers 124a 'and 124b', and the etching speed of aluminum and the lower metal layers 124a 'and 124b'. Are materials that do not differ significantly, and molybdenum alloys (Mo-Nb, MoV) containing a predetermined amount of niobium (Nb), vanadium (V), or titanium (Ti) in molybdenum (Mo) , MoTi). Here, niobium, vanadium or titanium in the molybdenum alloy is preferably added in an amount of about 0.1 to 10 at%, more preferably 3 to 8 at%. When the content of the additives is further increased, the adhesion or chemical resistance with other layers may be improved, but it is appropriately added within the above range because it involves a problem of increasing specific resistance.

Side surfaces of the gate line 121 and the storage electrode 133 are inclined, and the inclination angle is 30-80 degrees with respect to the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 and island semiconductors 154b made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends in the vertical direction, from which a plurality of extensions extend toward the first gate electrode 124a to form a first channel portion 154a overlapping the first gate electrode 124a. have. In addition, the width of the linear semiconductor 151 extends near a point where the linear semiconductor 151 meets the gate line 121. The island-like semiconductor 154b includes a second channel portion crossing the second gate electrode 124b and has a storage electrode portion 157 overlapping the storage electrode 133.

On the top of the linear semiconductor 151 and the island-like semiconductor 154b, a plurality of linear and island resistive contact layers 161 and 165a made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration. 163b and 165b are formed. The linear contact layer 161 has a plurality of protrusions 163a, and the protrusions 163a and the island contact layer 165a are paired and positioned on the protrusions 154a of the linear semiconductor 151. In addition, the island contact layers 163b and 165b are paired to face the second gate electrode 124b and positioned on the island semiconductor 154b.

Sides of the semiconductors 151 and 154b and the ohmic contacts 161, 165a, 163b and 165b are also inclined and have an inclination angle of 30 to 80 degrees.

The plurality of data lines 171, the plurality of first drain electrodes 175a, the plurality of power lines 172, and the second drain electrodes are disposed on the ohmic contacts 161, 165a, 163b, and 165b and the gate insulating layer 140, respectively. 175b is formed.

The data line 171 and the power supply line 172 extend in the vertical direction to intersect the gate line 121 to transfer the data voltage and the power supply voltage, respectively. A plurality of branches extending from the data line 171 toward the first drain electrode 175a forms the first source electrode 173a and a plurality of branches extending from the power supply line 172 toward the second drain electrode 175b. Forms a second source electrode 173b. The pair of first and second source electrodes 173a and 173b and the first and second drain electrodes 175a and 175b are separated from each other and opposite to each other with respect to the first and second gate electrodes 124a and 124b, respectively. Located in

The first gate electrode 124a, the first source electrode 173a, and the first drain electrode 175a together with the protrusion 154a of the linear semiconductor 151 form a switching thin film transistor, and the second gate electrode 124b, the second source electrode 173b, and the second drain electrode 175b together with the island-like semiconductor 154b form a thin film transistor for driving. At this time, the power supply line 172 overlaps the sustain electrode portion 157 of the island-like semiconductor 154b.

The data line 171, the first and second drain electrodes 175a and 175b, and the power supply line 172 are preferably formed in a three-layered laminated structure, and include the first metal layer 171b including aluminum and the metal layer. It is formed of a second metal layer 171a and a third metal layer 171c including molybdenum (Mo) formed at upper and lower portions thereof. The second metal layer 171a and the third metal layer 171c including the molybdenum may be formed of a molybdenum alloy containing at least one of niobium (Nb) and titanium (Ti) of vanadium (V) in molybdenum (Mo). Here, one of the second metal layer and the third metal layer may be formed of molybdenum alone or made of another material. Niobium, vanadium or titanium in the molybdenum alloy is preferably added in an amount of about 0.1 to 10 at%, more preferably 3 to 8 at%. Increasing the content of the additives may improve the adhesion or chemical resistance with other layers, but the use of an appropriately added within the above range because it involves a problem of increasing the specific resistance. As such, by forming a structure in which at least one of niobium (Nb), vanadium (V), and titanium (Ti) forming molybdenum and an electrolytic solid solution is laminated on the upper and lower portions of the aluminum by using a molybdenum alloy added to molybdenum, Not only the chemical resistance (etching speed) is significantly improved compared to conventional molybdenum (Mo), but also the difference in chemical resistance with aluminum or aluminum alloy is reduced, so undercut, overhang and mouse bite are not formed during etching. There is this.

Like the gate line 121, the data line 171, the first and second drain electrodes 175a and 175b, and the power supply line 172 are inclined at an angle of about 30 to 80 degrees, respectively.

The ohmic contacts 161, 163b, 165a, and 165b include a linear semiconductor 151 and an island semiconductor 154b at a lower portion thereof, a data line 171 at an upper portion thereof, a first drain electrode 175a and 175b, and a power supply line ( It exists only between 172) and serves to lower the contact resistance. The linear semiconductor 151 has a portion exposed between the first source electrode 173a and the first drain electrode 175a and not covered by the data line 171 and the first drain electrode 175a. Although the width of the linear semiconductor 151 is smaller than the width of the data line 171, as described above, the width of the linear semiconductor 151 is increased so that the width of the linear semiconductor 151 becomes greater than the width of the data line 171. This prevents disconnection.

On the data line 171, the first and second drain electrodes 175a and 175b, the power supply line 172, and the exposed portions of the semiconductors 151 and 154b, an organic material or a plasma chemical vapor phase having excellent planarization characteristics and photosensitivity. A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by deposition (PECVD) is formed.

In the case where the passivation layer 180 is formed of an organic material, silicon nitride (SiNx) or silicon oxide ( An inorganic insulating film made of SiO 2 ) may be further formed.

The passivation layer 180 has a plurality of contacts exposing the first drain electrode 175a, the second gate electrode 124b, the second drain electrode 175b, and the extension 125 of the gate line and the extension 179 of the data line, respectively. The spheres 185, 183, 181. 182, 189 are formed.

The contact holes 182 and 189 exposing the data lines 171 and the extension portions 125 and 179 of the gate line 121 formed in the passivation layer 180 may have an external driving circuit output terminal and data line 171. And extension portions 125 and 179 of the gate line 121. At this time, an anisotropic conductive film is disposed between the driving circuit output terminal, the gate line 121, and the extension portions 125 and 179 of the data line 171 to achieve physical adhesion and electrical connection. However, when the driving circuit is directly formed on the substrate 110, the contact line is unnecessary because the gate line 121 and the data line 171 are formed to be connected to the output terminal of the driving circuit. In some cases, the gate driving circuit may be directly formed on the substrate 110 and the data driving circuit may be mounted in a separate chip form. In this case, the contact hole exposing the extension 179 of the data line 171 may be provided. 189) only.

The contact holes 185, 183, 181, 182, and 189 may include the first and second drain electrodes 175a and 175b, the second gate electrode 124b, and the extension part 125 of the gate line and the extension part 179 of the data line. In the contact holes 185, 183, 181. 182, and 189, the contact holes 185, 183, 181, 182, and 189 are preferably formed of a three-layer laminated structure composed of the above-described molybdenum alloy and aluminum metal in order to secure contact characteristics with the metal layer formed later.

A plurality of pixel electrodes 901, a plurality of connection members 902, and a plurality of contact assistants 906 and 908 are formed on the passivation layer 180.

The pixel electrode 901 is physically and electrically connected to the second drain electrode 175b through the contact hole 185, respectively, and the connection member 902 is connected to the first drain electrode through the contact holes 181 and 183. 175a and the second gate electrode 124b are connected to each other. The contact auxiliary members 906 and 908 are connected to the extension 125 of the gate line and the extension 179 of the data line through the contact holes 182 and 189, respectively.

The pixel electrode 901, the connection member 902, and the contact assistant members 906 and 908 are made of ITO or IZO.

An upper portion of the passivation layer 180 is formed of an organic insulating material or an inorganic insulating material, and a partition 803 is formed to separate the organic light emitting cells. The partition 803 surrounds the edge of the pixel electrode 901 to define a region in which the organic light emitting layer 70 is to be filled.

An organic light emitting layer 70 is formed in an area on the pixel electrode 901 surrounded by the partition 803. The organic light emitting layer 70 is formed of an organic material emitting one of red (R), green (G), and blue (B), and the organic light emitting layers 70 of red, green, and blue are repeatedly arranged in sequence. It is.

On the partition wall 803, an auxiliary electrode 272 made of a conductive material having the same shape as that of the partition wall 803 and having a low specific resistance is formed. The auxiliary electrode 272 is in contact with the common electrode 270 formed later to reduce the resistance of the common electrode 270.

The common electrode 270 is formed on the partition wall 803, the organic light emitting layer 70, and the auxiliary electrode 272. The common electrode 270 is made of a metal having low resistance such as aluminum. Although the bottom emission type organic light emitting display device is illustrated here, in the case of the top emission type organic light emitting display device or the double sided emission type organic light emitting display device, the common electrode 270 is formed of a transparent conductive material such as ITO or IZO.

A method of manufacturing the TFT panel for the OLED display illustrated in FIGS. 17 to 21 will be described in detail with reference to FIGS. 22 to 33B and 17 to 21.

22, 24, 26, 28, 30, and 32 are layout views showing intermediate steps in the method of manufacturing the thin film transistor array panel of FIGS. 17 to 21, and FIGS. 23A, 23B, and 23C are FIGS. Are cross-sectional views taken along lines XXIIIa-XXIIIa ', XXIIIb-XXIIIb', and XXIIIc-XXIIIc ', and FIGS. 25A, 25B, and 25C are lines XXVa-XXVa', XXVb-XXVb ', and Sectional drawing cut along the XXVc-XXVc 'line, and FIGS. 27A, 27B, 27C, and 27D are XXVIIa-XXVIIa' line, XXVIIb-XXVIIb 'line, XXVIIc-XXVIIc' line, and XXVIId-XXVIId 'in FIG. 29A, 29B, 29C, and 29D are cut along the lines, and cut along the lines XXIXa-XXIXa ', XXIXb-XXIXb', XXIXc-XXIXc ', and XXIXd-XXIXd' in FIG. 31A, 31B, 31C, and 31D are cross-sectional views taken along lines XXXIa-XXXIa ', XXXIb-XXXIb', XXXIc-XXXIc ', and XXXId-XXXId' in FIG. 30. 33A and 33B are FIGS. 32 is a cross-sectional view taken along the lines XXXIIIa-XXXIIIa 'and XXXIIIb-XXXIIIb'.

First, as shown in FIGS. 22 to 23C, a gate metal layer is stacked on an insulating substrate 110 made of transparent glass or the like. The metal layer is formed by co-sputtering. In this embodiment, aluminum (Al) or niobium (Nb), niobium (Nb), vanadium (V) or aluminum (Al) or neodymium (Nd) is added as a target of the co-sputtering. Molybdenum alloys (MoNb, MoV, MoTi) added with titanium (Ti) are used.

Co-sputtering is performed as follows.

Initially, no power is applied to the molybdenum alloy target and only the aluminum or aluminum alloy target is applied to form first metal layers 124a 'and 124b' made of aluminum on the substrate. Then, after the power applied to the aluminum target is turned off, the power applied to the molybdenum alloy is applied to form the second metal layers 124a "and 124b". In this case, the aluminum alloy preferably uses an Al-Nd sputtering target containing about 2 at% of neodymium (Nd), and preferably has a thickness of about 2,500 kPa. In addition, the molybdenum alloy is added in a content of 0.1 at% to 10 at% niobium (Nb), vanadium (V) or titanium (Ti), preferably from 5 at% to 8 at%.

Thereafter, the first metal layers 124a 'and 124b' and the second metal layers 124a "and 124b" are etched at once to form a gate line 121 and a second gate electrode 124b including a plurality of gate electrodes 124a. And the sustain electrode 133. At this time, an etchant containing phosphoric acid, nitric acid, acetic acid, and demineralized water in an appropriate ratio is suitable. Specifically, 63-70% phosphoric acid, 4-8% nitric acid, 8-11% acetic acid, and residual demineralized water are used. An integrated etchant including or an etchant containing an acetic acid content of about 4-8% increased than the etchant may be used. The gate line 121 including the plurality of first gate electrodes 124a, the second gate electrode 124b, and the storage electrode 133 are formed by patterning by a photolithography process using a photoresist pattern.

Next, as shown in FIGS. 25 to 26C, three layers of the gate insulating layer 140, the intrinsic amorphous silicon layer, and the impurity amorphous silicon layer are successively stacked, and the impurity amorphous silicon layer and the intrinsic amorphous silicon layer are photo-etched to form a plurality of layers. The linear semiconductor 151 and the island-like semiconductor 154b each including the linear impurity semiconductor 164 and the plurality of protrusions 154a are formed. As the material of the gate insulating layer 140, silicon nitride (SiNx) is preferable, and the stacking temperature is preferably about 250 to 500 ° C., and about 2,000 to 5,000 kPa.

Next, as shown in FIGS. 26 to 27D, metal layers 171b ', 173b', and 175b 'made of aluminum or an aluminum alloy, and niobium (Nb) and vanadium (V) formed on the lower and upper portions of the metal layer, or A metal layer (171a ', 173a', 175a ', 171c', 173c ', and 175c') containing a molybdenum alloy film containing a predetermined amount of titanium (Ti) is laminated, and a photoresist film is formed thereon, and the conductive film is patterned using an etching mask. The power line 172 includes a plurality of data lines 171 having a plurality of first source electrodes 173a, a plurality of first and second drain electrodes 175a and 175b, and a plurality of second source electrodes 173b. ).

Subsequently, a portion of the exposed impurity semiconductor 164 is removed by removing or leaving the photoresist film on the data line 171, the power supply line 172, and the first and second drain electrodes 175a and 175b. While completing the plurality of linear ohmic contacts 161 and the plurality of islands of ohmic contact 165a, 165b, and 163b each including protrusions 163a, the linear intrinsic semiconductor 151 and the island intrinsic semiconductor (below) are completed. 154b) expose a portion.

Subsequently, oxygen (O 2 ) plasma is preferably followed to stabilize the exposed surfaces of the intrinsic semiconductors 151 and 154b.

Next, as shown in FIGS. 28 to 29D, an organic insulating material or an inorganic insulating material is coated to form the passivation layer 180, and dry etching is performed by a photo process to produce a plurality of contact holes 189, 185, 183, 181, and the like. 182 is formed. The contact holes 181, 182, 185, 183, and 189 may include first and second drain electrodes 175a and 175b, a part of the second gate electrode 124b, an extension part 125 of the gate line, and an extension part of the data line ( 179).

Next, as shown in FIGS. 31 to 32D, the pixel electrode 901, the connection member 902, and the contact auxiliary members 906 and 908 are formed of ITO or IZO.                     

32 to 36, the barrier rib 803 and the auxiliary electrode 272 are formed by a photolithography process using one mask, and the organic emission layer 70 and the organic light emitting layer 70 as shown in FIGS. 22 to 24. The common electrode 270 is formed.

In this embodiment, although only the case where both the gate line 121 and the data line 171 are formed by the multiple layer which consists of a layer containing aluminum and a layer containing molybdenum was shown, the gate line 121 and the data line are shown. It is also possible to form a plurality of layers only for any one of the layers 171.

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

A wiring of a liquid crystal display device or a thin film transistor array panel for an organic light emitting display device, comprising a molybdenum alloy in which a predetermined amount of niobium (Nb), vanadium (V), or titanium (Ti) is added to molybdenum (Mo) and an aluminum or aluminum alloy layer By forming the stacked structure, the difference in the relative etching rate between the molybdenum alloy layer and the aluminum layer is reduced compared to the case of using pure molybdenum (Mo), so that undercut, overhang, and mouse bite are not formed during etching, and the semiconductor layer or the pixel electrode Since the contact characteristics of are also improved, it is possible to form an excellent wiring having both low resistance and chemical resistance.

Claims (27)

  1. Insulating substrate;
    A gate line formed on the insulating substrate and including a gate electrode including a first metal layer including aluminum (Al) and a second metal layer including molybdenum alloy to which niobium (Nb) is added to molybdenum (Mo);
    A gate insulating film formed on the gate line;
    A semiconductor layer formed on the gate insulating film;
    A data line formed on the gate insulating layer and the semiconductor layer and including a source electrode;
    A drain electrode facing the source electrode separately;
    A passivation layer formed on the data line and the drain electrode and having a contact hole; And
    A pixel electrode on the passivation layer and connected to the drain electrode through the contact hole;
    The data line and the drain electrode include a third metal layer including molybdenum, a fourth metal layer including aluminum, and a fifth metal layer including molybdenum, and the third and fifth metal layers include niobium (Nb) added to molybdenum. A thin film transistor array panel made of a molybdenum alloy.
  2. The thin film transistor array panel of claim 1, wherein the first metal layer comprises an aluminum alloy in which neodymium (Nd) is added to aluminum.
  3. delete
  4. delete
  5. Insulating substrate;
    A gate line formed on the insulating substrate and including a gate electrode;
    A gate insulating film formed on the gate line;
    A semiconductor layer formed on the gate insulating film;
    The first insulating layer is formed on the gate insulating layer and the semiconductor layer, and includes a first metal layer including molybdenum, a second metal layer including aluminum, and a third metal layer including molybdenum, and the first and third metal layers are formed of niobium (B) in molybdenum. A data line including a source electrode made of molybdenum alloy to which Nb) is added;
    A drain electrode facing the source electrode separately;
    A passivation layer formed on the data line and having a contact hole; And
    And a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole.
  6. The thin film transistor array panel of claim 5, wherein the gate line is formed of a metal layer including aluminum.
  7. The thin film transistor array panel of claim 6, wherein the gate line is formed of an aluminum alloy in which neodymium (Nd) is added to aluminum.
  8. The thin film transistor array panel of claim 1, wherein the molybdenum alloy contains 0.1 at% to 20 at% of niobium (Nb).
  9. The thin film transistor array panel of claim 8, wherein the molybdenum alloy contains 3 at% to 8 at% of niobium (Nb).
  10. The thin film transistor array panel of claim 1, wherein the pixel electrode is made of ITO or IZO.
  11. The thin film transistor array panel of claim 1, further comprising a color filter formed on the insulating substrate and positioned below the pixel electrode.
  12. Forming and patterning a gate line on the insulating substrate, the gate line including a gate electrode including a first metal layer including aluminum and a second metal layer including a molybdenum alloy mixed with niobium (Nb) in molybdenum (Mo);
    Sequentially depositing a gate insulating film, a semiconductor layer, and an ohmic contact layer on the gate line;
    Etching and patterning the semiconductor layer and the ohmic contact layer;
    Forming and patterning a metal layer on the insulating layer and the ohmic contact layer to form a data line including a source electrode and a drain electrode separately facing the source electrode;
    Forming a passivation layer including a contact hole exposing the drain electrode on the data line; And
    Forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer,
    The metal layer sequentially forms a third metal layer including molybdenum, a fourth metal layer including aluminum, and a fifth metal layer including molybdenum, and the third and fifth metal layers include niobium (Nb) added to molybdenum. A method of manufacturing a thin film transistor array panel made of molybdenum alloy.
  13. Forming and patterning a gate line including a gate electrode on the insulating substrate;
    Sequentially depositing a gate insulating film, a semiconductor layer, and an ohmic contact layer on the gate line;
    Etching and patterning the semiconductor layer and the ohmic contact layer;
    A first metal layer including molybdenum, a second metal layer including aluminum, and a third metal layer including molybdenum are sequentially formed on the gate insulating layer and the ohmic contact layer, and the first and third metal layers are formed of niobium (Nb) in molybdenum. Forming and patterning a data line and a drain electrode including a source electrode made of molybdenum alloy to which y) is added;
    Forming a passivation layer including a contact hole exposing the drain electrode on the data line; And
    And forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer.
  14. The method of claim 12, wherein the gate line or the data line is patterned by using an etchant including phosphoric acid, nitric acid, and acetic acid.
  15. The data line and the semiconductor layer of claim 12 or 13, wherein the data line and the semiconductor layer have a first portion, a second portion thicker than the first portion, and a third portion thinner than the thickness of the first portion. A method of manufacturing a thin film transistor array panel patterned using a photosensitive film pattern.
  16. The method of claim 15, wherein the first portion is formed between the source electrode and the drain electrode, and the second portion is formed above the data line.
  17. The method of claim 12, further comprising forming a color filter before forming the passivation layer.
  18. A gate line formed on the insulating substrate and including a gate electrode, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, a first insulating film formed on the gate insulating film and the semiconductor layer and including molybdenum A data line comprising a metal layer, a second metal layer including aluminum, and a third metal layer including molybdenum, wherein the first and third metal layers include a source electrode made of molybdenum alloy in which niobium (Nb) is added to molybdenum, A thin film transistor array panel including a drain electrode facing the source electrode separately from the source electrode, a passivation layer formed on the data line and having a contact hole, and a pixel electrode connected to the drain electrode through the contact hole on the passivation layer;
    A color filter substrate facing the thin film transistor array panel and including a common electrode formed on a second insulating substrate; And
    And a liquid crystal layer injected between the thin film transistor array panel and the color filter substrate.
  19. The liquid crystal display of claim 18, wherein the gate line is formed of a metal layer including aluminum.
  20. The liquid crystal display of claim 18, wherein the molybdenum alloy contains 0.1 at% to 20 at% of niobium (Nb).
  21. The liquid crystal display of claim 21, wherein the molybdenum alloy contains 3 at% to 8 at% of niobium (Nb).
  22. The liquid crystal display of claim 21, wherein the molybdenum alloy contains 3 at% to 8 at% of niobium (Nb).
  23. First and second semiconductors each having first and second channel portions formed of polycrystalline silicon or amorphous silicon on an insulating substrate;
    A gate line having a first gate electrode overlapping the first channel portion;
    A second gate electrode overlapping the second channel portion;
    A gate insulating film formed between the first and second semiconductors and the first and second gate electrodes;
    A data line having a first source electrode in contact with the first semiconductor;
    A first drain electrode facing the first source electrode around the first channel part and in contact with the first channel part and connected to the second gate electrode;
    A power supply voltage electrode having a second source electrode in contact with the second channel portion;
    A second drain electrode facing the second source electrode with respect to the second channel portion;
    A pixel electrode connected to the second drain electrode and disposed in the pixel area surrounded by the gate line and the data line;
    A partition having an opening exposing the pixel electrode in the pixel area;
    An auxiliary electrode formed on the barrier rib, the auxiliary electrode having the same shape as the barrier rib;
    An organic emission layer formed in the opening above the pixel electrode;
    A common electrode covering the auxiliary electrode and the organic light emitting layer; And
    A contact auxiliary member connected to an extension of the gate line and an extension of the data line;
    The electrode for the data line and the power supply voltage includes a first metal layer including molybdenum, a second metal layer including aluminum, and a third metal layer including molybdenum, and the first and third metal layers are formed of niobium (Nb) in molybdenum. The organic light emitting display element which consists of this added molybdenum alloy.
  24. The organic light emitting diode display of claim 23, wherein the gate line is formed of a metal layer including aluminum.
  25. The organic light emitting diode display of claim 24, wherein the gate line is formed of an aluminum alloy in which neodymium (Nd) is added to aluminum.
  26. The organic light emitting diode display of claim 23, wherein the molybdenum alloy contains 0.1 at% to 20 at% of niobium (Nb).
  27. 27. The organic light emitting diode display as claimed in claim 26, wherein the molybdenum alloy contains 3 at% to 8 at% of niobium (Nb).
KR20040071612A 2004-09-08 2004-09-08 Thin film transistor array panel and manufacturing method thereof KR101061850B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR20040071612A KR101061850B1 (en) 2004-09-08 2004-09-08 Thin film transistor array panel and manufacturing method thereof

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
KR20040071612A KR101061850B1 (en) 2004-09-08 2004-09-08 Thin film transistor array panel and manufacturing method thereof
US11/180,989 US7301170B2 (en) 2004-09-08 2005-07-12 Thin film transistor array panel and method for manufacturing the same
TW94123767A TWI404212B (en) 2004-09-08 2005-07-13 Thin film transistor array panel and method for manufacturing the same
JP2005233289A JP5240964B2 (en) 2004-09-08 2005-08-11 Thin film transistor array panel and manufacturing method thereof
CN 200910137759 CN101552242B (en) 2004-09-08 2005-09-08 The thin film transistor array panel and a manufacturing method
CN 200510098150 CN1761049B (en) 2004-09-08 2005-09-08 Thin film transistor array panel and method for manufacturing the same
US11/944,130 US7550768B2 (en) 2004-09-08 2007-11-21 Thin film transistor array panel and method for manufacturing the same
US11/944,083 US7662715B2 (en) 2004-09-08 2007-11-21 Thin film transistor array panel and method for manufacturing the same

Publications (2)

Publication Number Publication Date
KR20060022839A KR20060022839A (en) 2006-03-13
KR101061850B1 true KR101061850B1 (en) 2011-09-02

Family

ID=36159673

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20040071612A KR101061850B1 (en) 2004-09-08 2004-09-08 Thin film transistor array panel and manufacturing method thereof

Country Status (5)

Country Link
US (3) US7301170B2 (en)
JP (1) JP5240964B2 (en)
KR (1) KR101061850B1 (en)
CN (2) CN1761049B (en)
TW (1) TWI404212B (en)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100935670B1 (en) * 2003-04-04 2010-01-07 삼성전자주식회사 Liquid crystal display, thin film transistor array panel and method for manufacturing the same
KR20060042425A (en) * 2004-11-09 2006-05-15 삼성전자주식회사 Thin film transistor array panel and method for manufacturing the same
TWI326379B (en) * 2005-09-20 2010-06-21 Au Optronics Corp A double-sided liquid crystal display
US7837929B2 (en) * 2005-10-20 2010-11-23 H.C. Starck Inc. Methods of making molybdenum titanium sputtering plates and targets
KR20070075808A (en) * 2006-01-16 2007-07-24 삼성전자주식회사 Method for manufacturing display substrate and display substrate manufactured by the same
TWI282467B (en) * 2006-04-07 2007-06-11 Innolux Display Corp Liquid crystal panel
KR101240652B1 (en) * 2006-04-24 2013-03-08 삼성디스플레이 주식회사 Thin film transistor array panel for display and manufacturing method of the same
EP2037434B1 (en) * 2006-06-30 2015-05-06 Sharp Kabushiki Kaisha Tft substrate, display panel and display device provided with such tft substrate, and tft substrate manufacturing method
CN100501950C (en) 2006-07-10 2009-06-17 友达光电股份有限公司 Thin film transistor and method for manufacturing the same
US20080032431A1 (en) * 2006-08-03 2008-02-07 Tpo Displays Corp. Method for fabricating a system for displaying images
JP2008098611A (en) * 2006-09-15 2008-04-24 Kobe Steel Ltd Display device
TWI319610B (en) * 2006-12-29 2010-01-11 Winbond Electronics Corp Method of manufacturing openings and via openings
KR101373735B1 (en) 2007-02-22 2014-03-14 삼성디스플레이 주식회사 Method for manufacturing a aisnal line, thin film transistor array panel and method for manufacturing the same
KR101319334B1 (en) * 2007-03-20 2013-10-16 엘지디스플레이 주식회사 Liquid crystal display panel and method for manufacturing the same
JP4506810B2 (en) * 2007-10-19 2010-07-21 ソニー株式会社 display device
KR101490480B1 (en) * 2008-07-07 2015-02-06 삼성디스플레이 주식회사 Thin film transistor array panel and manufacturing the same
KR101570347B1 (en) * 2008-11-25 2015-11-20 삼성디스플레이 주식회사 film transistor array panel and manufacturing Method thereof
WO2011027676A1 (en) * 2009-09-04 2011-03-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2011027701A1 (en) * 2009-09-04 2011-03-10 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and method for manufacturing the same
KR101623956B1 (en) * 2010-01-15 2016-05-24 삼성전자주식회사 Transistor, method of manufacturing the same and electronic device comprising transistor
KR101702106B1 (en) * 2010-03-17 2017-02-03 삼성디스플레이 주식회사 Electrowetting display device
JP5839819B2 (en) * 2010-04-16 2016-01-06 株式会社半導体エネルギー研究所 Light emitting device, display module and electronic device
US8449817B2 (en) 2010-06-30 2013-05-28 H.C. Stark, Inc. Molybdenum-containing targets comprising three metal elements
US8449818B2 (en) 2010-06-30 2013-05-28 H. C. Starck, Inc. Molybdenum containing targets
KR101764902B1 (en) * 2010-12-06 2017-08-14 엘지디스플레이 주식회사 Thin film Transistor substrate and method for manufacturing the same
US9334562B2 (en) 2011-05-10 2016-05-10 H.C. Starck Inc. Multi-block sputtering target and associated methods and articles
JP6033071B2 (en) * 2011-12-23 2016-11-30 株式会社半導体エネルギー研究所 Semiconductor device
CN102636927B (en) * 2011-12-23 2015-07-29 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof
US20130240995A1 (en) * 2012-03-19 2013-09-19 Shenzhen China Star Optoelectronics Technology Co., Ltd Thin-film transistor array substrate and manufacturing method thereof
US9334565B2 (en) 2012-05-09 2016-05-10 H.C. Starck Inc. Multi-block sputtering target with interface portions and associated methods and articles
KR101444777B1 (en) * 2012-08-10 2014-09-26 엘지디스플레이 주식회사 Organic light emitting diode display device and method of fabricating the same
US20150221773A1 (en) * 2012-09-05 2015-08-06 Sharp Kabushiki Kaisha Semiconductor device and method for producing same
CN103745980B (en) * 2014-01-28 2017-02-15 昆山龙腾光电有限公司 The thin film transistor array substrate and a manufacturing method and a liquid crystal display device
WO2016017516A1 (en) * 2014-07-30 2016-02-04 シャープ株式会社 Display device and method for producing same
KR20160017795A (en) 2014-08-05 2016-02-17 삼성디스플레이 주식회사 Thin film transistor substrate, manufacturing method of the same, and display device having the thin film transistor
KR20160056964A (en) 2014-11-12 2016-05-23 엘지디스플레이 주식회사 Organic Light Emitting Diode Display Having High Aperture Ratio And Method For Manufacturing The Same
KR20160091525A (en) * 2015-01-23 2016-08-03 삼성디스플레이 주식회사 Organic light emitting diode display and manufacturing method thereof
CN105655391B (en) * 2016-01-28 2018-10-26 武汉华星光电技术有限公司 Tft array substrate and preparation method thereof
TWI662327B (en) * 2018-02-09 2019-06-11 友達光電股份有限公司 Display panel

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1327358C (en) 1987-11-17 1994-03-01 Morio Fujiu Fluoro cytidine derivatives
JP2673460B2 (en) * 1990-02-26 1997-11-05 キヤノン株式会社 The liquid crystal display element
SK279958B6 (en) 1992-04-02 1999-06-11 Smithkline Beecham Corporation Compounds exhibiting anti-allergic and anti-inflammatory properties, pharmaceutical composition them containing and their use
US5831694A (en) * 1995-06-14 1998-11-03 Hitachi, Ltd. TFT panel for high resolution- and large size- liquid crystal display
JPH0926598A (en) 1995-07-10 1997-01-28 Hitachi Ltd Active matrix type liquid crystal display device
EP1338914A3 (en) * 1995-11-21 2003-11-19 Samsung Electronics Co., Ltd. Method for manufacturing liquid crystal display
TW409194B (en) * 1995-11-28 2000-10-21 Sharp Kk Active matrix substrate and liquid crystal display apparatus and method for producing the same
KR100248123B1 (en) * 1997-03-04 2000-03-15 구본준 Thin-film transistor and method for manufacturing thereof
US6333518B1 (en) * 1997-08-26 2001-12-25 Lg Electronics Inc. Thin-film transistor and method of making same
AT254778T (en) * 1997-09-05 2003-12-15 Sun Microsystems Inc Lookup table and method for data storage in
JP4493741B2 (en) * 1998-09-04 2010-06-30 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6287899B1 (en) * 1998-12-31 2001-09-11 Samsung Electronics Co., Ltd. Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
JP2000284326A (en) 1999-03-30 2000-10-13 Hitachi Ltd Liquid crystal display device and its production
JP2000314897A (en) 1999-05-06 2000-11-14 Hitachi Ltd Liquid crystal display device
US6380559B1 (en) * 1999-06-03 2002-04-30 Samsung Electronics Co., Ltd. Thin film transistor array substrate for a liquid crystal display
KR100733876B1 (en) 2000-01-04 2007-07-02 엘지.필립스 엘시디 주식회사 Liquid Crystal Display Device and Fabricating Method Thereof
JP3785900B2 (en) * 2000-04-28 2006-06-14 株式会社日立製作所 The liquid crystal display device and a method of manufacturing the same
KR20020039736A (en) 2000-11-22 2002-05-30 박종섭 Liquid crystal display device and method of manufacturing the same
JP3859119B2 (en) 2000-12-22 2006-12-20 日立金属株式会社 For electronic components thin film wiring
JP2002324808A (en) * 2001-01-19 2002-11-08 Semiconductor Energy Lab Co Ltd Semiconductor device and method for manufacturing the same
JP2002322528A (en) * 2001-04-24 2002-11-08 Mitsubishi Chemicals Corp Electrode wiring material and production method therefor
JP4920140B2 (en) * 2001-05-18 2012-04-18 ゲットナー・ファンデーション・エルエルシー Liquid crystal display device and manufacturing method thereof
JP2003172946A (en) * 2001-09-28 2003-06-20 Fujitsu Display Technologies Corp Substrate for liquid crystal display device and liquid crystal display device using the substrate
US7102168B2 (en) 2001-12-24 2006-09-05 Samsung Electronics Co., Ltd. Thin film transistor array panel for display and manufacturing method thereof
JP3675420B2 (en) * 2002-03-26 2005-07-27 セイコーエプソン株式会社 Liquid crystal display device and an electronic apparatus
US20030203627A1 (en) * 2002-04-30 2003-10-30 Jia-Pang Pang Method for fabricating thin film transistor
TWI273637B (en) * 2002-05-17 2007-02-11 Semiconductor Energy Lab Manufacturing method of semiconductor device
KR20040001689A (en) 2002-06-28 2004-01-07 삼성전자주식회사 A wiring, a thin film transistor array panel including the wiring and a method for manufacturing the panel
JP2004035647A (en) * 2002-07-01 2004-02-05 Sumitomo Rubber Ind Ltd Thread rubber composition, thread rubber, and thread wound golf ball
JP2004054069A (en) * 2002-07-23 2004-02-19 Advanced Display Inc Display device and method for repairing disconnection of display device
JP4496518B2 (en) 2002-08-19 2010-07-07 日立金属株式会社 Thin film wiring
KR100883769B1 (en) 2002-11-08 2009-02-18 엘지디스플레이 주식회사 Method for fabricating of an array substrate for LCD
KR100895313B1 (en) 2002-12-11 2009-05-07 삼성전자주식회사 Organic electro-luminescence display panel
KR100511353B1 (en) 2002-12-27 2005-08-31 엘지.필립스 엘시디 주식회사 Fabrication method of liquid crystal display device and liquid crystal display device fabticated by the same
US7105896B2 (en) * 2003-07-22 2006-09-12 Nec Lcd Technologies, Ltd. Thin film transistor circuit device, production method thereof and liquid crystal display using the think film transistor circuit device
JP2005163901A (en) 2003-12-02 2005-06-23 Taisei Corp Water bed pipe laying method

Also Published As

Publication number Publication date
US20080166827A1 (en) 2008-07-10
JP2006080505A (en) 2006-03-23
CN1761049A (en) 2006-04-19
JP5240964B2 (en) 2013-07-17
CN101552242B (en) 2012-02-01
US20060050192A1 (en) 2006-03-09
US7550768B2 (en) 2009-06-23
US20080073674A1 (en) 2008-03-27
TW200614514A (en) 2006-05-01
TWI404212B (en) 2013-08-01
US7662715B2 (en) 2010-02-16
KR20060022839A (en) 2006-03-13
US7301170B2 (en) 2007-11-27
CN101552242A (en) 2009-10-07
CN1761049B (en) 2010-09-01

Similar Documents

Publication Publication Date Title
CN100371810C (en) A wire structure, a thin film transistor substrate of using the wire structure and a method of manufacturing the same
KR100796795B1 (en) Contact portion of semiconductor device and method for manufacturing the same, and thin film transistor array panel for display device including the contact portion and method for manufacturing the same
US6207480B1 (en) Method of manufacturing a thin film transistor array panel for a liquid crystal display
DE10355666B4 (en) Thin film transistor matrix substrate and method for its production
US6642580B1 (en) Thin film transistor array substrate and manufacturing method thereof
US7615784B2 (en) Thin film transistor array panel and manufacturing method thereof
JP4413337B2 (en) Thin film transistor substrate for liquid crystal display device and manufacturing method thereof
US8563980B2 (en) Array substrate and manufacturing method
US6114184A (en) Method for manufacturing LCD device capable of avoiding short circuit between signal line and pixel electrode
JP4658514B2 (en) Thin film transistor array substrate and manufacturing method thereof
KR101415561B1 (en) Thin film transistor array panel and manufacturing method thereof
US7659130B2 (en) Thin film transistor array panel for display and manufacturing method thereof
JP5466665B2 (en) Thin film transistor substrate for liquid crystal display device and manufacturing method thereof
CN1139837C (en) Film transistor array substrate for liquid crystal and manufacture thereof
US9431426B2 (en) Thin film transistor array panel including layered line structure and method for manufacturing the same
KR101213708B1 (en) Array substrate and method of fabricating the same
KR100752600B1 (en) Polycrystalline thin film transistor for liquid crystal device LCD and Method of manufacturing the same
JP5302275B2 (en) Contact portion of semiconductor element and manufacturing method thereof, thin film transistor array panel for display device, and manufacturing method thereof
US5990555A (en) Electronic circuit device with multi-layer wiring
US8053802B2 (en) Liquid crystal display device and method of fabricating the same
JP4544860B2 (en) Method of manufacturing contact portion of semiconductor element, and method of manufacturing thin film transistor array substrate for liquid crystal display device including the same
US7129105B2 (en) Method for manufacturing thin film transistor array panel for display device
US7538850B2 (en) Panel for display device, manufacturing method thereof and liquid crystal display
US7742118B2 (en) Thin film transistor array panel and manufacturing method thereof
JP4928665B2 (en) Wiring contact structure, method for forming the same, thin film transistor substrate including the same, and method for manufacturing the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
AMND Amendment
J201 Request for trial against refusal decision
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20160801

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20180802

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20190801

Year of fee payment: 9