KR20030086804A - Method of manufacturing an active layer and a method for manufacturing a MOS transistor using the same - Google Patents

Abstract

PURPOSE: A method for fabricating an active layer of a semiconductor device is provided to prevent a problem arising from germanium segregation by forming a high density germanium segregation layer on an interface between silicon germanium and an oxide so that the germanium segregation layer is used as a channel of a metal oxide semiconductor(MOS) transistor after a heat treatment process. CONSTITUTION: A silicon germanium layer(22) and a silicon layer are sequentially formed on a semiconductor substrate(21). The silicon layer is oxidized to form the germanium segregation layer(22a) on the silicon germanium layer. A heat treatment process is performed to uniformly distribute germanium of the germanium segregation layer.

Description

Method of manufacturing an active layer of a semiconductor device and a method of manufacturing a MOS transistor using the same {Method of manufacturing an active layer and a method for manufacturing a MOS transistor using the same}

The present invention relates to a method of manufacturing an active layer of a semiconductor device and a method of manufacturing a MOS transistor using the same, and more particularly, silicon germanium having improved mobility of a carrier using a high concentration of germanium (Ge) segregation layer as a channel ( An active layer of a semiconductor device using a SiGe) compound and a method for producing a MOS transistor having a heterostructure using the same.

As the integration density and operation speed of semiconductor devices increase, current MOSFETs using silicon (Si) as a channel have limitations in operation. Therefore, studies on the fabrication of hetero-structure transistors using silicon germanium (SiGe) as a channel have been actively conducted.

Electrons and holes serving as carriers in MOS transistors have been known to have higher mobility in silicon germanium (SiGe) than silicon (Si). In addition, the heterogeneous structure of silicon germanium (SiGe) has been reported to improve the mobility of the carrier and to solve all problems caused by the short channel.

In the heterogeneous structure composed of silicon (Si) and silicon germanium (SiGe), deformation of the energy band gap causes electrical conduction while the carrier is trapped in the quantum well, thus reducing scattering and increasing the mobility of the carrier ( IEEE Trans.on Electron Devices, 43 (8), pp 1224 ).

PMOS transistors typically have a Si / SiGe / Si structure, and a strained silicon germanium (SiGe) layer is used as a channel in which holes are confined. In this case, a quantum well is generated in a channel of a balance band ( IEEE Trans.on Electron Devices, 41 (5), pp 857 ).

Meanwhile, the NMOS transistor has a SiGe / Si / SiGe or Si / SiGe structure, and a strained silicon (Si) layer is used as a channel. Such a channel has been reported to improve in trans-conductance (gm), especially when located closer to the surface layer ( IEEE Electron Device Letters, 15 (3), pp 100 ).

Although much research has been conducted to develop a CMOS device having a heterogeneous structure of silicon germanium (SiGe), only a structure capable of simultaneously implementing an NMOS and a PMOS transistor is proposed. As an example, a technology using a silicon (Si) layer in an NMOS device and a high concentration of a silicon germanium (SiGe) layer in a PMOS device has been reported based on a silicon germanium (SiGe) layer having a low concentration of germanium (Ge). ( IEEE Trans.on Electron Devices, 43 (8), pp 1224 ). In addition, the structure of the device associated with it has also recently been registered as a patent ( Fischer et al., US patent US 006111267A ).

As such, research for realizing a MOS transistor having a heterogeneous structure of silicon germanium (SiGe) has been accelerated, but on the other hand, a problem caused by germanium (Ge) segregation is emerging as a large barrier. Germanium (Ge) segregation is a phenomenon in which germanium (Ge) has a certain amount of solubility in silicon germanium (SiGe) compounds due to the difference in enthalpy between silicon (Si) and germanium (Ge), and the rest accumulates on the surface as the thin film grows. When the energy barrier is not high and becomes above a predetermined temperature, it occurs suddenly ( Applied Physics Letter, 59 (17), pp 2103 ). For example, segregation occurs due to the movement of germanium (Ge) at a temperature of 400 ° C. or higher, or when the silicon germanium (SiGe) layer is oxidized, oxides (SiO ₂ ) are generated, and germanium (Ge) is pushed out to form oxides and silicon germanium. Accumulate at the interface of (SiGe).

As such, the high concentration of germanium (Ge) segregation on the surface adversely affects the properties of the device. That is, since germanium (Ge) accumulated at the interface between the semiconductor and the oxide plays a role of interfacial charge, it acts as a trap for the carrier and deteriorates the characteristics of the device. This problem occurs because germanium (Ge) segregation is unevenly distributed at the interface, and the center of the concentration distribution is at the interface.

When the gate oxide film is grown, silicon (Si) is preferentially oxidized in the silicon germanium (SiGe) layer. When germanium (Ge) is accumulated at a predetermined thickness or more at the interface, germanium (Ge) begins to be oxidized ( Journal of Applied Physics, 74 (7), pp 4750 ). In the case of the gate oxide film, since it is very thin, it remains in the stage before germanium (Ge) is oxidized, that is, the germanium (Ge) piles up at an interface.

The accumulation of germanium segregation depends on oxidation temperature, composition of germanium (Ge), oxidation method (dry or wet), etc. ( Journal of Applied Physics, 81 (12), pp 8024 ). Due to the segregation of germanium (Ge) during the growth of the thin film and germanium (Ge) pushed out during oxidation, germanium (Ge) having a much higher concentration than the channel layer is present at the interface. This concentration distribution of germanium (Ge) has recently been reported that the center of the distribution moves from the interface toward the channel as the maximum value of the concentration is reduced by subsequent heat treatment ( Applied Physics Letter, 79 (22), pp 3607 ). This draws attention because it suggests that germanium (Ge) segregation may contribute to the channel.

The role of the silicon germanium (SiGe) layer containing a high concentration of germanium (Ge) has been highlighted that a variety of applications. Patents related to the technology for growing a silicon germanium (SiGe) layer to prevent deterioration of the device due to the diffusion of boron (Schmitz et al., US Patent US 006271551B1 ) and metal oxides such as Ta ₂ O ₅ There is a patent (Okuno et al., US Pat . Therefore, unlike germanium (Ge) that accumulates at the interface when using a silicon oxide film as a dielectric film, a positive role of germanium (Ge) is expected in the growth of high-k dielectric films such as metal oxide film.

Germanium (Ge) segregation at the interface between the semiconductor and the oxide film is predominantly reported to reduce the electrical characteristics of the device. At present, it is very difficult to suppress the formation of germanium (Ge) segregation at a certain temperature or more, and such germanium (Ge) segregation is the biggest obstacle to realizing heterogeneous structure of silicon germanium (SiGe).

Therefore, the present invention only solves the problem due to germanium segregation by using high temperature germanium segregation layer at the interface between silicon germanium (SiGe) and oxide through oxidation and heat treatment to use as channel of MOS transistor. Furthermore, it is possible to manufacture MOS transistors having improved characteristics.

According to the present invention, not only the deterioration of the overall characteristics of the device due to germanium (Ge) segregation is prevented, but also a high mobility channel is formed, thereby improving the characteristics of the device. Therefore, it solves the germanium (Ge) segregation problem, which was the main factor of the limitation of the existing silicon germanium (SiGe) device, and configures a high concentration of germanium (Ge) channel layer to achieve two effects at once. This silicon germanium (SiGe) channel layer was applied to both PMOS and NMOS devices. In addition, a silicon cap layer is formed on the silicon germanium (SiGe) layer, and the thickness of the silicon cap layer is controlled so that the concentration of the germanium (Ge) segregation is controlled at the interface, and thus the silicon germanium (SiGe) channel. By adjusting the concentration and thickness of the quantum well to control the size and width. Furthermore, the high concentration of silicon germanium (SiGe) layer prevents the diffusion of boron (B), it is possible to expect the effect of preventing the generation of low dielectric layer of the high-k metal film.

In the method of manufacturing an active layer of a semiconductor device according to the present invention for achieving the above object, the step of sequentially forming a silicon germanium layer and a silicon layer on a semiconductor substrate, the silicon germanium segregation layer is formed on top of the silicon germanium layer Oxidizing the layer, heat treatment to uniformize the germanium distribution of the germanium segregation layer.

In addition, in the method of manufacturing a MOS transistor using an active layer manufactured according to the present invention, the step of sequentially forming a silicon germanium layer and a silicon layer on a semiconductor substrate, a gate oxide film is formed at the same time the germanium segregation layer on top of the silicon germanium layer Oxidizing the silicon layer so as to be formed, heat-treating it to make a germanium distribution of the germanium segregation layer uniform, forming a polysilicon layer on the gate oxide film, and then patterning to form a gate electrode, the gate electrode And forming a source and a drain by implanting impurity ions into the exposed silicon germanium layer after forming spacers on both side walls.

The silicon germanium layer and the silicon layer may be formed in a multi-structure, and oxidize only a partial thickness of the silicon layer during the oxidation process.

In addition, the germanium concentration of the silicon germanium layer is characterized in that 5 to 20at%, the thickness of the germanium segregation layer is characterized by the thickness, oxidation time and temperature of the silicon layer. This is because the silicon layer acts as a barrier to segregation of germanium.

The germanium concentration of the germanium segregation layer is 10 to 100 at%, characterized in that determined by the thickness of the silicon layer.

1 is a cross-sectional view of a device for explaining the concentration distribution of germanium (Ge).

Figure 2a is a graph showing the concentration distribution of germanium (Ge) when the silicon cap layer is not formed.

2B and 2C are graphs showing the concentration distribution of germanium (Ge) when the silicon cap layer is formed.

3 is a graph showing the distribution of germanium (Ge) concentration before and after heat treatment.

4 is a cross-sectional view illustrating a phenomenon in which germanium (Ge) accumulates when a gate oxide film is formed in a hetero structure of silicon germanium (SiGe).

5 is a cross-sectional view of a device for explaining a method of manufacturing a PMOSFET having a high concentration of germanium (Ge) channels according to the present invention.

FIG. 6 is a graph illustrating an energy band of the transistor illustrated in FIG. 5.

7 is a cross-sectional view of a device for explaining a method of manufacturing an NMOSFET having a high concentration of germanium (Ge) channel according to the present invention.

FIG. 8 is a graph showing an energy band of the transistor shown in FIG. 7. FIG.

9 is a graph showing the thickness and concentration change of the segregated silicon germanium (SiGe) layer with the change of heat treatment temperature and time.

<Explanation of symbols for the main parts of the drawings>

1, 11, 21, and 31: silicon substrate

2, 12, 22, and 32: silicon germanium (SiGe) layers

2a, 12a, 22a, and 32a: germanium (Ge) segregation layer

3 and 23: silicon cap layer 3a: oxide film

13, 23a and 33a: gate oxide films 24 and 34: gate electrode

25 and 35: spacers 26 and 36: source / drain

27: hole 33: silicon layer

39: electronic

The present invention implements a channel made of high concentration of silicon germanium (SiGe) using germanium (Ge) segregation. This requires a technique that can control the formation of germanium segregation. Deposition temperature, flow rate and pressure, hydrogen atmosphere and partial pressure during deposition will be factors that can determine the concentration and distribution of germanium segregation. However, there are some difficulties in changing these in an optimized process.

Therefore, in the present invention, the silicon cap layer is grown on the silicon germanium (SiGe) layer, and the concentration of the germanium (Ge) segregation may be adjusted by controlling the thickness of the silicon cap layer.

FIG. 1A is a cross-sectional view of a silicon germanium (SiGe) layer 2 and a silicon cap layer 3 sequentially formed on a silicon (Si) substrate 1 to confirm a concentration distribution of germanium (Ge). The (SiGe) layer 2 is formed at a pressure of 30 torr and a temperature of 600 ° C., and the silicon cap layer 3 is formed by a reduced pressure chemical vapor deposition (RPCVD) method at a pressure of 30 tor and a temperature of 700 ° C., respectively.

FIG. 1B is a cross-sectional view of a state in which an oxide film 3a is formed by oxidizing the silicon cap layer 3, wherein a germanium segregation layer 2a is formed on the silicon germanium (SiGe) layer 2 during the oxidation process. Is generated.

FIG. 2A illustrates the germanium in the silicon germanium (Ge) layer 2 using a surface ion analyzer (SIM) after performing an oxidation process without forming the silicon cap layer 3 in the structure of FIG. 1A. Ge is a graph showing the result of analyzing the concentration distribution. In this case, the composition of germanium (Ge) is relatively low at 20at% (line A), and the germanium (Ge) of 70at% concentration is segregated at the interface (line B). This results in a very sharp peak distribution.

On the other hand, when the phosphorus (Phosphorus) is doped it was observed that the concentration is improved to about 80 to 90 at%, it is determined that phosphorus (P) has an effect on lowering the energy barrier of germanium (Ge) segregation. As a similar example, it has recently been reported that the energy barrier to surface segregation of antimony (Sb) changes depending on the presence or absence of germanium (Ge) ( Journal of Crystal Growth, 201/202, pp 560 ). Since the center of the germanium (Ge) concentration distribution coincides with the center of the semiconductor and the oxide film interface, it can be seen that the germanium (Ge) is bonded to the high energy state of the interface.

FIG. 2B is a graph illustrating the germanium (Ge) concentration distribution in the silicon germanium (Ge) layer 2 using a surface analyzer (SIMS) after forming the silicon cap layer 3 to a thickness of 5 nm and performing an oxidation process in FIG. As a graph showing one result, it can be seen that about 50 at% of germanium (Ge) is segregated at the interface (line C) of the silicon germanium (SiGe) layer 2 and the oxide film 3a. This is a very important result in terms of suggesting the possibility of controlling the amount of segregation of germanium (Ge) at the interface by adjusting the thickness of the silicon cap layer (3). In this case, it can be seen that the maximum value of segregated germanium (Ge) concentration is located at the center of the interface, and shows a very sharp maximum distribution.

FIG. 2C illustrates the distribution of germanium (Ge) concentration in the silicon germanium (Ge) layer 2 using a surface analyzer (SIMS) after forming the silicon cap layer 3 to a thickness of 10 nm and performing an oxidation process in FIG. 1. As a graph showing the results of the analysis, in this case, the amount of germanium (Ge) segregated on the surface (line D) is lower than about 20 at% of the lower silicon germanium (SiGe) layer (2). It also shows a sharp peak distribution, and the center of the distribution is also located at the interface.

As can be seen from the results of FIGS. 2A to 2C, the concentration of germanium segregation was controlled by a silicon cap layer 3 having a relatively thin thickness of about 0 to 10 nm, and boron (B) or phosphorus (P) and It can be seen that the same dopant is significantly affected.

3 is a heat treatment when subsequent heat treatment is performed to shift the maximum center of germanium (Ge) concentration because germanium (Ge) segregation is unevenly distributed at the interface center between the silicon germanium (SiGe) layer 2 and the oxide film 3a. The concentration maximum distribution before and after is shown. This was confirmed by a recent paper ( Applied Physics Letter, 79 (22), pp3607 ), where the center of the maximum concentration distribution of germanium (Ge) before heat treatment (line E) is the same as the channel after heat treatment (line F). Moving toward, the concentration of the maximum is somewhat lowered and the pattern of the maximum is changed to a round shape. Subsequent heat treatment is preferred to be in-situ for accurate control. However, heat treatment may be inevitable in the process of generating silicide or activating the dopant in a subsequent manufacturing process of the MOS device. After heat treatment, the high concentration of germanium (Ge) distribution becomes uniform, and the possibility of application to the high mobility quantum well channel is further increased.

4 shows accumulation of germanium (Ge) 12a generated when the gate oxide layer 13 is formed in a silicon germanium (SiGe) heterostructure in which a silicon germanium (SiGe) layer 12 is stacked on the silicon substrate 11. (Pile up) The phenomenon is shown in cross section. Here, the silicon oxide film (SiO ₂ ) or the metal oxide film is used as the gate oxide film 13.

Like germanium (Ge) that is segregated during the growth of a silicon germanium (SiGe) thin film, when growing a silicon oxide film (SiO ₂ ), the germanium (Ge) is pushed to the interface, the silicon germanium (SiGe) layer at a certain thickness A germanium oxide film GeO ₂ is formed on the top. The thickness of the oxide film required to generate the germanium oxide film (GeO ₂ ) should be thicker when dry oxidation than wet oxidation, and in the case of the gate oxide film, the thickness of the oxide film is thin so that germanium (Ge) remains. The accumulation of germanium (Ge) during the oxide film growth becomes a factor that makes the concentration of germanium (Ge) higher. The accumulation of germanium (Ge) varies depending on the oxidation temperature, oxidation method (dry, wet, ozone, plasma), the composition of germanium (Ge), and the thickness of the oxide film, and prediction of this is very necessary.

5A to 5B are cross-sectional views of devices for explaining a method of manufacturing a PMOSFET having a high concentration of germanium (Ge) channels according to the present invention.

FIG. 5A illustrates that a germanium (SiGe) layer 22 and a silicon cap layer 23 are sequentially formed on a silicon substrate 21 at a low concentration, for example, at a concentration of 5 to 20 at%. It is a cross section of the condition.

FIG. 5B is a cross-sectional view of a state in which the gate oxide film 23a is formed by oxidizing the silicon cap layer 23, and a high concentration of germanium (Ge) segregation layer 22a is formed on the silicon germanium (SiGe) layer 22 during the oxidation process. In this case, the germanium (Ge) concentration of the germanium (Ge) segregation layer 22a becomes high at about 10 to 100 at%.

Subsequently, subsequent heat treatment is performed to make the distribution of germanium (Ge) segregation uniform.

FIG. 5C illustrates the gate electrode 24 by forming and patterning a polysilicon layer on the gate oxide layer 23a, forming spacers 25 on both sidewalls of the gate electrode 24, and then exposing the silicon. It is sectional drawing of the state in which the source / drain 26 was formed by injecting impurity ion into the germanium (SiGe) layer 22. FIG.

The transistor manufactured as described above uses a high concentration of the germanium (Ge) segregation layer 22a as a channel. Therefore, the thickness of the low concentration silicon germanium (SiGe) layer 22 should be very thin, and the high concentration of the germanium (Ge) segregation layer 22a should be sufficiently exhibited the quantum well effect. According to the prior patent, when the metal oxide film is used as the gate oxide film 23a, the formation of the low dielectric film is suppressed by the germanium (Ge) segregation layer 22a, so such an effect can be expected in such a structure.

FIG. 6 shows an energy band in a structure consisting of an oxide film / silicon germanium (SiGe) channel / silicon substrate as shown in FIG. 5C. The hole 27 is confined in the well by conducting quantum well formation in a balance band. Show the appearance. To achieve this structure, the silicon germanium (SiGe) layer must be in an unstressed state. The wells in the high concentration of silicon germanium (SiGe) layers are deeper and slightly sag due to the presence of low concentrations of silicon germanium (SiGe) layers. Therefore, it is important to reduce the thickness of the low concentration silicon germanium (SiGe) layer. This device contains more than 70 at% of germanium (Ge), which not only increases the transport of carriers in the material itself, but is also limited to quantum wells, reducing scattering of the carriers, and the conduction channel's position close to the surface, leading to the ability to induce current. It can be increased to improve the mutual conductivity (gm) and the cutoff frequency (f _T ).

7A to 7C are cross-sectional views illustrating a method of manufacturing an NMOSFET having a high concentration germanium (Ge) channel according to the present invention.

FIG. 7A is a cross-sectional view of a low-concentration silicon germanium (SiGe) layer 32 and a strained silicon layer 33 sequentially formed on the silicon substrate 31, wherein the silicon germanium (SiGe) layer 32 is formed. And the silicon layer 33 may be formed in a multiple structure.

The silicon germanium (SiGe) layer 32 should be formed to a thickness sufficient to serve as a stress relaxation buffer layer. In the actual experiment, a thin thickness of about 200 nm could be grown.

FIG. 7B is a cross-sectional view of a state in which a part of the silicon layer 33 is oxidized to form a gate oxide film 33a, and a high concentration of germanium (Ge) segregation layer (top) of the silicon germanium (SiGe) layer 32 during the oxidation process. 32a) is generated, followed by subsequent heat treatment to ensure uniform distribution of germanium (Ge) segregation.

FIG. 7C illustrates a gate electrode 34 by forming and patterning a polysilicon layer on the gate oxide layer 33a, forming spacers 35 on both sidewalls of the gate electrode 34, and then exposing silicon. It is sectional drawing of the state in which the source / drain 36 was formed by injecting impurity ions into the layer 33 and the silicon germanium (SiGe) layer 32. FIG.

In the transistor formed as described above, electrons are conducted in the silicon layer 33 used as a channel.

FIG. 8 illustrates an energy band in a structure consisting of an oxide film / silicon channel / silicon substrate as shown in FIG. 7C, in which a quantum well is generated in a conduction band and electrons 39 are limited to the well. Conduction occurs. Even in this case, the channel is relatively close to the surface, so it is judged that the current inducing ability is excellent. In the device having such a structure proposed by the present invention, how much the thickness of the silicon (Si) layer 33 used as a channel can be a key factor in determining the characteristics of the device.

9 is a graph showing the thickness and concentration change of the segregated high concentration silicon germanium (SiGe) layer with the change of the heat treatment temperature and time, the concentration center of the high concentration silicon germanium (SiGe) layer is lowered when the high temperature heat treatment is performed for a long time. It tends to migrate to and the maximum concentration is also lower (lines G, H, I). When implementing a NMOSFET or a PMOSFET using a heterogeneous structure of silicon germanium (SiGe), a thick silicon germanium (SiGe) layer may be required depending on conditions, and a high concentration of silicon germanium (SiGe) layer may be required. Therefore, in order to form a silicon germanium (SiGe) layer having a desired thickness and concentration, sufficient data on the thickness and concentration change according to the heat treatment time and temperature change should be obtained. At this time, it is also important to adjust the heat treatment conditions so that the strained structures do not relieve stress.

As described above, the present invention implements a channel of high mobility by using germanium (Ge) segregation which is a problem in a silicon germanium (SiGe) heterostructure MOSFET. Conventionally, research has been conducted to reduce or avoid occurrence of segregation in order to prevent deterioration of the device due to germanium (Ge) segregation, but in the present invention, a device having better characteristics using germanium (Ge) segregation To be prepared. In the present invention, the concentration of the germanium (Ge) segregation is adjusted according to the thickness control of the silicon cap layer, and it was confirmed that dopants such as boron (B) or phosphorus (P) may affect the germanium (Ge) segregation. Therefore, this can be controlled by controlling factors influencing the amount of segregation of germanium (Ge).

Subsequent heat treatment times and temperature adjustments allow control of the central position and maximum distribution of germanium (Ge) concentrations. The high-concentration silicon germanium (SiGe) layer thus obtained is determined in thickness or concentration in accordance with various applications of the channel layer in the PMOSFET or the layer just below the interface in the NMOSFET. The last expected effect is that the high concentration of silicon germanium (SiGe) layer has been reported to be used as a diffusion barrier of boron (B) or to a low dielectric film formation prevention layer in high-k dielectric metal oxide layer. May appear. Such a high mobility channel can improve the channel conductivity of the device and improve the cutoff frequency of the high frequency (RF) device.

Claims (7)

Sequentially forming a silicon germanium layer and a silicon layer on a semiconductor substrate, Oxidizing the silicon layer such that a germanium segregation layer is formed on the silicon germanium layer; Method of manufacturing an active layer of a semiconductor device comprising the step of heat treatment to uniformize the germanium distribution of the germanium segregation layer. The method of claim 1, wherein the silicon germanium layer and the silicon layer are formed in a multiple structure. The method of claim 1, wherein the germanium concentration of the silicon germanium layer is 5 to 20 at%. The method of claim 1, wherein only a partial thickness of the silicon layer is oxidized during the oxidation process. The method of claim 1, wherein the thickness of the germanium segregation layer is determined by a thickness, an oxidation time, and a temperature of the silicon layer. The method according to claim 1, wherein the germanium concentration of the germanium segregation layer is 10 to 100 at%, and is determined by the thickness of the silicon layer. Forming a polysilicon layer on the active layer formed by the method according to any one of claims 1 to 6 and then patterning to form a gate electrode, And forming a source and a drain by implanting impurity ions into the exposed silicon germanium layer after forming spacers on both sidewalls of the gate electrode.