KR20030069407A - Method of manufacturing a heterojunction CMOS transistor in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a complementary metal oxide semiconductor(CMOS) transistor of a semiconductor device having a heterojunction structure is provided to use a conventional setup for fabricating a CMOS transistor by forming PMOS and NMOS transistors with a heterojunction structure composed of SiGe and Si on the same substrate. CONSTITUTION: The first SiGe layer(22) is formed on a silicon substrate(21). A p-well(23a), an n-well(23b) and an isolation layer(24) are formed in the first SiGe layer. The second SiGe layer(26) is formed on the n-well. A silicon layer(27) is formed on the second SiGe layer and the p-well. A predetermined thickness of the upper portion of the silicon layer is oxidized to form a gate oxide layer through a thermal oxidation process. A gate electrode(29), a gate spacer(31), a source/drain(30) and a silicide layer(32) are formed on the n-well and the p-well.

Description

Method for manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure {Method of manufacturing a heterojunction CMOS transistor in a semiconductor device}

The present invention relates to a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure, and more particularly, to a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure in which a silicon-germanium layer is formed by CVD (Chemical Vapor Deposition).

In general, most semiconductor integrated circuits consist of CMOS circuits. CMOS circuits are fabricated on silicon substrates, and silicon has the advantages of low production cost and high density-high integration.

However, in recent years, as the data transfer amount and the data processing speed thereof are greatly increased, researches to overcome the limitations of the characteristics of silicon have been continuously conducted as the high-density, high-density capability and fast operation speed are urgently needed.

1 is a cross-sectional view of a state in which a PMOS transistor and an NMOS transistor generally used in a CMOS circuit are formed.

Referring to FIG. 1, an isolation layer 12 is formed in an isolation region of a silicon substrate 11, a well is formed in an active region in which an element is formed, and the active regions include a P well region 13a and an n well region ( 13b). In the P well region 13a and the n well region 13b, the gate oxide layer 14, the gate electrode 15, the gate spacer 16, the source / drain 17a and 17b having the LDD structure, and the silicide layer 18 are formed. NMOS transistor 110 and PMOS transistor 120 made of each is manufactured.

As described above, the NMOS transistor 110 and the PMOS transistor 120 are manufactured on a silicon substrate made of pure silicon. Since silicon has a disadvantage of low mobility, it is difficult to implement a circuit requiring high density and ultra-high speed of operation. Not suitable

As an alternative to overcome this problem, the most anticipated technology is a technique of manufacturing a transistor in a heterojunction structure by adding germanium to silicon, and it is possible to obtain an operation speed comparable to other compound semiconductor devices. This technique basically states that silicon and germanium have the same group 4 elements but different bandgap energies (e.g., 1.12 eV for silicon, 0.68 eV for germanium) and different distances between atoms (e.g., 0.5431 for silicon). nm, germanium is 0.5646nm). That is, in the case of an NMOS transistor, when stressed silicon is used as a channel layer, carrier mobility increases due to a band gap energy difference and stress between silicon and silicon-germanium (SiGe). Increasing the mobility of the carrier is to increase the operating speed of the device can manufacture a transistor having an ultra-fast operating characteristics. In the case of PMOS transistors, silicon-germanium is used as the channel layer instead of silicon to obtain ultra-fast operating characteristics.

Metal-oxide-semiconductor field effect transistors (MOSFETs) using heterojunctions of silicon-germanium / silicon show superior characteristics in terms of gain and carrier mobility than conventional silicon transistors, but the channel structures of NMOS transistors and PMOS transistors are different. It is very difficult to fabricate together on the same substrate because it is very unstable thermally.

In addition, when germanium is added to silicon, various problems occur in the process, and only a few of them are described as follows.

First, germanium and silicon have an advantage that stress is generated because the distance between atoms is different, but it is very difficult to form a silicon-germanium layer on the silicon substrate by the epitaxial growth method. The structure that epitaxially grows a material having a different atomic distance from silicon on a substrate made of silicon is called a heterojunction structure, and a silicon-germanium layer is mainly formed by a molecular beam epitaxial (MBE) and CVD method. As it is added, the thickness of the epilayer that can be grown without defects while maintaining stress is reduced.

Second, since the silicon-germanium layer cannot grow an oxide film having good properties unlike pure Si, it is difficult to form a gate oxide film of a transistor. In fact, the gate oxide film is absolutely important so that the performance of the transistor is determined by the gate oxide film. Unlike the silicon oxide film, the germanium oxide is poor in characteristics and is not suitable for making a good device. That is, segregation of germanium occurs in the process of performing the oxidation process to form the gate oxide film, and defects occur at the interface between the oxide film and the semiconductor substrate, thereby degrading the characteristics of the device. Therefore, even when a transistor is formed by using a heterojunction structure of silicon-germanium, the top layer before forming the gate oxide film should be made of a silicon layer instead of the silicon-germanium layer to obtain a good gate oxide film. In addition, since the same problem occurs not only in the process of forming the gate oxide film but also in the process of forming the field oxide film, it is difficult to apply the process of forming the field oxide film at a high temperature of 900 ° C. or less over a long time on the silicon substrate as it is. For this reason, the low temperature oxide film (LTO) is mainly used, but the low temperature oxide film has a disadvantage in that it is not suitable for a high density structure.

Third, it is difficult to implement a CMOS transistor made of silicon-germanium / silicon on the same silicon substrate. The biggest obstacle is that the epistructures of PMOS transistors and NMOS transistors are different. The channel layer of the PMOS transistor is a silicon-germanium layer and the channel layer of the NMOS transistor is not only different from each other as the silicon layer, but also the stress relaxation buffer layer immediately below the channel layer is opposite to the silicon layer and the silicon-germanium layer, respectively. For this reason, a CMOS transistor using a silicon-germanium heterojunction has not been reported so far, and PMOS transistors and NMOS transistors are currently being developed independently.

As described above, the silicon-germanium structure is not only complicated in the process and slow in progress compared to the silicon structure, but also has difficulty in manufacturing the NMOS transistor and the PMOS transistor on the same substrate.

Accordingly, the present invention forms a silicon-germanium epi layer on the substrate by CVD at a high temperature, and forms a silicon layer after forming a channel layer made of silicon-germanium only on the n well where the PMOS transistor is to be formed by the selective epitaxial growth method. By using the sacrificial layer for forming the gate oxide film in the PMOS transistor region, and also as the channel layer in the NMOS transistor region, to provide a method for manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure that can solve the above problems. The purpose is.

1 is a cross-sectional view of a state in which a PMOS transistor and an NMOS transistor generally used in a CMOS circuit are formed.

2A to 2G are cross-sectional views of devices for describing a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: semiconductor substrate 22: first SiGe layer

12, 24: device isolation layer 13a, 23a: p well

13b, 23b; n well 14, 28: gate oxide film

25 growth preventing film 26 second SiGe layer

27 silicon layer 15, 29 gate electrode

16, 31: gate spacer 30a: low concentration ion implantation layer

30b: high concentration ion implantation layer 17a, 17b, 30: source / drain

18, 32: silicide layer 110, 210: NMOS transistor

120, 220: PMOS transistor

The method for manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure according to the present invention includes the steps of forming a first SiGe layer on a silicon substrate, forming a p well, an n well, and an isolation layer on the first SiGe layer; forming a second oxide layer on the n well, forming a silicon layer on the second SiGe layer and the p well, and oxidizing the upper portion of the silicon layer by a predetermined thickness to form a gate oxide layer. And forming a gate electrode, a gate spacer, a source / drain, and a silicide layer on the n well and the p well.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

2A to 2G are cross-sectional views of devices for describing a method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure according to the present invention.

Referring to FIG. 2A, after forming a first SiGe layer 22 serving as a buffer layer by RPCVD at a high temperature to relieve stress on the silicon substrate 21, the p well 23a may be formed in the first SiGe layer 22. ), the n well 23b and the device isolation film 24 are formed to define the device formation region. Thereafter, after forming a photoresist pattern (not shown) exposing only the p well 23a region, a growth prevention layer 25 is formed on the p well 23a. The growth prevention layer 25 prevents the growth of the second SiGe layer on the n well 23b in a subsequent process of growing the second SiGe layer on the n well 23b and prevents the growth of the second SiGe layer only on the p well 23a. The SiGe layer is formed to be grown, and may be formed of a SiNx film.

In this case, the first SiGe layer 22 serving as the buffer layer is formed to have a germanium concentration of 10% to 30%, and the stress must be sufficiently relaxed, and the density of defects on the surface must be very low. A stable state must be maintained even after forming a well drive-in or device isolation layer. On the other hand, the device isolation layer 24 is formed by a local oxidation isolation (LOCOS) method, it may be formed by a device isolation process using a trench process. In fact, when the device isolation film 24 is formed by wet oxidation, SiGe can significantly reduce the oxide film growth time since the oxide film growth rate is several times faster than Si.

Referring to FIG. 2B, a second SiGe layer 26 to be a channel layer of the PMOS transistor is formed on the n well 23b by the selective epitaxial growth (SEG).

The core of the manufacturing process of a semiconductor device having a heterojunction structure composed of SiGe is channel layer epitaxial growth. That is, the channel layer structure of the NMOS transistor and the PMOS transistor is different from that of the CMOS transistor of the general silicon structure, and thus a more complicated process is required. In case of PMOS transistor, deposition of SiGe epi layer with Ge composition higher than that of substrate is required for offset of balance band, whereas in case of NMOS transistor, SiGe epi layer or lower pure Ge composition than substrate is required. Deposition of the Si layer is required.

Accordingly, the second SiGe layer 26 is formed to have a germanium concentration of 30% to 50% of the first SiGe layer 22 as a buffer layer, and a quantum well is formed in a balance band according to the germanium concentration. As a result, when holes, which are carriers of the PMOS transistors to be formed on the n well 23b, flow through the quantum wells, the holes have high mobility, and the PMOS transistors have ultrafast operating characteristics.

In addition, if the second SiGe layer 26 is formed by selective epitaxial growth after the well forming process and the LOCOS process, stress relaxation of the channel layer can be prevented, and when the epitaxial epitaxial growth method is applied when forming the channel layer, Since the SiGe layer is not grown on the separator 24, there is no need to remove the SiGe layer on the device separator 22, thereby simplifying the process.

Referring to FIG. 2C, after removing the growth prevention layer 25 on the p well 23a, the silicon layer 27 is disposed on the second SiGe layer 26 and the p well 23a formed on the n well 23b. Form.

In the case of a PMOS transistor, in order to form a gate oxide film of excellent film quality, a gate oxide film must be formed on the silicon layer. Therefore, the top layer must be a pure silicon layer before forming the gate oxide film.

The silicon layer 27 is formed to a thickness of 50 to 200Å, it can be formed by the selective epitaxial growth method to simplify the process. At this time, the silicon layer 27 formed in the p well 23a serves as a channel layer of the NMOS transistor to be manufactured in the p well 23a, and the silicon formed on the second SiGe layer 26 on the n well 23b. The layer 27 serves as a sacrificial silicon layer for forming a gate oxide film. At this time, since the thickness of each layer is sufficiently thinner than the device isolation layer 24 at about 50 to 200Å, there is no problem in device isolation.

In the above, the silicon layer 27 formed in the p-well 23a causes offset of the conduction band by stress, thereby contributing to increase the mobility of electrons. That is, the PMOS transistor uses the second SiGe layer 26 formed on the n well 23b as the channel layer, and the NMOS transistor uses the silicon layer 27 formed on the p well 23a as the channel layer. It is manufactured on the silicon substrate 21. Therefore, based on the germanium composition of the first SiGe layer 22 serving as a substrate as a buffer layer, the PMOS transistor is manufactured in the n well 23b of the first SiGe layer 22 with a higher germanium composition, The NMOS transistor is fabricated in the p well 23a of the first SiGe layer 22 with a lower germanium composition.

Note that the silicon layer 27 is used as the channel layer of the NMOS transistor and at the same time as the sacrificial silicon layer for forming the gate-thermal oxide film of the PMOS transistor, the thickness must be properly adjusted. That is, if the silicon layer 27 is formed too thick on the n well 23b, the thickness of the gate oxide film of the PMOS transistor becomes too thick, thereby reducing the gain, and thus the thickness more than necessary for the oxide film growth is undesirable. However, in the case of the NMOS transistor, the thickness of the channel layer must be secured to 50 mV or more, and thus the thickness of the silicon layer 27 formed on the p well 23a must be secured to some extent.

Referring to FIG. 2D, the silicon layer 27 is oxidized by a thermal oxidation process to form a gate oxide film 28 on the n well 23b and p well 23a regions.

In the above, the gate oxide film 28 is formed by a general thermal oxidation method, so that it can be easily applied to mass production, and the gate oxide film may be formed of a metal oxide film.

In this case, the gate oxide layer 28 is formed on the silicon layer 27 while the upper portion of the silicon layer 27 is oxidized to a predetermined thickness in the p well 23a region, and the remaining silicon layer 27 is a channel layer. Used. Meanwhile, in the n well 23b region, the upper portion of the silicon layer 27 is oxidized to a predetermined thickness so that the gate oxide film 28 is formed on the silicon layer 27, and the silicon layer 27 is disposed below the gate oxide film 28. ) Is left, but due to the difference in the band gap energy between the silicon layer 27 and the second SiGe layer 26, no channel is formed in the silicon layer 27, but a channel is formed in the second SiGe layer 26. Therefore, the silicon layer 27 remains under the gate oxide film 28 in the n well 23b region as in the p well 23a region, but the channel layer becomes the second SiGe layer 26.

Referring to FIG. 2E, after the conductive material is deposited, the gate electrode 29 is formed on the n well 23b and the p well 23a by patterning the conductive material and the gate oxide layer 28 by an etching process. In this case, a metal material may be used as the conductive material, and preferably, a polysilicon layer is used.

Referring to FIG. 2F, the low concentration ion implantation process is performed to form the low concentration ion implantation layer 30a on both sides of the gate electrode, the gate spacer 31 is formed on the sidewall of the gate electrode 29, and the high concentration ion implantation process is performed. The high concentration ion implantation layer 30b is formed. As a result, gate spacers 31 are formed on both side walls of the gate electrode 29, and source / drain 30 having an LDD structure is formed on both sides of the gate electrode 29, respectively.

The low concentration ion implantation process, the spacer formation process, and the high concentration ion implantation process proceed in the same general steps as those performed when the transistor is formed on the silicon substrate.

Referring to FIG. 2G, the silicide layer 32 is formed on the gate electrode 29 and the source / drain 30 to lower the contact resistance.

As a result, an NMOS transistor 210 having a silicon layer 27 as a channel layer is manufactured in the p well 23a, and a PMOS transistor 220 having a second SiGe layer 26 as a channel layer in the n well 23b. Is prepared.

As described above, the present invention applies a semiconductor manufacturing process, which is generally performed, to manufacture a PMOS transistor and an NMOS transistor having a heterojunction structure composed of SiGe / Si on the same substrate. In other words, most of the processes such as device isolation and gate oxide growth, which are the core of the MOSFET process, can be performed using a conventional silicon transistor CMOS transistor manufacturing process. have. In addition, the additional process is only three epi growths, one photo-lithography, and one etching process, which can improve integration density and operation speed several times over conventional CMOS transistors. Can be.

Claims (5)

Forming a first SiGe layer on the silicon substrate, Forming a p well, an n well, and an isolation layer on the first SiGe layer; Forming a second SiGe layer on the n well; Forming a silicon layer on the second SiGe layer and the p well; Thermally oxidizing an upper portion of the silicon layer by a predetermined thickness to form a gate oxide film; And forming a gate electrode, a gate spacer, a source / drain, and a silicide layer on the n well and the p well. The method of claim 1, wherein the second SiGe layer is formed only on the n well by a selective epitaxial growth method after forming a growth barrier on the p well, and the growth barrier is removed before the silicon layer is formed. Etching method of the platinum thin film and the ferroelectric thin film characterized in that. The method of claim 1 or 2, wherein the second SiGe layer is formed by a selective epitaxial growth method, and the composition of germanium is 30% to 50%, the method of manufacturing a CMOS transistor of a semiconductor device having a heterojunction structure. . The method of claim 1, wherein the silicon layer is formed to a thickness of 50 to 200 kHz. 2. The method of claim 1, wherein the silicon layer is formed so that the silicon layer remains at a thickness of at least 30 GPa even after a gate oxide film made of a thermal oxide film or a metal oxide film is formed.