KR20030082084A - Method for preventing short channel by using trench formation - Google Patents
Method for preventing short channel by using trench formation Download PDFInfo
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- KR20030082084A KR20030082084A KR1020020020626A KR20020020626A KR20030082084A KR 20030082084 A KR20030082084 A KR 20030082084A KR 1020020020626 A KR1020020020626 A KR 1020020020626A KR 20020020626 A KR20020020626 A KR 20020020626A KR 20030082084 A KR20030082084 A KR 20030082084A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 230000001131 transforming effect Effects 0.000 abstract 1
- 239000007943 implant Substances 0.000 description 14
- 125000001475 halogen functional group Chemical group 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 트랜치 형성을 이용한 쇼트 채널 방지방법에 관한 것으로, 특히 에스티아이(shallow trench for transistor isolation : STI) 패턴 형성 시에 카비티(cavity)를 위한 게이트 영역에 트랜치를 형성하여 역 쇼트 채널(reverse shortchannel) 현상을 방지할 수 있도록 하는 방법에 관한 것이다.The present invention relates to a short channel prevention method using trench formation. In particular, when a shallow trench for transistor isolation (STI) pattern is formed, a trench is formed in a gate region for a cavity to reverse a reverse short channel. ) Is to prevent the phenomenon.
통상적으로, 소스 드레인 접합(source drain junction)에서의 디플렉션(depletion) 확장을 막기 위해 스페이서(spacer) 형성 전후에 헤이로우(halo) 또는 포켓 임플란트(pocket implant)를 진행하여 역 쇼트 채널을 방지한다.Typically, a halo or pocket implant is run before and after spacer formation to prevent reverse expansion at the source drain junction to prevent reverse short channel. .
즉, 도 1에 도시된 바와 같이, 헤이로우 임플란트(halo implant) 또는 포켓 임플란트(pocket implant) 공정 과정을 진행하여 N+S/D 접합(junction)에서의 쇼트 채널 형성 시에 발생되는 펀치 스로우 블랙다운을 방지하여 디플렉션(depletion) 확장을 막을 수 있는 것이다.That is, as shown in FIG. 1, a punch throw black generated when a short channel is formed at an N + S / D junction by performing a halo implant or a pocket implant process. You can prevent the expansion of the deflation by preventing the down.
그러나, 스페이서(spacer) 형성 전후에 헤이로우 임플란트(halo implant) 또는 포켓 임플란트(pocket implant) 공정 과정을 진행하게 되어 역 쇼트 채널(reverse short channel) 현상을 제거할 수 없게 되는 문제점이 있었다.However, there is a problem in that a reverse short channel phenomenon cannot be eliminated because a process of a halo implant or a pocket implant is performed before and after forming a spacer.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로서, 그 목적은 에스티아이(shallow trench isolation : STI) 패턴 형성 시에 카비티(cavity)를 위한 트랜치(trench)를 트랜지스터가 형성되는 실리콘 표면 밑에 형성하여 역 쇼트 채널 현상을 방지할 수 있도록 하는 트랜치 형성을 이용한 쇼트 채널 방지방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems, the object of which is to form a trench for cavity when the shallow trench isolation (STI) pattern is formed under the silicon surface where the transistor is formed. The present invention provides a method for preventing a short channel using trench formation so as to prevent the reverse short channel phenomenon.
상술한 목적을 달성하기 위하여 본 발명에서 트랜치 형성을 이용한 쇼트 채널 방지방법은 STI 패턴을 형성하는 경우, 게이트 영역에 트랜치 패턴(trenchpattern)을 형성하는 단계; 형성된 트랜치 패턴 상에 산화물을 증착(deposition)하는 단계; 증착된 산화물상에 씨엠피(chemical mechanical polishing : CMP) 공정을 통해 평탄화 작업을 수행하는 단계; 평탄화 작업 후에 산화물을 채우는 작업 및 질화물을 스트립(strip)하며, 형성된 트랜치 패턴(trench pattern)상에 서멀 산화물(thermal oxide)을 채우는 단계; 비오이(Buffered Oxide Etch : BOE)가 있는 세정 공정을 통해 실리콘 표면에 잔재하는 산화막을 제거하는 단계; 세정 공정이 완료된 상태에서 셀렉티브 적층(epitaxial) 실리콘 필름을 증착(deposition)하는 단계; 증착(deposition)된 필름에 대하여 고온 열공정을 진행하면, 서멀 산화물(thermal oxide)이 채워진 트랜치 패턴(trench pattern)이 카비티(cavity)로 형성되는 단계; 카비티(cavity)로 형성된 후, 반도체 생산을 위한 공정 과정을 계속적으로 수행하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, a short channel prevention method using trench formation may include forming a trench pattern in a gate region when forming an STI pattern; Depositing an oxide on the formed trench pattern; Performing planarization on a deposited oxide through a chemical mechanical polishing (CMP) process; Stripping the oxide after the planarization operation and stripping the nitride, and filling a thermal oxide on the formed trench pattern; Removing the oxide film remaining on the surface of the silicon through a cleaning process with a buffered oxide etch (BOE); Depositing a selective epitaxial silicon film in a state where the cleaning process is completed; When a high temperature thermal process is performed on the deposited film, a trench pattern filled with a thermal oxide is formed into a cavity; After forming the cavity (cavity), it characterized in that it comprises the step of continuously performing a process for producing a semiconductor.
도 1은 종래 헤이로우(halo) 또는 포켓 임플란트(pocket implant)를 진행하여 쇼트 채널을 방지하는 도면이며,1 is a view for preventing a short channel by proceeding a conventional halo (pocket) or pocket implant (pocket implant),
도 2a 내지 도 2e는 본 발명에 따른 트랜치 형성을 이용하여 쇼트 채널을 방지하기 위한 공정방법에 대하여 도시한 도면이다.2A to 2E illustrate a process method for preventing a short channel using trench formation according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>
10 : STI 20 : 트랜치10: STI 20: Trench
30 : 산화물 40 : 서멀 산화물을 갖는 트랜치30: oxide 40: trench with thermal oxide
50 : 적층(EPI) 증착 60 : 열공정50: deposition (EPI) deposition 60: thermal process
70 : 카비티(cavity)70: cavity
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 트랜치 형성을 이용하여 쇼트 채널을 방지하기 위한 공정방법에 관한 것이다.2A-2E relate to a process method for preventing short channels using trench formation in accordance with the present invention.
먼저, 도 2a를 참조하면, 에스티아이(shallow trench for transistor isolation : STI)(10) 패턴을 형성하는 경우, 게이트 영역에 트랜치 패턴(trench pattern)(20)을 형성한다.First, referring to FIG. 2A, when forming a shallow trench for transistor isolation (STI) 10 pattern, a trench pattern 20 is formed in a gate region.
트랜치 패턴(20)을 형성한 다음에, 형성된 패턴 상에 산화물을증착(deposition)하고, 증착된 산화물상에 씨엠피(chemical mechanical polishing : CMP) 공정을 통해 평탄화 작업을 수행한다.After forming the trench pattern 20, an oxide is deposited on the formed pattern, and a planarization operation is performed on the deposited oxide through a chemical mechanical polishing (CMP) process.
평탄화 작업을 수행한 후, 도 2b와 같이, 산화물을 채우는 작업(filling oxide)(30) 및 질화물을 스트립(strip)하며, 형성된 트랜치 패턴(trench pattern)상에 서멀 산화물(thermal oxide)을 채운다(40).After the planarization operation is performed, as shown in FIG. 2B, a filling oxide 30 and a nitride are stripped, and a thermal oxide is filled on the formed trench pattern ( 40).
이후, 비오이(Buffered Oxide Etch : BOE)가 있는 세정 공정을 통해 실리콘 표면에 잔재하는 산화막을 제거한다.Thereafter, an oxide film remaining on the surface of the silicon is removed through a cleaning process with a buffered oxide etch (BOE).
실리콘 표면에 잔재하는 산화막에 대하여 세정 공정이 완료되면, 도 2c에 도시된 바와 같이, 셀렉티브 적층(epitaxial) 실리콘 필름(50)을 증착(deposition)한다.When the cleaning process is completed with respect to the oxide film remaining on the silicon surface, as shown in FIG. 2C, a selective epitaxial silicon film 50 is deposited.
증착(deposition) 과정이 완료된 후, 도 2d와 같이, 셀렉티브 적층 실리콘 필름에 대하여 고온 열공정(60)을 진행하며, 서멀 산화물(thermal oxide)이 채워진 트랜치 패턴(trench pattern)이 카비티(cavity)(70)로 형성된다.After the deposition process is completed, a high temperature thermal process 60 is performed on the selective stacked silicon film as shown in FIG. 2D, and a trench pattern filled with a thermal oxide is formed in a cavity. 70 is formed.
마지막으로, 카비티(cavity)(70)가 형성된 후, 도 2e와 같이, 반도체 생산을 위한 공정 과정을 계속적으로 수행하면, 기존의 스페이서(spacer) 형성 전후에 헤이로우 임플란트(halo implant) 또는 포켓 임플란트(pocket implant) 공정 과정을 진행할 경우, 발생되는 역 쇼트 채널(reverse short channel) 현상을 제거할 수 있는 것이다.Finally, after the cavity 70 is formed, as shown in FIG. 2E, if the process for semiconductor production is continuously performed, a halo implant or pocket is formed before and after the formation of a conventional spacer. In the case of an implant (pocket implant) process, it is possible to eliminate the reverse short channel (phenomena) generated.
그러므로, 본 발명은 에스티아이(shallow trench isolation : STI) 패턴 형성 시에 카비티(cavity)를 위한 트랜치(trench)를 트랜지스터가 형성되는 실리콘 표면 밑에 형성함으로써, 기존의 스페이서(spacer) 형성 전후에 헤이로우 임플란트(halo implant) 또는 포켓 임플란트(pocket implant) 공정 과정을 진행할 경우, 발생되는 역 쇼트 채널(reverse short channel) 현상을 제거할 수 있는 효과가 있다.Therefore, the present invention forms a trench for the cavity under the silicon surface where the transistor is formed when forming a shallow trench isolation (STI) pattern, and thus before and after forming a conventional spacer. In the case of an implant (halo implant) or a pocket implant (pocket implant) process, there is an effect that can remove the reverse short channel phenomenon occurs.
Claims (5)
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| KR10-2002-0020626A KR100489526B1 (en) | 2002-04-16 | 2002-04-16 | Method for preventing short channel by using trench formation |
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| KR10-2002-0020626A KR100489526B1 (en) | 2002-04-16 | 2002-04-16 | Method for preventing short channel by using trench formation |
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| KR940009355B1 (en) * | 1991-11-09 | 1994-10-07 | 삼성전자주식회사 | Semiconductor device and manufacturing method thereof |
| KR100366740B1 (en) * | 1998-04-24 | 2003-01-06 | 가부시끼가이샤 도시바 | Semiconductor device and method of fabricating thereof |
| JP2000307112A (en) * | 1999-04-26 | 2000-11-02 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
| JP2001093887A (en) * | 1999-09-22 | 2001-04-06 | Toshiba Corp | Method for manufacturing semiconductor device |
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