KR100489526B1 - Method for preventing short channel by using trench formation - Google Patents
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- KR100489526B1 KR100489526B1 KR10-2002-0020626A KR20020020626A KR100489526B1 KR 100489526 B1 KR100489526 B1 KR 100489526B1 KR 20020020626 A KR20020020626 A KR 20020020626A KR 100489526 B1 KR100489526 B1 KR 100489526B1
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 11
- 239000007943 implant Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims abstract description 4
- 230000002265 prevention Effects 0.000 claims description 5
- 150000003376 silicon Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
본 발명은 STI 패턴 형성 시에 카비티를 위한 트랜치를 트랜지스터가 형성되는 실리콘 표면 밑에 형성하여 역 쇼트 채널 현상을 방지하기 위한 것으로, 이를 위한 작용은 STI 패턴을 형성하는 경우, 게이트 영역에 트랜치 패턴을 형성하는 단계와, 형성된 트랜치 패턴 상에 산화물을 증착하는 단계와, 증착된 산화물상에 CMP 공정을 통해 평탄화 작업을 수행하는 단계와, 평탄화 작업 후에 산화물을 채우는 작업 및 질화물을 스트립하며, 형성된 트랜치 패턴상에 서멀 산화물을 채우는 단계와, BOE가 있는 세정 공정을 통해 실리콘 표면에 잔재하는 산화막을 제거하는 단계와, 세정 공정이 완료된 상태에서 셀렉티브 적층(epitaxial) 실리콘 필름을 증착하는 단계와, 증착된 필름에 대하여 고온 열공정을 진행하면, 서멀 산화물이 채워진 트랜치 패턴이 카비티로 형성되는 단계와, 카비티로 형성된 후, 할로 임플란트 또는 포켓 임플란트 공정 과정을 진행하는 단계를 포함한다. 따라서, 기존의 스페이서 형성 전후에 할로 임플란트 또는 포켓 임플란트 공정 과정을 진행할 경우, 발생되는 역 쇼트 채널 현상을 제거할 수 있는 효과가 있다. The present invention is to prevent the reverse short channel phenomenon by forming a trench for the cavity under the silicon surface on which the transistor is formed when forming the STI pattern, the action for this is to form a trench pattern in the gate region when forming the STI pattern Forming, depositing an oxide on the formed trench pattern, performing a planarization operation on the deposited oxide through a CMP process, filling the oxide and stripping nitride after the planarization operation, and forming a trench pattern Filling the thermal oxide on the substrate, removing the oxide film remaining on the silicon surface through a BOE cleaning process, depositing a selective epitaxial silicon film in a state where the cleaning process is completed, and depositing the deposited film. When the high temperature thermal process is performed, the trench pattern filled with thermal oxide forms a cavity. And forming a cavity, and then proceeding to a halo implant or pocket implant process. Therefore, when the halo implant or the pocket implant process is performed before and after the formation of the existing spacer, there is an effect that can remove the reverse short channel phenomenon generated.
Description
본 발명은 트랜치 형성을 이용한 쇼트 채널 방지방법에 관한 것으로, 특히 에스티아이(shallow trench for transistor isolation : STI) 패턴 형성 시에 카비티(cavity)를 위한 게이트 영역에 트랜치를 형성하여 역 쇼트 채널(reverse short channel) 현상을 방지할 수 있도록 하는 방법에 관한 것이다.The present invention relates to a short channel prevention method using trench formation. In particular, when a shallow trench for transistor isolation (STI) pattern is formed, a trench is formed in a gate region for a cavity to reverse a short short channel. channel) to prevent the phenomenon.
통상적으로, 소스 드레인 접합(source drain junction)에서의 디플리션(depletion) 확장을 막기 위해 스페이서 형성 전후에 할로 또는 포켓 임플란트를 진행하여 역 쇼트 채널을 방지한다.Typically, halo or pocket implants are carried out before and after spacer formation to prevent reverse short channel expansion to prevent depletion expansion at the source drain junction.
즉, 도 1에 도시된 바와 같이, 할로 임플란트 또는 포켓 임플란트 공정 과정을 진행하여 N+S/D 접합에서의 쇼트 채널 형성 시에 발생되는 펀치 스로우 블랙다운을 방지하여 디플리션 확장을 막을 수 있다.That is, as shown in FIG. 1, the process of halo implants or pocket implants may be performed to prevent punch throw blackdown generated when the short channel is formed in the N + S / D junction, thereby preventing depletion expansion. .
그러나, 스페이서 형성 전후에 할로 임플란트 또는 포켓 임플란트 공정 과정을 진행하게 되어 역 쇼트 채널 현상을 제거할 수 없게 되는 문제점이 있었다. However, there is a problem in that the inverse short channel phenomenon cannot be eliminated because the halo implant or pocket implant process is performed before and after the spacer formation.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로서, 그 목적은 STI 패턴 형성 시에 카비티를 위한 트랜치를 트랜지스터가 형성되는 실리콘 표면 밑에 형성하여 역 쇼트 채널 현상을 방지할 수 있도록 하는 트랜치 형성을 이용한 쇼트 채널 방지방법을 제공함에 있다. Accordingly, the present invention has been made to solve the above-described problems, the purpose of which is to form a trench for the cavity under the silicon surface on which the transistor is formed when forming the STI pattern to prevent the reverse short channel phenomenon It is to provide a short channel prevention method using the formation.
상술한 목적을 달성하기 위하여 본 발명에서 트랜치 형성을 이용한 쇼트 채널 방지방법은 STI 패턴을 형성하는 경우, 게이트 영역에 트랜치 패턴을 형성하는 단계와, 형성된 트랜치 패턴 상에 산화물을 증착하는 단계와, 증착된 산화물상에 CMP 공정을 통해 평탄화 작업을 수행하는 단계와, 평탄화 작업 후에 산화물을 채우는 작업 및 질화물을 스트립하며, 형성된 트랜치 패턴상에 서멀 산화물을 채우는 단계와, BOE가 있는 세정 공정을 통해 실리콘 표면에 잔재하는 산화막을 제거하는 단계와, 세정 공정이 완료된 상태에서 셀렉티브 적층 실리콘 필름을 증착하는 단계와, 증착된 필름에 대하여 고온 열공정을 진행하면, 서멀 산화물이 채워진 트랜치 패턴이 카비티로 형성되는 단계와, 카비티로 형성된 후, 할로 임플란트 또는 포켓 임플란트 공정 과정을 진행하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, a method for preventing a short channel using trench formation includes forming a trench pattern in a gate region when depositing an STI pattern, depositing an oxide on the formed trench pattern, and depositing an oxide layer. Performing a planarization operation on the oxidized oxide through a CMP process, filling the oxide and stripping nitride after the planarization operation, filling a thermal oxide on the formed trench pattern, and a cleaning process with BOE. Removing the remaining oxide film, depositing the selective laminated silicon film in a state where the cleaning process is completed, and performing a high temperature thermal process on the deposited film to form a trench pattern filled with a thermal oxide. Step, and after the cavity is formed, the halo implant or pocket implant process Characterized in that it comprises a step of performing.
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 트랜치 형성을 이용하여 쇼트 채널을 방지하기 위한 공정과정을 도시한 도면이다. 2A to 2E illustrate a process for preventing short channels using trench formation according to the present invention.
즉, 도 2a를 참조하면, STI(10) 패턴을 형성하는 경우, 게이트 영역에 트랜치 패턴(20)을 형성한다. That is, referring to FIG. 2A, when the STI 10 pattern is formed, the trench pattern 20 is formed in the gate region.
트랜치 패턴(20)을 형성한 다음에, 형성된 패턴(20) 상에 산화물을 증착하고, 증착된 산화물상에 씨엠피(chemical mechanical polishing, CMP) 공정을 통해 평탄화 작업을 수행한다. After forming the trench pattern 20, an oxide is deposited on the formed pattern 20, and a planarization operation is performed on the deposited oxide through a chemical mechanical polishing (CMP) process.
평탄화 작업을 수행한 후, 도 2b와 같이, 산화물을 채우는 작업(filling oxide)(30) 및 질화물을 스트립(strip)하며, 형성된 트랜치 패턴상에 서멀 산화물(thermal oxide)(40)을 채운다.After the planarization operation is performed, as shown in FIG. 2B, a filling oxide 30 and a nitride are stripped, and a thermal oxide 40 is filled on the formed trench pattern.
이후, 비오이(Buffered Oxide Etch, BOE)가 있는 세정 공정을 통해 실리콘 표면에 잔재하는 산화막을 제거한다. Thereafter, an oxide film remaining on the surface of the silicon is removed through a cleaning process with a buffered oxide etch (BOE).
실리콘 표면에 잔재하는 산화막에 대하여 세정 공정이 완료된 다음에, 도 2c에 도시된 바와 같이, 셀렉티브 적층 실리콘 필름(50)을 증착한다. After the cleaning process is completed for the oxide film remaining on the silicon surface, as shown in FIG. 2C, the selective laminated silicon film 50 is deposited.
증착 과정이 완료된 후, 도 2d와 같이, 셀렉티브 적층 실리콘 필름(50)에 대하여 고온 열공정(60)을 진행하며, 서멀 산화물이 채워진 트랜치 패턴이 카비티(70)로 형성된다. 여기서, 고온 열공정(60)은 트랜치 패턴을 카비티로 형성하기 위한 열공정이며, 이는 통상적인 반도체 공정과정의 고온 열공정인 것이다. After the deposition process is completed, as shown in FIG. 2D, the high temperature thermal process 60 is performed on the selective laminated silicon film 50, and a trench pattern filled with a thermal oxide is formed as a cavity 70. Here, the high temperature thermal process 60 is a thermal process for forming a trench pattern into a cavity, which is a high temperature thermal process of a conventional semiconductor process.
마지막으로, 카비티(70)가 형성된 후, 도 2e와 같이, 반도체 생산을 위한 공정 과정을 계속적으로 수행하면, 기존의 스페이서 형성 전후에 할로 임플란트 또는 포켓 임플란트 공정 과정을 진행할 경우, 발생되는 역 쇼트 채널 현상을 제거할 수 있다. Lastly, after the cavity 70 is formed, as shown in FIG. 2E, if the process for semiconductor production is continuously performed, an inverse short generated when the halo implant or the pocket implant process is performed before and after forming the existing spacers. Channel phenomenon can be eliminated.
그러므로, 본 발명은 STI 패턴 형성 시에 카비티를 위한 트랜치를 트랜지스터가 형성되는 실리콘 표면 밑에 형성함으로서, 기존의 스페이서 형성 전후에 할로 임플란트 또는 포켓 임플란트 공정 과정을 진행할 경우, 발생되는 역 쇼트 채널 현상을 제거할 수 있는 효과가 있다. Therefore, the present invention forms a trench for the cavity under the silicon surface where the transistor is formed when forming the STI pattern, thereby preventing the reverse short channel phenomenon generated when the halo implant or pocket implant process is performed before and after forming the existing spacer. It can be removed.
도 1은 종래 할로(halo) 또는 포켓 임플란트(pocket implant)를 진행하여 쇼트 채널을 방지하는 도면이며,1 is a diagram for preventing a short channel by performing a conventional halo or pocket implant.
도 2a 내지 도 2e는 본 발명에 따른 트랜치 형성을 이용하여 쇼트 채널을 방지하기 위한 공정방법에 대하여 도시한 도면이다. 2A to 2E illustrate a process method for preventing a short channel using trench formation according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : STI 20 : 트랜치10: STI 20: Trench
30 : 산화물 40 : 서멀 산화물을 갖는 트랜치30: oxide 40: trench with thermal oxide
50 : 적층(EPI) 증착 60 : 열공정50: deposition (EPI) deposition 60: thermal process
70 : 카비티(cavity)70: cavity
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930011210A (en) * | 1991-11-09 | 1993-06-24 | 김광호 | Semiconductor device and manufacturing method thereof |
| KR19990083427A (en) * | 1998-04-24 | 1999-11-25 | 니시무로 타이죠 | Semiconductor device and method of fabricating thereof |
| JP2000307112A (en) * | 1999-04-26 | 2000-11-02 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JP2001093887A (en) * | 1999-09-22 | 2001-04-06 | Toshiba Corp | Method for manufacturing semiconductor device |
| US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
-
2002
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930011210A (en) * | 1991-11-09 | 1993-06-24 | 김광호 | Semiconductor device and manufacturing method thereof |
| KR19990083427A (en) * | 1998-04-24 | 1999-11-25 | 니시무로 타이죠 | Semiconductor device and method of fabricating thereof |
| JP2000307112A (en) * | 1999-04-26 | 2000-11-02 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
| JP2001093887A (en) * | 1999-09-22 | 2001-04-06 | Toshiba Corp | Method for manufacturing semiconductor device |
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