KR20030081616A - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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Publication number
KR20030081616A
KR20030081616A KR1020020019939A KR20020019939A KR20030081616A KR 20030081616 A KR20030081616 A KR 20030081616A KR 1020020019939 A KR1020020019939 A KR 1020020019939A KR 20020019939 A KR20020019939 A KR 20020019939A KR 20030081616 A KR20030081616 A KR 20030081616A
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South Korea
Prior art keywords
pad
thin film
metal thin
semiconductor device
forming
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KR1020020019939A
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Korean (ko)
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조경수
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아남반도체 주식회사
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Priority to KR1020020019939A priority Critical patent/KR20030081616A/en
Publication of KR20030081616A publication Critical patent/KR20030081616A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing pad failure due to the oxide or particle generated on the surface of the pad by forming the second pad at the exposed portion of an uppermost metal line through the pad using pure aluminum. CONSTITUTION: After forming an uppermost metal line(3) at the upper portion of a semiconductor substrate, a pad region is formed by exposing a predetermined portion of the uppermost metal line using a protecting layer(4). A metal thin film(5) made of pure aluminum is formed on the entire surface of the resultant structure. The second pad region(200) is then formed at the upper portion of the pad region by selectively etching the metal thin film. Then, a bonding process is carried out at the second pad region.

Description

반도체 소자 제조 방법 {Fabrication method of semiconductor device}Fabrication method of semiconductor device

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 본딩패드를 형성하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a bonding pad.

통상적으로 본딩패드는 반도체 소자와 패키지를 연결해주는 단자로서의 역할을 하는 것으로, 소자의 최상층 금속배선이 일정 부분 노출된 패드를 패키지 후 핀(pin)으로 사용되는 부분과 상호 연결시켜주는 본딩 작업을 통해 반도체 소자의 배선을 전원 공급장치와 같은 외부와 전기적으로 접속하는 것이다.In general, a bonding pad serves as a terminal for connecting a semiconductor device and a package. A bonding pad interconnects a pad where the uppermost metal wiring of the device is exposed to a portion used as a pin after the package. The wiring of the semiconductor element is electrically connected to the outside such as a power supply device.

이러한 본딩패드를 이루는 금속박막은 표면에는 이물질이 없고 산화막이 형성되지 않아야 본딩 작업이 원활하게 이루어진다.The metal thin film constituting the bonding pad has no foreign matter on the surface thereof and a bonding operation is smoothly performed when no oxide film is formed.

그러나 종래기술에서는 금속배선의 표면이 산화되거나 도는 금속박막의 표면에 리프렉토리(refractory) 금속이 잔존하여, 본딩이 제대로 이루어지지 않고 본딩라인이 이탈하는 등의 문제점이 발생하였다.However, in the related art, the surface of the metal wiring is oxidized or the surface of the metal thin film (refractory) remains, so that the bonding is not properly performed, the bonding line has a problem occurs.

특히, 금속배선으로 알루미늄 합금을 사용할 경우 알루미늄 합금에 소량 함유된 구리가 쉽게 산화되어 본딩 불량을 일으켜왔다.In particular, when the aluminum alloy is used as the metal wiring, a small amount of copper contained in the aluminum alloy is easily oxidized, causing bonding failure.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 본딩 불량을 일으키지 않는 본딩 패드를 형성하는 데 있다.The present invention is to solve the problems described above, the object is to form a bonding pad that does not cause a bad bonding.

도 1a 내지 1c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 패드 상에 순수 알루미늄으로 이루어진 2차 패드를 형성하는 것을 특징으로 한다. 즉, 반도체 기판 상에 형성된 반도체 소자의 최상층 금속배선의 소정영역이 보호막으로부터 노출되어 패드를 이루는 구조에서, 패드를 통해 노출된 최상층 금속배선 상에 순수 알루미늄으로 이루어진 금속박막을 형성하는 단계; 패드의 상부에 해당하는 영역을 포함한 소정 영역의 금속박막을 제외하고 나머지 금속박막을 식각하여, 패드의 상부에 금속박막으로 이루어진 2차 패드를 형성하는 단계; 2차 패드에 본딩 작업을 수행하는 단계를 포함하여 반도체 소자를 제조한다.In order to achieve the object as described above, the present invention is characterized by forming a secondary pad made of pure aluminum on the pad. That is, in the structure in which a predetermined region of the uppermost metal wiring of the semiconductor element formed on the semiconductor substrate is exposed from the protective film to form a pad, forming a metal thin film made of pure aluminum on the uppermost metal wiring exposed through the pad; Etching the remaining metal thin film except for the metal thin film of the predetermined region including the area corresponding to the upper part of the pad, thereby forming a secondary pad made of the metal thin film on the upper part of the pad; A semiconductor device is manufactured by performing a bonding operation on a secondary pad.

이 때, 금속박막은 스퍼터링 방법을 이용하여 200℃ 이상의 증착온도에서 1000Å 내지 8000Å의 두께로 형성하는 것이 바람직하다.In this case, the metal thin film is preferably formed to a thickness of 1000 Pa to 8000 Pa at a deposition temperature of 200 ° C. or higher using a sputtering method.

이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail.

도 1a 내지 1c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판의 구조물(1), 즉 개별 소자가형성된 반도체 기판 또는 하부 금속 배선층 상부에 산화막 등으로 이루어진 절연막(2)을 형성하고, 절연막(2) 상의 소정 영역에는 최상층 금속배선(3)을 형성한다. 최상층의 금속배선(3)의 소정 영역을 제외한 나머지 상부에는 보호막(4)을 형성하고, 최상층 금속배선(3)의 소정 영역은 보호막(4)으로부터 노출되어 패드(100)를 이룬다.First, as shown in FIG. 1A, an insulating film 2 made of an oxide film or the like is formed on a structure 1 of a semiconductor substrate, that is, on a semiconductor substrate on which individual elements are formed or on a lower metal wiring layer, and a predetermined region on the insulating film 2. In the uppermost metal wiring 3 is formed. A protective film 4 is formed on the remaining portions of the uppermost metal wiring 3 except for a predetermined region, and a predetermined region of the uppermost metal wiring 3 is exposed from the protective film 4 to form a pad 100.

다음, 도 1b에 도시된 바와 같이, 상기 패드(100)를 통해 노출된 최상층 금속배선(3) 및 보호막(4)의 상부 전면에 순수한 알루미늄으로 이루어진 금속박막(5)을 1000~8000Å의 두께로 증착하고, 금속박막(5) 상에 감광막을 도포하고 노광 및 현상하여 패드의 상부를 포함한 소정 영역을 제외한 나머지가 제거된 감광막 패턴(6)을 형성한다.Next, as shown in FIG. 1B, the uppermost metal wiring 3 exposed through the pad 100 and the metal thin film 5 made of pure aluminum on the entire upper surface of the passivation layer 4 have a thickness of 1000 to 8000 Å. After the deposition, the photoresist film is coated on the metal thin film 5, and the photoresist film is exposed and developed to form a photoresist pattern 6 in which the rest except for a predetermined region including the upper part of the pad is removed.

이 때 금속박막(5)은 스퍼터링 방법을 이용하여 200℃ 이상의 온도로 증착하여 알루미늄 결정립이 가급적 커지도록 하는 것이 바람직하다.At this time, the metal thin film 5 is preferably deposited at a temperature of 200 ° C. or more using a sputtering method so that the aluminum crystal grains are made as large as possible.

금속박막(5)의 증착 후에는 250~500℃의 온도로 질소 가스 분위기에서 1분 이상의 시간동안 열처리하여 금속박막(5)과 최상층 금속배선(3)과의 접착성을 향상시킬 수도 있다.After the deposition of the metal thin film 5, heat treatment may be performed at a temperature of 250 ° C. to 500 ° C. for at least 1 minute to improve adhesion between the metal thin film 5 and the uppermost metal wiring 3.

금속박막(5)의 증착 전에 패드(100)를 통해 노출된 최상층 금속배선(3)의 상면에 형성된 산화막을 20Å 이상 식각할 수도 있다.The oxide film formed on the upper surface of the uppermost metal wiring 3 exposed through the pad 100 before the deposition of the metal thin film 5 may be etched at least 20 kPa.

다음, 도 1c에 도시된 바와 같이, 감광막 패턴(6)을 마스크로 하여 노출된 금속박막(5)을 건식 식각하여 제거한 후, 감광막 패턴(6)을 제거하고 세정 공정을 수행한다. 이로써, 패드(100) 상에는 순수한 알루미늄으로 이루어진 2차 패드(200)이 형성된다.Next, as shown in FIG. 1C, the exposed metal thin film 5 is removed by dry etching using the photoresist pattern 6 as a mask, and then the photoresist pattern 6 is removed and a cleaning process is performed. As a result, a secondary pad 200 made of pure aluminum is formed on the pad 100.

2차 패드(200) 형성 후에는 다시 한번 200~450℃의 온도로 질소 가스 분위기에서 1분 이상의 시간동안 열처리할 수도 있다.After the formation of the secondary pads 200, the heat treatment may be performed at a temperature of 200 ° C. to 450 ° C. for at least one minute in a nitrogen gas atmosphere.

상술한 바와 같이, 본 발명에서는 패드를 통해 노출된 최상층 금속배선 상에 순수한 알루미늄으로 이루어진 2차 패드를 형성하기 때문에, 패드의 금속표면에 산화물 또는 이물질이 없어서 패드 불량을 방지하는 효과가 있다.As described above, in the present invention, since the secondary pad made of pure aluminum is formed on the uppermost metal wiring exposed through the pad, there is no oxide or foreign matter on the metal surface of the pad, thereby preventing pad failure.

Claims (5)

반도체 기판 상에 형성된 반도체 소자의 최상층 금속배선의 소정영역이 보호막으로부터 노출되어 패드를 이루는 구조에서, 상기 패드를 통해 노출된 최상층 금속배선 상에 순수 알루미늄으로 이루어진 금속박막을 형성하는 단계;Forming a metal thin film made of pure aluminum on the uppermost metal wiring exposed through the pad in a structure in which a predetermined region of the uppermost metal wiring of the semiconductor device formed on the semiconductor substrate is exposed from the protective film to form a pad; 상기 패드의 상부에 해당하는 영역을 포함한 소정 영역의 금속박막을 제외하고 나머지 금속박막을 식각하여, 상기 패드의 상부에 상기 금속박막으로 이루어진 2차 패드를 형성하는 단계;Etching the remaining metal thin film except a metal thin film of a predetermined region including an area corresponding to an upper portion of the pad to form a secondary pad formed of the metal thin film on the pad; 상기 2차 패드에 본딩 작업을 수행하는 단계Performing a bonding operation on the secondary pads 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1 항에 있어서, 상기 금속박막은 1000Å 내지 8000Å의 두께로 형성하는 반도체 소자 제조 방법.The method of claim 1, wherein the metal thin film is formed to a thickness of 1000 kPa to 8000 kPa. 제 1 항에 있어서, 상기 금속박막은 스퍼터링 방법을 이용하여 200℃ 이상의 증착온도로 형성하는 반도체 소자 제조 방법.The method of claim 1, wherein the metal thin film is formed at a deposition temperature of 200 ° C. or more using a sputtering method. 제 1 항에 있어서, 상기 금속박막을 형성한 후에는 250~500℃의 온도로 질소 가스 분위기에서 1분 이상의 시간동안 열처리하는 단계를 더 포함하는 반도체 소자 제조 방법.The method of claim 1, further comprising, after forming the metal thin film, performing heat treatment at a temperature of 250 ° C. to 500 ° C. for at least one minute. 제 1 항에 있어서, 상기 2차 패드를 형성한 후에는 200~450℃의 온도로 질소 가스 분위기에서 1분 이상의 시간동안 열처리하는 단계를 더 포함하는 반도체 소자 제조 방법.The method of claim 1, further comprising, after forming the secondary pad, performing heat treatment at a temperature of 200 ° C. to 450 ° C. for at least one minute.
KR1020020019939A 2002-04-12 2002-04-12 Fabrication method of semiconductor device KR20030081616A (en)

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