KR20030079490A - Method and apparatus for driving plasma display panel - Google Patents

Abstract

PURPOSE: A method and an apparatus for driving a plasma display panel are provided to optimize an address operation condition and prevent the mis-discharge under the environment of high temperature by reducing forcibly a voltage level of a set-down voltage to a predetermined voltage level. CONSTITUTION: A method for driving a plasma display panel includes a cell reset process and a voltage level change process. The cell reset process is to reset all cells on screen by using a set-down voltage. The voltage level change process is to change forcibly a voltage level of the set-down voltage before an address period is performed to select the cells. The process for changing voltage level of the set-down voltage is characterized in that the voltage level of the set-down voltage is forcibly reduced to the predetermined voltage level before the address period is performed to select the cells.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel to prevent erroneous discharge in a high temperature environment.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. Electrodes X1 to Xm are provided.

Cells 1 for displaying any one of red, green and blue are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gradation according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. In the set-down period SD, after the rising ramp waveform Ramp-up is supplied, it starts to fall at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up, and thus the base voltage GND or the negative polarity is specified. A falling ramp waveform Ramp-down falling to the voltage level is simultaneously applied to the scan electrodes Y. Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The sustain electrode Z is supplied with a positive DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference with the scan electrode Y so as to prevent mis-discharge with the scan electrode Y.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, ramp waveforms having a small pulse width and a low voltage level are supplied to the sustain electrode Z to erase wall charges remaining in the cells of the full screen.

4 shows a conventional scan electrode driving circuit, and FIG. 5 shows output signals from the scan electrode driving circuit.

4 and 5, a conventional scan electrode driving circuit includes a scan driver 41 connected with a scan electrode Y and having a high potential scan voltage Vsc and a low potential scan voltage −Vy; A bias detector 42 connected to the scan driver 41 is provided. The low potential scan voltage (-Vy) is a base voltage GND or a specific voltage of negative polarity.

The scan driver 41 is connected in a push-pull form and switches QH of a drive integrated circuit 43 (hereinafter referred to as " IC ") connected to the scan electrode Y through an output node therebetween. QL and the third switch Q3 connected to the driving IC 43 via the first node n1 and input with the high potential scan voltage Vsc, and the second node n2 are driven. A second switch Q2 connected to the IC 43 and to which a low potential scan voltage (-Vy) is input; a fourth switch Q4 connected between the first and second nodes n1 and n2; A first switch Q1 connected between the two nodes n2 and the negative scan voltage source -Vy is provided.

The first switch QH of the driver IC 43 supplies the scan electrode Y with the high potential scan voltage Vsc supplied via the first node n1, and the second switch of the driver IC 43. QL supplies the scan electrode Y with a setdown voltage or a low potential scan voltage -Vy supplied via the second node n2. The third switch Q3 is turned on during the address period to supply the high potential scan voltage Vsc to the first node n1. The second switch Q2 is turned on during the setdown period SD to supply the second node n2 with a voltage falling to the low potential scan voltage -Vy at a predetermined falling slope determined by the RC time constant. do. The first switch Q1 is turned on during the address period to supply the low potential scan voltage -Vy to the second node n2. The fourth switch Q4 is turned on during the address period to open a current path between the first node n1 and the second node n2 to insulate between the first node n1 and the second node n2. It plays a role.

The bias detector 42 includes a zener diode ZD connected between the second node n2 and the low potential scan voltage source (-Vy), the first and second voltage divider resistors R1 and R2, and a common voltage source Vcc. And third and fourth voltage divider resistors R3 and R4 connected between the low potential scan voltage source -Vy and a comparator 44 connected to the third and fourth nodes n3 and n4.

The first and second voltage divider resistors R1 and R2 divide the voltage on the second node n2 with a predetermined voltage divider resistance ratio and supply the divided voltage Vd to the inverting terminal of the comparator 44. The third and fourth voltage divider resistors R3 and R4 divide the common voltage Vcc by a predetermined voltage divider resistance ratio to generate a reference voltage Vr, and convert the reference voltage Vr into the non-inverting terminal of the comparator 44. To feed. The reference voltage Vr is set to a voltage in FIG. 5 such that the setdown voltage no longer falls at the -Vyb potential.

The comparator 44 generates a low logic output signal when the setdown detection voltage Vd input to the inverting terminal is greater than the reference voltage Vr (Vd> Vr) and the setdown detection voltage Vd input to the inverting terminal. When the voltage is equal to or less than the reference voltage Vr (Vd? Vr), a high logic output signal is generated.

The output signal of the comparator 44 is inverted from low logic to high logic at the beginning of the address period. The timing controller (not shown) turns on the first and third switches Q1 and Q3 and turns off the fourth switch Q4 in response to the high logic output signal of the comparator 44 as shown in FIG. 5. The operating conditions of the address are set by preventing the setdown voltage from falling below the -Vyb potential. This stop of the setdown voltage at the -Vyb potential is such that an address discharge can occur when the low potential scan voltage (-Vy) and the data voltage (data) are applied to the scan electrode (Y) and the address electrode (X). To leave sufficient wall charge in the cell. The scan pulse scan is supplied to the scan electrodes Y from the time t3 set after the address operation condition is set. That is, from time t3, the switches QH and QL of the driving IC 43 repeatedly turn on / off the scan pulses to supply the scan electrodes Y to each other.

On the other hand, when the conventional PDP is operated in a high temperature environment of 50 ℃ or more as shown in Figure 6 the slope of the ramp ramp (Ramp-down) is smaller than the normal temperature environment. It is estimated that the change of setdown in the high temperature environment is caused by the change of wall charge loss and operating conditions in the cell between the normal temperature environment and the high temperature environment.

6 is a waveform diagram showing a change in setdown in a high temperature environment.

In FIG. 6, the solid line shows the ramp ramp down of the normal slope which appears in the normal temperature environment, and the dotted line shows the ramp ramp down that the slope becomes smaller in the high temperature environment of 50 ° C or higher.

Referring to FIG. 6, in the normal temperature environment, when the set-down voltage due to the ramp-down ramp down to the ground voltage GND falls at the time t0, the ramp ramp becomes gentle in the high temperature environment. down only falls to an arbitrary voltage level Vdn higher than the ground voltage GND at time t0. As a result, the conventional PDP is a wall accumulated by the setup discharge generated between the scan electrode (Y) and the sustain electrode (Z) and between the scan electrode (Y) and the address electrode (X) by the rising ramp waveform (Ramp-up) Unnecessary wall charges in the charge in the charge are not completely erased and remain in the cell by Vdn. Thus, wall discharge remaining unnecessarily in the cell before the address starts can cause an erroneous discharge even when no data voltage is applied to the address electrode Z, which can cause an address discharge. As a result, in the conventional PDP, the address down discharge occurs because the setdown voltage does not drop by a desired voltage level in a high temperature environment.

Accordingly, it is an object of the present invention to provide a method and apparatus for driving a PDP to prevent erroneous discharge in a high temperature environment.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform for driving a conventional PDP.

4 is a circuit diagram showing a conventional scan electrode driving circuit.

FIG. 5 is a waveform diagram illustrating output signals from the scan electrode driving circuit shown in FIG. 4.

6 is a waveform diagram showing a change in inclination due to high temperature in a conventional falling ramp waveform.

7 to 9 are waveform diagrams illustrating a setdown voltage changed by a method and an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

10 is a circuit diagram illustrating a driving apparatus of a plasma display panel according to a first embodiment of the present invention.

FIG. 11 is a waveform diagram illustrating input and output waveforms of the driving apparatus of the plasma display panel shown in FIG. 10.

12 is a circuit diagram illustrating a driving apparatus of a plasma display panel according to a second embodiment of the present invention.

13 and 14 are waveform diagrams illustrating input and output waveforms of the driving apparatus of the plasma display panel shown in FIG. 12.

<Description of Symbols for Main Parts of Drawings>

41,126: scan driver 42,127: bias detector

43,81,121: Driver IC 44,128: Comparator

80: control signal generator 82,122,125: OR gate

123: exclusive OR gate 124: AND gate

In order to achieve the above object, the driving method of the PDP according to the embodiment of the present invention comprises the steps of initializing the cells of the full screen using a set down voltage, and the voltage of the set down voltage before the address period for selecting a cell is started. Forcibly changing the level.

In the driving method of the PDP according to the embodiment of the present invention, the step of forcibly changing the voltage level of the setdown voltage is characterized by forcibly lowering the setdown voltage level to a predetermined voltage level before the address period starts.

The set down voltage is characterized in that it is sharply lowered at a specific time point before the address period starts.

The set-down voltage is characterized in that it gradually decreases for a period between a specific time point before the start of the address period and the start time of the address period.

The set-down voltage is characterized in that it gradually decreases during a period between a specific time point before the start of the address period and the start time of the address period.

Forcibly changing the voltage level of the set down voltage includes generating a first control signal indicative of the address period and a second control signal indicative of a period from a specific point before the address period to the start of the address period. Generating a set down control signal by performing an OR operation on the first and second control signals, and lowering the set down voltage to a predetermined voltage level at a specific time in response to the set down control signal.

The driving method of the PDP according to the embodiment of the present invention further includes supplying a high potential voltage of the scan pulse in response to the first control signal.

The step of forcibly changing the voltage level of the set down voltage includes generating a first control signal indicating an address period and a second indicating a period from a time when the set down voltage is supplied to a specific time before the address period. Generating a control signal, generating a third control signal indicative of a period from a specific point in time to the start of the address period, and fourth control instructing a point in time when the setdown voltage is lowered below a predetermined voltage level. Generating a signal, performing an AND operation on the second control signal and the fourth control signal, performing an exclusive OR operation on the third control signal and the fourth control signal, and an AND operation value and an exclusive OR operation value. Generating a setdown control signal by performing an OR operation, and lowering the setdown voltage to a predetermined voltage level in response to the setdown control signal. It should.

The driving method of the PDP according to the embodiment of the present invention further includes supplying a high potential voltage of the scan pulse in response to an AND operation value.

An apparatus for driving a PDP according to an embodiment of the present invention includes a set down voltage generator for generating a set down voltage, and a set down controller for forcibly changing the voltage level of the set down voltage before an address period for selecting a cell is started.

The set down control unit may forcibly lower the set down voltage level to a predetermined voltage level before the address period starts.

The set-down control unit includes a control signal generator for generating a first control signal indicating an address period and a second control signal indicating a period from a specific point in time before the address period to the start of the address period, and first and second controls. And an OR gate for generating a setdown control signal by performing an OR operation on the signal, and a switch element for lowering the setdown voltage to a predetermined voltage level at the specific time in response to the setdown control signal.

The driving apparatus of the PDP according to the embodiment of the present invention further includes a switch element for supplying a high potential voltage of the scan pulse in response to the first control signal.

The set-down control section includes a first control signal indicating an address period and a second control signal indicating a period from a time when the set-down voltage starts to supply to a specific time point before the address period, and a period from the specific time point to the start time of the address period. A control signal generator for generating a third control signal for indicating a; a bias detector for indicating a point in time when the set-down voltage is lowered below a predetermined voltage level; and an AND for performing an AND operation on the second control signal and the fourth control signal. An exclusive OR gate for performing an exclusive OR operation on the gate, the third control signal and the fourth control signal, an OR gate for generating a set down control signal by performing an OR operation on the output signal of the AND gate and the output signal of the exclusive OR gate, and the set down control And a switch element for lowering the setdown voltage to a predetermined voltage level in response to the signal.

The driving apparatus of the PDP according to the embodiment of the present invention further includes a switch element for supplying a high potential voltage of the scan pulse in response to the output signal of the AND gate.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 9.

Referring to FIG. 7, the method and apparatus for driving a PDP may set the setdown voltage at a time t2 when the setdown voltage does not decrease to a desired voltage level, for example, the base voltage GND, until the time t2 set before the time t3 at which the address is started. It will be forced down to the desired voltage level.

In FIG. 7, the dotted line lowered to the base voltage GN at the time t1 indicates the set down voltage optimally set in the normal temperature environment. The time t2 is set between the time t1 and the time t3. On the other hand, the set-down voltage may drop sharply at the time t2 as shown in the figure, but may be gradually lowered by a predetermined slope during the period between the time t2 and the time t3 as shown in FIG. In addition, the set-down voltage may be lowered step by step in a multi-step form between time t2 and time t3 as shown in FIG. 9.

FIG. 10 shows a driving device of the PDP according to the first embodiment of the present invention, and FIG. 11 is a waveform diagram showing an output signal and a control signal of the driving device of the PDP shown in FIG.

10 and 11, the driving apparatus of the PDP according to the first embodiment of the present invention generates the set down voltage of the falling ramp waveform lowered by a predetermined slope, and also has a high potential scan voltage Vsc and a ground voltage ( A scan driving circuit for switching the GND) to generate a scan pulse, a control signal generator 80 for controlling the scan driving circuit, and an OR gate element (hereinafter referred to as an "OR gate") 82; .

In the scan driving circuit, the first switch QH of the driving IC 81 supplies the high potential scan voltage Vsc supplied through the first node n1 to the scan electrode Y, and the driving IC ( The second switch QL of 81 supplies the scan electrode Y with a setdown voltage or a ground voltage supplied via the second node n2. The third switch Q3 is turned on during the address period to supply the high potential scan voltage Vsc to the first node n1. The second switch Q2 is turned on during the setdown period SD in response to the control signal Csetdn shown in FIG. 9 so as to fall down to the base voltage GND with a predetermined falling slope determined by the RC time constant. The voltage is supplied to the second node n2. The first switch Q1 is turned on during the address period to supply the base voltage GND to the second node n2. The fourth switch Q4 is turned on during the address period to open a current path between the first node n1 and the second node n2 to insulate between the first node n1 and the second node n2. It plays a role.

The control signal generator 80 generates the first and second control signals Cad and CH as shown in FIG. 9. The first control signal Cad maintains a high logic level during the address period, while indicating the address period by maintaining a low logic level for other periods. The second control signal CH maintains high logic for a period between the time t2 at which the setdown voltage is forcibly lowered and the time t3 at which the address is initiated, while the second control signal CH maintains low logic for other periods at the time t2 and t3. It will indicate the period between.

The OR gate 82 turns on the first switch Q1 at time t2 by performing an OR operation on the first and second control signals Cad and CH from the control signal generator 80. Then, the base voltage is supplied to the second node n2 at time t2. At this time, the second switch Q2 of the driving IC 81 is turned on by a timing controller (not shown), so that the ground voltage GND is supplied to the scan electrode Y. FIG. Meanwhile, the third switch Q3 supplies the high potential scan voltage Vsc to the first node n1 during the address period in response to the first control signal Cad.

FIG. 12 shows a driving device of the PDP according to the second embodiment of the present invention, and FIGS. 13 and 14 are waveform diagrams showing output signals and control signals of the driving device of the PDP shown in FIG.

12 to 14, the driving apparatus of the PDP according to the second embodiment of the present invention generates a set down voltage of a falling ramp waveform that is lowered by a predetermined slope, and also has a high potential scan voltage Vsc and a low potential scan. A scan driving circuit 126 for switching the voltage (-Vy) to generate a scan pulse, a bias detecting unit 127 for detecting a set voltage and comparing the set down detection voltage with a predetermined reference voltage, and a scan driving circuit First and second OR gates 122 and 125, an exclusive OR gate 123, and an AND gate element (hereinafter referred to as an "AND" gate) 124 for controlling.

In the scan driving circuit 126, the first switch QH of the driving IC 121 supplies a high potential scan voltage Vsc supplied through the first node n1 to the scan electrode Y. The second switch QL of the driving IC 121 supplies the scan electrode Y with a setdown voltage or a ground voltage supplied via the second node n2. The third switch Q3 is turned on during the address period to supply the high potential scan voltage Vsc to the first node n1. The second switch Q2 is turned on during the setdown period SD to supply a setdown voltage falling to the low potential scan voltage −Vy to the second node n2 at a predetermined falling slope determined by the RC time constant. Done. The first switch Q1 is turned on during the address period to supply the low potential scan voltage -Vy to the second node n2. The fourth switch Q4 is turned on during the address period to open a current path between the first node n1 and the second node n2 to insulate between the first node n1 and the second node n2. It plays a role.

The bias detector 127 includes a zener diode ZD connected between the second node n2 and the low potential scan voltage source (-Vy), the first and second voltage divider resistors R1 and R2, and the common voltage source Vcc. And third and fourth voltage divider resistors R3 and R4 connected between the low potential scan voltage source -Vy and a comparator 128 connected to the third and fourth nodes n3 and n4.

The first and second voltage divider resistors R1 and R2 divide the voltage on the second node n2 with a predetermined voltage divider resistance ratio and supply the divided voltage Vd to the inverting terminal of the comparator 44. The third and fourth voltage divider resistors R3 and R4 divide the common voltage Vcc by a predetermined voltage divider resistance ratio to generate a reference voltage Vr, and convert the reference voltage Vr into the non-inverting terminal of the comparator 44. To feed. The reference voltage Vr is set to a voltage such that the setdown voltage does not fall below the preset setdown lower limit voltage -Vyb in FIGS. 3 and 14.

The comparator 128 generates a low logic output signal when the setdown detection voltage Vd input to the inverting terminal is greater than the reference voltage Vr (Vd> Vr), and the setdown detection voltage Vd input to the inverting terminal. When the voltage is equal to or less than the reference voltage Vr (Vd? Vr), a high logic output signal is generated.

The timing controller (not shown) turns on the first and third switches Q1 and Q3 and turns off the fourth switch Q4 in response to the high logic output signal of the comparator 128.

The AND gate 124 performs an AND operation on the first reference control signal Cref_1 and the output signal Co of the comparator 128. The output signal of the AND gate 124 changes to high logic when both the first reference control signal Cref_1 and the output signal Co of the comparator 128 are high logic, and otherwise remains low logic. . As shown in FIGS. 13 and 14, the first reference control signal Cref_1 maintains high logic from the start of the setdown period SD to the point t2 at which the setdown voltage is forcibly dropped, while keeping the low logic for other periods. The period from the start of the set down period SD to the time t2 is indicated. The high logic output signal Co of the comparator 128 can be seen in FIGS. 13 and 14, in which the setdown voltage is lowered below the setdown lower limit voltage (-Vyb) according to the slope of the falling ramp waveform (Ramp-down). Since the viewpoint changes, the starting time points td and td 'vary. When the slope of the ramp ramp down becomes high in a high temperature environment, as shown in FIG. 13, the starting time td of the high logic output signal Co of the comparator 128 is mostly a period between a time t2 and a time t3. Will appear on the screen. In this case, the output signal of the AND gate 124 is almost kept low logic. On the other hand, when the slope of the falling ramp waveform (rampdown) increases as in the normal temperature environment, as shown in FIG. 14, the starting point td 'of the high logic output signal Co of the comparator 128 is mostly between the time point t1 and t2. Appears in the period of. In this case, the output signal of the AND gate 124 is a period in which both of the first reference control signal Cref_1 and the output signal Co of the comparator 128 maintain high logic, that is, the setdown voltage is the setdown lower limit voltage (-Vyb). The high logic is maintained during the period between the time ≤ t) and the time t2, and low logic otherwise.

The exclusive OR gate 123 performs an exclusive AND operation on the second reference control signal Cref_2 and the output signal Co of the comparator 128. The output signal of the exclusive OR gate 123 is changed to high logic when the output signal of the second reference control signal Cref_2 and the logic value of the output signal Co of the comparator 128 are opposed to each other. Keep the low logic at The second reference control signal Cref_2 maintains the high logic from the time point t2 to the time point t3 at which the address starts, as shown in FIGS. 13 and 14, while the second reference control signal Cref_2 maintains the low logic for other time periods. Will be indicated.

The first and second reference control signals Cref_1 and Cref_2 are generated by a control signal generation circuit (not shown).

The first OR gate 122 performs an OR operation on the output signal of the AND gate 124 and the output signal of the exclusive OR gate 123. The output signal of the first OR gate 122 is changed to high logic when any one of the output signal of the AND gate 124 and the output signal of the exclusive OR gate 123 is high logic. Keep it. The high logic output signal of the exclusive OR gate 123 occurs at time t2 in a high temperature environment and occurs at time td 'between time t1 and time t2 in a normal temperature environment. For this reason, the first OR gate 122 turns on the first switch Q1 at time t2 when the slope of the ramp ramp down becomes small in a high temperature environment as shown in FIG. 13, and as shown in FIG. 14. When the slope of the ramp ramp down becomes normal in a normal temperature environment, the first switch Q1 is turned on between a time t1 and a time t2. As a result, the PDP according to the present invention always optimizes the address operating conditions because the setdown voltage is brought to a desired voltage level before the address is started regardless of the change in ambient temperature.

Meanwhile, the second OR gate 125 performs an OR operation on the first control signal Cad and the output signal of the AND gate 124. The output signal of the second OR gate 125 changes to high logic when either one of the first control signal Cad and the output signal of the AND gate 124 is high logic, and maintains low logic for other periods. . In the high temperature environment, the output signal of the AND gate 124 remains low in most cases, so the output signal of the second OR gate 125 in the high temperature environment is high when the first control signal Cad is high logic. Turns into logic As described above, the first control signal Cadd indicates an address period from the time t3 to the time when the address ends. Accordingly, the output signal of the second OR gate 125 is changed to high logic at the time t3 at which the address period is started in the high temperature environment, thereby turning on the third switch Q3. On the other hand, in the normal temperature environment, the output signal of the AND gate 124 changes to a high logic at a time point td 'between a time point t1 and a time point t2, so that the output signal of the second OR gate 125 is earlier than the high temperature environment ( td ') is changed to a high logic to turn on the third switch Q3.

Therefore, after the third switch Q3 is turned on at the time t2 in the high temperature environment, the third switch Q3 is turned on at the time t3. On the other hand, in the normal temperature environment, the first and third switches Q1 and Q3 simultaneously turn-on at a time when the setdown voltage becomes lower than or equal to the setdown lower limit voltage (-Vyb), that is, at any time td 'between the time points t1 and t2. Is on.

As described above, the method and apparatus for driving a PDP according to the present invention forcibly lowers the setdown voltage to the desired voltage level before the address is started unless the setdown voltage is lowered to the desired voltage level until the start of the address. Accordingly, the method and apparatus for driving a PDP according to the present invention can prevent mis-discharge in a high temperature environment by setting an optimal address operating condition before the set-down voltage starts addressing regardless of temperature change.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

Initializing full screen cells using the setdown voltage; And forcibly changing a voltage level of the set down voltage before an address period for selecting a cell is started. The method of claim 1, Forcibly changing the voltage level of the set down voltage, And the set down voltage level is forcibly lowered to a predetermined voltage level before the address period starts. The method of claim 1, And the set down voltage is drastically lowered at a specific time point before the address period begins. The method of claim 1, And the set down voltage is gradually lowered during a period between a specific time point before the address period begins and the start time of the address period. The method of claim 1, And said set-down voltage decreases step by step during a period between a specific time point before the address period starts and the start time of said address period. The method of claim 1, Forcibly changing the voltage level of the set down voltage, Generating a first control signal indicative of the address period; Generating a second control signal indicative of a period from a specific time point before the address period to a start time of the address period; Generating a setdown control signal by performing an OR operation on the first and second control signals; And in response to the set down control signal, lowering the set down voltage to a predetermined voltage level at the specific time point. The method of claim 6, And supplying a high potential voltage of a scan pulse in response to the first control signal. The method of claim 1, Forcibly changing the voltage level of the set down voltage, Generating a first control signal indicative of the address period; Generating a second control signal indicative of a period from a time when the setdown voltage is supplied to a specific time point before the address period; Generating a third control signal indicative of a period from the specific time point to the start time of the address period; Generating a fourth control signal indicating a time point at which the setdown voltage is lowered below a predetermined voltage level; Performing an AND operation on the second control signal and the fourth control signal; Performing an exclusive OR operation on the third control signal and the fourth control signal; Generating a setdown control signal by performing an OR operation on the AND product and the exclusive OR operation value; And lowering the setdown voltage to a predetermined voltage level in response to the setdown control signal. The method of claim 8, And supplying a high potential voltage of a scan pulse in response to the AND operation value. A set down voltage generator for generating a set down voltage; And a set down controller for forcibly changing the voltage level of the set down voltage before an address period for selecting a cell is started. The method of claim 10, And the set down controller forcibly lowers the set down voltage level to a predetermined voltage level before the address period starts. The method of claim 10, The set down control unit, A control signal generator for generating a first control signal indicative of the address period and a second control signal indicative of a period from a specific point before the address period to a start point of the address period; An OR gate configured to OR the first and second control signals to generate a set down control signal; And a switch element for lowering the set down voltage to a predetermined voltage level at the specific time point in response to the set down control signal. The method of claim 12, And a switch element for supplying a high potential voltage of a scan pulse in response to the first control signal. The method of claim 10, The set down control unit, The first control signal indicative of the address period and the second control signal indicative of the period from the time point at which the set-down voltage is supplied to the specified time point before the address period and from the specified time point to the start time of the address period time period. A control signal generator for generating a third control signal indicating a period; A bias detector which indicates a time point at which the setdown voltage is lowered below a predetermined voltage level; An AND gate for performing an AND operation on the second control signal and the fourth control signal; An exclusive OR gate configured to perform an exclusive OR operation on the third control signal and the fourth control signal; An OR gate generating a set down control signal by performing an OR operation on the output signal of the AND gate and the output signal of the exclusive OR gate; And a switch element for lowering the set down voltage to a predetermined voltage level in response to the set down control signal. The method of claim 14, And a switch element for supplying a high potential voltage of a scan pulse in response to an output signal of the AND gate.