KR20030079454A - Apparatus and method for Ingress control of packet switch system - Google Patents

Abstract

PURPOSE: An input control device and method in a packet switch system is provided to increase the usability of a network system and improve the performance of a high-speed packet switch system, without the necessity of increasing internal operation speed, by fairly switching packets according to the priority order. CONSTITUTION: An input control device and method in a packet switch system is composed of the first demultiplexer(4200), the first and second control parts(4210,4220), the first and second multiplexers(4270a,4270b), a port selection control part(4280), and the third multiplexer(4290). The first demultiplexer(4200) divides inputted packets into unicast packets and multicast or broadcast packets and outputs the divided packets to the first and second control parts(4210,4220). The first control part(4210) consists of the second demultiplexer(4231a) and the first and second storage parts(4240a,4240b). The second demultiplexer(4231a) separates the unicast packets inputted from the first demultiplexer(4200) into real-time traffics and non-real time traffics. The first and second storage parts(4240a,4240b) classify the real-time and non-real time traffics outputted from the second demultiplexer(4231a) by output ports and outputs them selectively. The second control part(4220) is composed of a selector(4232), the third demultiplexer(4231b), the third and fourth storage parts(4250a,4250b), and the fifth and sixth storage parts(4260a,4260b). The first multiplexer(4270a), connected to the first storage part(4240a) and the fifth storage part(4260a), selects the real-time traffics outputted from the first storage part(4240a) and the fifth storage part(4260a). The second multiplexer(4270b), connected to the second storage part(4240b) and the sixth storage part(4260b), selects the non-real time traffics outputted from the second storage part(4240b) and the sixth storage part(4260b). The third multiplexer(4290) selects one between the real-time packet outputted from the first multiplexer(4270a) and the non-real time packet outputted from the second multiplexer(4270b) and transfers it to a switch fabric. The port selection control part(4280) executes communication for the port arbitration of a crossbar scheduler in the switch fabric.

Description

Input control device and method of packet switch system {Apparatus and method for Ingress control of packet switch system}

The present invention relates to a packet switch, and more particularly, to an input control apparatus and method of a packet switch system.

The packet switch system is classified into input buffered switch, output buffered switch, internal buffered switch, and input / output buffered switch according to the location of memory among various parameters that determine its performance.

FIG. 1 is a block diagram of a general input / output buffered packet switch system 100 and illustrates a configuration of an input / output buffering switch system using FIFOs (First In, First Out). Referring to FIG. 1, the input / output buffering switch 100 includes a plurality of input buffers 101-10n, a switch fabric 130, a plurality of output buffers 121-12n, and a control processor 140.

Packets stored in the input buffer 101-10n make a switching request to the switch fabric 130 when the input buffer 101-10n operates as a FIFO. However, the input / output buffering switch 100 performs switching on only one port for the switching request. Accordingly, HOL blocking occurs on packets having the same destination on different input ports.

The output buffers 121-12n shown in FIG. 1 are used to prevent output blocking in which packets are concentrated on one output port. An ideal output buffered switch accepts up to N packets in one time slot in an N × N switch system. To do this, the bandwidth of the bus must be NV (where V is the input link speed) and the output buffer's access speed must be (N + 1) V. To this end, the internal speed of the output buffer type switch should be increased by N times, but there is a limit that is used only for low speed switches because the switch capacity that can be implemented is limited.

The above input buffer type switch 100 exhibits a poor yield of 58.6% by HOL blocking. However, since the input buffer type switch 100 can operate at the same speed as the external link when the HOL blocking phenomenon is reduced, high speed operation is possible. Therefore, methods for reducing the HOL blocking phenomenon have been sought.

2 is a block diagram of a window-type input buffering switch system 200 according to the prior art. The input buffering switch system 200 shown in FIG. 2 shows a system configuration when the window method is used as a method for reducing the HOL blocking phenomenon.

Referring to FIG. 2, a window type input buffering switch system 200 includes a plurality of input buffers 201-20n having a window having a predetermined size (for example, 2), and a crossbar scheduler 232. It is composed of a provided N × N switch fabric (230).

Input buffers 201-20n having a window size of 2 make a switching request to the switch fabric 230. When the HOL blocking occurs in the first window of the input buffers 201-20n, the switch system 200 requests a switching to the destination of the second window, thereby increasing the yield to 70.4%.

As such, the window-type input buffering switch system 200 has an improved yield compared to the input buffer type switch 100. However, since the HOL blocking phenomenon still exists in the switch system 200, the yield is limited.

The characteristics of such input buffered packet switch systems 100, 200 are described by IEEE JOURNAL ONSELECTED AREAS IN COMMUNICATIONS, VOL.6., Dec. 1988 by MICHAEL G. HLUCHYJ and MARK J. KAROL. NO. 9, "Queueing in High-performance Packet Switching."

3 is a block diagram of a virtual output queue type input buffering switch system 300 according to the prior art. In the virtual output queue method, as many buffers as the number of output ports are configured in one port in order to remove HOL blocking. Since the input buffering switch system 300 of this type has respective buffers corresponding to the respective output ports, HOL blocking can be eliminated. For details, see December 2000, Minkenberg, c. And in an article in "A combined input and output queued packet switched system based on PRIZMA switch on a chip technology" by Engbersen, T. in IEEE Communications Magazine, Volume: 38, page (s): 70-77. .

Referring to FIG. 3, the input buffering switch system 300 of the virtual output queue type includes a plurality of input ports 301- 30n each having a plurality of virtual output buffers 311-31n and 321-32n. , N × N switch fabric 330 is provided with a crossbar scheduler (332).

When the virtual output buffers 311-31n and 321-32n provided in the input ports 301-30n make a switch request to the switch fabric 330, the scheduler 332 provided in the switch fabric 330 may be plural. One of the two requests is randomly selected to generate a grant signal. The virtual output queues 311-31n and 321-32n corresponding to each output port switch to the corresponding output port in response to the grant signal.

As an example of such packet scheduling, in the patent filed by the present applicant (Korean Patent Application No. 10-1999-0040405), "Packet Scheduling Apparatus and Method in Packet Switch System", a packet in which HOL blocking has not occurred is used. After switching by priority, by switching the packets for which HOL blocking has occurred by priority, all input packets can be switched evenly. However, this method improves the performance of the switch, but packet starvation may occur because the destination output for the packet in the register that stores the HOL blocking packet must always be checked and looped back. It has a disadvantage.

And, in the patent filed by the present applicant (Korean Patent Application No. 10-1998-0054207), "Input control apparatus and method of the asynchronous transfer mode switch network", the speed is received through a receiving test cell generated via a switch. Control the congestion of the switch network. However, according to the present invention, when the multicast packet or the broadcast packet is input, the speed control part receiving the test cell of the switch network adjusts the switch network input rate, so that the switching processing speed is somewhat lowered in the high speed switch system. .

In addition, Korean Patent Application No. 10-1999-0049167, "Packet Buffer Control Device in Packet Switch Using Common Bus," determines whether to continuously receive packet data according to the state in which the data is actually stored in the packet buffer. Do it. According to the present invention, the switching phenomenon is less likely to occur due to the packet control operation, the switching operation can be performed smoothly, the method using a common bus has a disadvantage that is difficult to apply to the high-speed switch system have.

Conventional input control methods performed in the packet switch system as described above, the yield of the packet is limited by the HOL blocking generated in the input buffer, fairness to the input ports, multicasting scheme and broadcasting It is difficult to support the method.

Moreover, with the continued trend of increasing line speeds, gigabit switches have emerged as the mainstream, and current trends are emerging for switch structures where 10 Gigabit ports are supported for uplinks, requiring hundreds of gigabytes of packet switching. If the above-described switching system and method are applied to the high speed switch system, the fairness of the input ports is not guaranteed and the performance of the system is degraded.

The technical problem to be achieved by the present invention is to provide a packet switch system that can improve the utilization of the network system, and can significantly improve the performance of the high-speed packet switch system without increasing the internal operating speed by switching packets in order of priority. To provide an input control device and method.

1 is a block diagram of an input / output buffering switch system using a FIFO according to the prior art.

2 is a block diagram of a window-type input buffering switch system according to the prior art.

3 is a block diagram of a virtual output queue type input buffering switch system according to the prior art.

4 is a block diagram of a packet switch system according to a preferred embodiment of the present invention.

5 is a diagram illustrating an IP address system format.

6 illustrates an IEEE 802.3 MAC frame format.

7 is a diagram illustrating a format of an internal message header of an input control apparatus according to an exemplary embodiment of the present invention.

8 is a block diagram of an input control apparatus of a packet switch system according to a preferred embodiment of the present invention.

9 is a flowchart illustrating an operation performed in the input control apparatus according to the present invention.

<Description of Symbols for Main Parts of Drawings>

400: packet switch system 401-40n, 441-44n: line card

410: packet switch unit 421-42n: input control device

431: switch fabric432: crossbar scheduler

4200: first demultiplexer 4210: first control unit

4220: second control unit 4231 a: second demultiplexer

4231b: third demultiplexer4232: selector

425 (n + 1): storage control unit 4280: port selection control unit

4240a, 4240b: first and second storage

4241-424n, 4251-425n, 4261-426n: Cue

4250a, 4250b: third and fourth reservoirs

4260a, 4260b: fifth and sixth reservoirs

4270a, 4270b, 4290: first to third multiplexers

In order to achieve the above object, the input control apparatus of the packet switch system according to the present invention comprises: a first demultiplexer for separating input packets into unicast packets and multicast / broadcast packets; A first control unit which separates the unicast packet transmitted through the first demultiplexer into real-time traffic and non-real-time traffic, and stores the separated traffic in a buffer for each destination output port; The multicast / broadcast packet transmitted through the first demultiplexer is divided into the real time traffic and the non-real time traffic, and the separated traffic is stored for each output port or corresponding group output port according to the characteristics of the packet. A second control unit for selecting; A first multiplexer for selecting and outputting any one of the real-time traffic output from the first control unit and the second control unit in response to a port selection control signal; A second multiplexer for selecting and outputting any one of the non-real-time traffic output from the first control unit and the second control unit in response to the port selection control signal; A third multiplexer for transmitting any one of the packets output from the first multiplexer and the second multiplexer to a switch fabric in response to the port selection control signal; And a port selection controller configured to communicate with a crossbar scheduler provided in the switch fabric to generate the port selection control signal.

In order to achieve the above object, the input control method of the packet switch system according to the present invention comprises the steps of: (a) separating the input packets into unicast packets and multicast / broadcast packets; (b) separating the unicast packet separated in step (a) into real-time traffic and non-real-time traffic, and storing the separated traffic in a buffer for each destination output port and selecting the separated unicast packet; (c) separating the multicast / broadcast packet separated in the step (a) into the real-time traffic and the non-real-time traffic, and outputting the packet for every output port or corresponding group according to the characteristics of the packet. Copying and storing each port for selection; (d) in response to the port control signal, selecting any one of real-time traffic output in steps (b) and (c); (e) selecting any one of the non-real-time traffic output in steps (b) and (c) in response to the port control signal; And (f) in response to the port control signal, delivering the packet output through steps (d) and (e) to a switch fabric.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a block diagram of a packet switch system according to a preferred embodiment of the present invention. Referring to FIG. 4, the packet switch system according to the present invention includes a packet switch unit 410 and a plurality of line cards 401-40n and 441-44n connected to input / output terminals of the packet switch unit 410. do. The packet switch unit 410 includes an N × N switch fabric 431 provided with a crossbar scheduler 432, and a plurality of input control devices 421-42n.

The input control devices 421-42n provided in the packet switch unit 410 analyze the headers of the packets input from the line card 401-40n, classify the packets, and control the input packets by priority. Perform a switching operation.

The switch fabric 431 configures a crossbar, which is a nonblocking switch without memory, in a three-layer cloth network. The switch fabric 431 is fully interconnected between the unit switches, so that there are several switching paths between the input and output ends of the switch network.

As shown in FIG. 4, the input control apparatuses 421-42n according to the present invention are connected to an input terminal of a fabric switch 431 configured as a cloth network, and the input packets are unicast packets, multicast packets, The performance of switching system is improved by classifying into broadcast packets and performing fair scheduling. As a result, the operation speed of the switch is equal to the speed of the input line, which is advantageous in speeding up the link.

5 is a diagram illustrating an IP address system format. Referring to FIG. 5, class A 500, class B 510, and class C 520 represent unicast packets, and class D 530 represents a multicast group. The address format 530 of class D 530 used in the IP multicast group is recognized by setting the value "1110" in the most significant bit of the first byte of the IP address. The 28 bits following the value are used as an ID specifying a particular multicast group of data to be transmitted. The multicast address range in the D class 530 used at this time is from 224.0.0.0 to 239.255.255.255.

In response to this IP multicast addressing scheme in the IP layer, the IEEE 802 MAC layer is provided with a multicast address called a hardware multicast address.

FIG. 6 illustrates an IEEE 802.3 MAC frame format supporting multicast address mapping. Referring to Fig. 6, in order to specify a multicast address in the IEEE 802 MAC frame format, the upper three bytes of the destination address start with a hexadecimal number such as "01-00-5E", as shown by reference numeral 621, and "01." -00-5E-00-00-00 "through" 01-00-5E-FF-FF-FF "are allocated for the IP multicast group. In the broadcast address, the upper three bytes of the destination address 620 are set to a "FF-FF-FF" value as indicated by reference numeral 622.

The Ethernet packet supports the transmission of multicast packets by allowing the multicast address to a six-byte destination address 620 indicating a destination, as shown in FIG. Therefore, the IP group address can be converted into an Ethernet multicast address. That is, the lower 23 bits of the IP group address of the D class 530 are converted to be located in the lower 23 bits of the Ethernet multicast address "01-00-5E-00-00-00" when expressed in hexadecimal. The upper three bytes 621 of the destination address 620 having a value of "01-00-5E" indicate that the frame is multicast, and the immediately following bit always has a value of "0". Thus, only the remaining 23 bits are used for the multicast address. That is, since the IP of the multicast group is 28 bits long, one-to-one mapping is impossible, and only 23 lower bits (LSBs) of the IP multicast group of the D class 530 have the destination address 620 of the MAC frame. Is mapped to. At this time, the remaining five high order bits of the D class 530 are ignored, and 32 (2 ⁵ = 32) different multicast groups are mapped equally to the multicast addresses of the Ethernet or FDDI destination addresses. This means that the Ethernet layer does not act as a complete filter to classify unicast packets and multicast packets. Therefore, the IP layer must decide whether to receive or discard data that has passed through the data link layer.

7 is a diagram illustrating a format of an internal message header of an input control apparatus according to an exemplary embodiment of the present invention. Referring to FIG. 7, the internal message header format of the input control apparatus according to the present invention includes a total of 1 byte.

The line card 401-40n shown in Fig. 4 checks the header of the destination address 620 or the IP address system of the MAC frame, and determines whether the input packet is a unicast packet, a multicast packet or a broadcast packet. After determining whether the input packet is a packet that requires real time or a non-real time packet irrelevant to the transmission time, the packet is transmitted to the input controllers 421-42n by attaching one byte of its own header.

The upper two bits 710 of the inner message header shown in FIG. 7 inform the input controller 421-42n whether the corresponding packet is a unicast packet or a multicast or broadcast packet. . The next 1 bit 720 is a bit for indicating a priority, and informs the input control apparatuses 421-42n whether the packet is a real time packet or a non real time packet. The lower 5 bits 730 are used by the first and second storage units 4240a and 4240b to recognize the corresponding output port number when the unicast packet is transmitted, and check the internal message header of the upper 2 bits 710. As a result, when the input packet is determined to be a multicast packet, the storage control unit 425 (n + 1) provided in the third and fourth storage units 4250a and 4250b receives information from the multicast forwarding table and outputs the corresponding information. Copies packets to port groups.

8 is a block diagram of an input control apparatus of a packet switch system according to a preferred embodiment of the present invention. Referring to FIG. 8, an input control apparatus of a packet switch system according to the present invention includes a first demultiplexer 4200, first and second controllers 4210 and 4220, first and second multiplexers 4270a and 4270b, A port selection controller 4280 and a third multiplexer 4290.

The first demultiplexer 4200 divides an input packet into a unicast packet and a multicast or broadcast packet, and outputs the divided packet to the first control unit 4210 and the second control unit 4220.

The first control unit 4210 includes a second demultiplexer 4231a and first and second storage units 4240a and 4240b. The second demultiplexer 4231a separates the unicast packet input from the first demultiplexer 4200 into real-time traffic and non-real-time traffic. The first and second storage units 4240a and 4240b classify and store the real-time and non-real-time traffic output from the second demultiplexer 4231a for each output port, and select and output the traffic.

The second control unit 4220 includes a selector 4322, a third demultiplexer 4231b, third and fourth storage units 4250a and 4250b, and fifth and sixth storage units 4260a and 4260b. The selector 4232 performs a role of recognizing whether a packet input from the first demultiplexer 4200 is a multicast packet or a broadcast packet. The third demultiplexer 4231b separates the multicast and broadcast packets recognized by the selector 4232 into real-time traffic and non-real-time traffic, respectively. The third and fourth storage units 4250a and 4250b copy and output the traffic output through the third demultiplexer 4231b into a buffer corresponding to the corresponding group or each output port according to packet characteristics. The fifth and sixth storage units 4260a and 4260b store packets transmitted through the third and fourth storage units 4250a and 4250b in buffers corresponding to the respective output ports, and select and output the packets. .

The first multiplexer 4270a is connected to the first storage unit 4240a of the first control unit 4210 and the fifth storage unit 4260a of the second control unit 4220, so that the first storage unit 4240a and the first multiplexer 4270a are connected. 5 Select the real-time traffic output from the storage 4260a.

The second multiplexer 4270b is connected to the second storage unit 4240b of the first control unit 4210 and the sixth storage unit 4260b of the second control unit 4220, and thus, the second storage unit 4240b and the second storage unit 4270b are connected to each other. 6 Select the non-real time traffic output from the storage unit 4260b.

The third multiplexer 4290 selects one of a real time packet output from the first multiplexer 4270a and a non-real time packet output from the second multiplexer 4270b and transmits the selected packet to the switch fabric 431.

The port selection controller 4280 performs communication for port arbitration with the crossbar scheduler 432 provided in the switch fabric 431, and the first and third storage units 4240a / b and 4260a / b. The operation of the first and second multiplexers 4270a / b and the third multiplexer 4290 is controlled.

Referring to the operation of the input control device having such a configuration in detail as follows.

First, the first demultiplexer 4200 separates an input packet into a unicast packet and a multicast or broadcast packet. The unicast packet is output to the first controller 4210, and the multicast packet and broadcast packet are output to the second controller 4220, respectively.

The first control unit 4210 separates the unicast packet input from the first demultiplexer 4200 into a real time packet and a non-real time packet through the second demultiplexer 4231a, and divides the separated packet into the first storage unit 4240a. And the second storage unit 4240b. The first and second storage units 4240a and 4240b read the destination address of the packet, store the packet in a plurality of buffers 4241-424n each representing a corresponding destination, and then select a predetermined packet. Output The real time packets output from the first storage unit 4240a are input to the first multiplexer 4270a, and the non-real time packets output from the second storage unit 4240b are respectively input to the second multiplexer 4270b.

The second controller 4220 recognizes whether the packets input from the first demultiplexer 4200 are multicast packets or broadcast packets through the selector 4232. The third demultiplexer 4231b divides the packet output from the selector 4232 into a real time packet and a non real time packet. The real time packet separated by the third demultiplexer 4231b is input to the first multiplexer 4270a via the third storage unit 4250a and the fifth storage unit 4260a. The non-real time packet separated by the third demultiplexer 4231b is input to the second multiplexer 4270b via the fourth storage unit 4250b and the sixth storage unit 4260b. The third and fourth storage units 4250a and 4250b are notified by the selector 4232 whether the input packet is a multicast packet or a broadcast packet. When the input packet is a multicast packet, the third and fourth storage units 4250a and 4250b search the multicast forwarding table and copy the input packet to all output ports or corresponding group output ports. After the copied packet is stored in the plurality of buffers 4251-425n corresponding to each output destination, the packets are transferred to the fifth and sixth storage units 4260a and 4260b. The fifth and sixth storage units 4260a and 4260b store the input packets in a plurality of buffers 441-426n indicating respective destinations. The fifth storage unit 4260a selects the real-time packets stored in the buffers 4426-426n and outputs them to the first multiplexer 4270a. The sixth storage unit 4260b stores the buffers 4426-426n. The stored non-real time packets are selected and output to the second multiplexer 4270b, respectively.

The first multiplexer 4270a receives the first multiplexer 4240a of the first control unit 4210 and the fifth storage unit 4260a of the second control unit 4220 in response to a control signal of the port selection control unit 4280. The input real-time traffic is output to the third multiplexer 4290.

The second multiplexer 4270b receives the second multiplexer 4240b of the first control unit 4210 and the sixth storage unit 4260b of the second control unit 4220 in response to a control signal of the port selection control unit 4280. The input non-real time traffic is output to the third multiplexer 4290.

The third multiplexer 4290 transmits the input packets to the packet switch system according to the priority of the real time packet and the non-real time packet in response to the control signal of the port selection controller 4280.

The port selection controller 4280 controls the first and second storage units 4240a and 4240b, the fifth and sixth storage units 4260a and 4260b, and the first to third multiplexers 4270a, 4270b and 4290. In order to do so, communication with the crossbar scheduler 432 for port arbitration is performed. As a result, the port selection controller 4280 prevents the performance of the packet switch system from deteriorating due to internal blocking that occurs when a request for each destination is selected at the same time.

The port selection controller 4280 performs preferential scheduling on the queues in which the real time packets 4240a and 4260a are stored, and then performs a non-real time operation so that a request for each destination can be serviced within a specific time. Allow fair scheduling to be performed on packets 4240b and 4260b. For example, if the queue 4241 having the destination 1 of the first storage unit 4240a is selected to be scheduled by the port selection controller 4280, the port selection controller 4280 that represents the destination 1 queue 4241. ) Increases by 1, and the pointers of the queues 4242-424n and 4261-426n having the remaining destinations do not change. Here, the queues 4242-424n and 4261-426n having destinations whose pointer values do not change are controlled according to the corresponding pointer values of the port selection controller 4280 for the next scheduling, thereby providing fair scheduling.

9 is a flowchart illustrating an operation performed in the input control apparatus according to the present invention. Referring to FIG. 9, the input control apparatus according to the present invention first receives a packet input from a line card (step 4201) and determines whether the input packet is a unicast packet (step 4202).

If it is determined in step 4202 that the input packet is a unicast packet, it is determined whether the unicast packet is a real time packet or a non-real time packet (step 4211).

As a result of the determination in step 4211, if the unicast packet is a real time packet, the packet is allocated to the virtual output queue (VOQ) (step 4223), and the scheduling is first performed on the virtual output queue (VOQ) in which the allocated real time packet is stored. (Step 4224). Then, the packet is selected (step 4225) and output (step 4262).

As a result of the determination in step 4211, if the unicast packet is a non-real time packet, the packet is allocated to the virtual output queue (VOQ) (step 4212), and the fairness is given to the virtual output queues (VOQ) in which the allocated non-real time packet is stored. The scheduling is performed (step 4229). Then, the packet is selected (step 4225) and output (step 4262).

As a result of the determination in step 4202, if the input packet is a multicast packet or a broadcast packet, it is determined whether the packet is a real time packet or a non-real time packet (step 4221).

As a result of the determination in step 4221, if the packet is a real-time packet, multicast and broadcast packets are copied to each output port (step 4202), and the packet is allocated to a virtual output queue (VOQ) (step 4223). ). Subsequently, scheduling is performed on the virtual output queue VOQ in which the real-time packets are stored (step 4224). Then, the packet is selected (step 4225) and output (step 4226).

As a result of the determination in step 4221, if the packet is a non-real time packet, the multicast and broadcast packets are copied to each output port (step 4227), and the packet is allocated to a virtual output queue (VOQ) (4228). step). Subsequently, fair scheduling is performed on non-real time packets so that the corresponding destination request can be serviced within a specific time (step 4229). Then, the packet is selected (step 4225) and output (step 4262).

As described above, the input control apparatus and method of the packet switch system according to the present invention performs switching by classifying the input packets into unicast packets and multicast or broadcast packets at the front of the switch fabric. In addition, real-time traffic and non-real-time traffic are scheduled by priority, thereby providing fair switching.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

As described above, according to the input control apparatus and method of the packet switch system according to the present invention, since the input packets are classified into unicast packets and multicast or broadcast packets and switched, the utilization of the network is increased.

In addition, since switching requests are scheduled by prioritizing real-time traffic and non-real-time traffic, the efficiency and performance of the switch system are increased without increasing the internal operation speed.

Claims (9)

A first demultiplexer for separating input packets into unicast packets and multicast / broadcast packets; A first control unit which separates the unicast packet transmitted through the first demultiplexer into real-time traffic and non-real-time traffic, and stores the separated traffic in a buffer for each destination output port; The multicast / broadcast packet transmitted through the first demultiplexer is divided into the real time traffic and the non-real time traffic, and the separated traffic is stored for each output port or corresponding group output port according to the characteristics of the packet. A second control unit for selecting; A first multiplexer for selecting and outputting any one of the real-time traffic output from the first control unit and the second control unit in response to a port selection control signal; A second multiplexer for selecting and outputting any one of the non-real-time traffic output from the first control unit and the second control unit in response to the port selection control signal; A third multiplexer for transmitting any one of the packets output from the first multiplexer and the second multiplexer to a switch fabric in response to the port selection control signal; And And a port selection controller configured to communicate with a crossbar scheduler provided in the switch fabric to generate the port selection control signal. The method of claim 1, wherein the first control unit A second demultiplexer for separating the unicast packet input from the first demultiplexer into the real time traffic and the non-real time traffic; And And first storage means for classifying and storing the real-time and the non-real-time traffic output through the second demultiplexer for each output port, and selecting and outputting the same. The method of claim 2, The first storage means includes a plurality of virtual output queues that make a switching request to the switch fabric and perform switching to a corresponding output port in response to an accept signal generated from the switch fabric by the request. An input controller of a packet switch system. The method of claim 1, wherein the second control unit A selector for recognizing whether the input packet is a multicast packet or a broadcast packet; A third demultiplexer for separating the multicast / broadcast packet recognized by the selector into the real time traffic and the non real time traffic; In response to the result recognized by the selector, a second storage for copying and storing the real time / non-real time packet output through the third demultiplexer for every output port or corresponding group output port according to the characteristics of the packet. Way; And And a third storage means for separating and storing the packet outputted through the second storage means into respective destination output buffers, and selecting the packet. The method of claim 4, wherein the second storage means, A plurality of buffers for storing the packet in every output port or corresponding group output port according to characteristics of the packet; And And a storage control unit for receiving the information from the multicast forwarding table and copying the packet for each corresponding output port, when the packet is a multicast packet. The method of claim 4, wherein The third storage means may include a plurality of virtual output queues that make a switching request to the switch fabric and perform switching to a corresponding output port in response to an accept signal generated from the switch fabric by the request. An input controller of a packet switch system. The method of claim 1, The input packets include an inner message header indicating an attribute of the packet, The header may include first attribute information indicating information on whether the packet is the unicast packet or the multicast / broadcast packet, and information indicating whether the packet is a real time packet or a non-real time packet. 2 attribute information, and an output port number to be used for the transmission of the packet. In the input control method of the packet switch system: (a) separating the input packets into unicast packets and multicast / broadcast packets; (b) separating the unicast packet separated in the step (a) into real-time traffic and non-real-time traffic, and storing the separated traffic in a buffer for each destination output port and selecting the separated unicast packet; (c) separating the multicast / broadcast packet separated in the step (a) into the real-time traffic and the non-real-time traffic, and outputting the packet for every output port or corresponding group according to the characteristics of the packet. Copying and storing each port for selection; (d) in response to the port control signal, selecting any one of real-time traffic output in steps (b) and (c); (e) selecting any one of the non-real-time traffic output in steps (b) and (c) in response to the port control signal; And and (f) in response to the port control signal, forwarding the packet outputted through steps (d) and (e) to a switch fabric. A computer-readable recording medium having recorded thereon a program for executing the method of claim 8 on a computer.