KR100372231B1 - Quasi-Shared Buffering Type Multicast ATM Switch Module Architecture with Two QoS Classes - Google Patents

Abstract

The present invention relates to a semi-shared buffered multicast ATM switch architecture supporting two quality of service (QoS) classes.

In the present invention, after dividing the buffer into two groups to store cells belonging to the real-time traffic class in one buffer group, and storing cells belonging to the non-real-time traffic class in the other buffer group, the switching order of the two class cells is changed. By adjusting appropriately, it is easy to support the QoS required by each class, and selector to distinguish whether the input cell is real-time traffic or non-real-time traffic in the switch element is separated according to the class of the input cell and stored in two buffer groups By managing and switching the two traffic having the opposite traffic characteristics, a structure for improving the performance of the switch by reducing latency for real-time traffic and cell loss for non-real-time traffic is proposed.

Description

Quasi-Shared Buffering Type Multicast ATM Switch Module Architecture with Two QoS Classes

The present invention relates to a quasi-shared buffer multicast ATM switch structure supporting two QoS (quality of service) classes. More specifically, the present invention relates to a buffer group for processing real-time traffic and a buffer group for processing non-real-time traffic. The present invention relates to a structure of a semi-shared buffered multicast ATM switch element having two different buffer groups and managing and switching these heterogeneous traffic separately to satisfy the QoS required by each traffic.

The conventional semi-shared buffered multicast ATM switch device does not distinguish between classes of all input cells, and switches and outputs cells using only priority information determined by the order in which the cells are input into the switch elements.

1 is a block diagram of a conventional N × M multicast ATM switch element of a quasi-shared buffer method.

The conventional quasi-shared buffer multicast switch device includes a distributor 1 for distributing input cells, L buffers 2 for storing input cells, and control information for determining the output order of cells stored in the buffer. A control register (3) for storing control signals for controlling the switch, an arbiter (4) for making a control signal using the control information, and an output switch (5) for sending cells stored in a buffer to a corresponding output port. do.

The output switch uses the control signal produced by the arbiter to switch the cell to the corresponding output ports.

The operation of each part in the conventional quasi-shared buffer type switch element is as follows. The input cells are stored in the L buffers 2 in a round-robin fashion by the distributor 1. At this time, the cells are distributed to each buffer 2 one by one from the cell of the upper input port. Cells sent to each buffer 2 are stored in the buffer 2 until output. The time stamp value and destination output port information, which are control information of HOL (head of line) cells of each buffer, are sent to the control register 3, and using the information, the arbiter 4 generates a control signal and generates a control register ( Send back to 3). The output switch 5 is controlled using the control signal of the control register 3 so that each cell is switched to the destination output port.

The detailed operation of the conventional switch element is described in detail by dividing the input process and the output process of the cell.

2 illustrates an input process of a cell.

The divider 11 causes the input cells from the input port to be sequentially stored one by one from the buffer # 0 to the buffer # L-1, and then distributes the cells in the form of round robin so that they are stored one by one from the buffer # 0 again. In FIG. 2, the numbers indicated in the buffer 12 indicate the storage order of the cells. In order to do this, the distributor distributes the cells of the input port so that cells are allocated one by one from the buffer 12 indicated by the buffer pointer 13. That is, when k cells are input to the N input ports, the cells are sequentially sent to the k buffers starting from the buffer indicated by the buffer pointer 13. In the example of FIG. 2, three input cells are distributed to be stored in three buffers, from buffer # L-2 to buffer # 0 indicated by the buffer pointer.

3 illustrates a cell output process in a conventional switch device.

Since the priorities of the HOL cells of each buffer 21 are compared and the output ports are allocated from the HOL cells having the highest priority, the cells are output using only the priority and destination output port information. "(Priority, Output Port) Information" of each HOL cell indicates the priority and destination output port of the cell. In the case of using the time stamp as an example of the priority information, the lower the value, the higher the priority. In other words, the buffer sharing effect is obtained by first outputting the cell that has been inputted to the switch element first. The destination output port information is represented by M bits of binary numbers, and bits corresponding to the ports to be output among the M output ports are indicated by 1. At this time, the LSB (least significant bit) means output port # 0, and the MSB (most significant bit) means output port # M-1. This destination output port information is made before the cell is input to the switch element, so it is only used within the switch element.

In the example of FIG. 3, since the HOL cell C2 of the buffer # 2 has the highest priority and the destination output port information is 0 ... 100, the output port # 2 is assigned to the cell C2 first, and the next highest priority has the highest priority. Since the destination output port information of cell CL-1 is 0 ... 110, cell CL-1 is sent to output port 1. Since cell C2 preempts output port # 2 prior to cell CL-1, cell CL-1 sends the cell only to output port # 1 and cell transfer to output port # 2 attempts at the next cell time.

However, the conventional switch device structure does not distinguish between real-time traffic and non-real-time traffic, which makes it difficult to satisfy QoS required differently for each traffic.

While real-time traffic, predominantly voice or video, is sensitive to latency and insensitive to cell loss, non-real-time traffic, predominantly data, is insensitive to latency but sensitive to cell loss. Thus, it is difficult to satisfy QoS individually without dividing traffic requiring different QoS into two different classes. Therefore, in order to satisfy QoS of real-time traffic and non-real-time traffic, a mechanism for separating and managing two traffics is required.

The present invention is to solve the problems of the prior art, the object of the present invention is to place two classes to support two QoS in the switch element QoS required by each class by properly adjusting the switching order of the two class cells To provide a semi-shared buffer multicast ATM switch device structure that is configured to facilitate the support.

As a technical idea for achieving the object of the present invention, by dividing the buffer into two groups, one buffer group stores cells belonging to the real-time traffic class, the other buffer group stores the cells belonging to the non-real-time traffic class Afterwards, the switching order of the two class cells is properly adjusted to facilitate the QoS required by each class, and a selector is provided in the switch element to distinguish whether the input cell is real-time traffic or non-real-time traffic. It stores the data in two buffer groups, manages them, and switches them accordingly.It separates and manages two traffic with opposite traffic characteristics, reducing latency for real-time traffic and reducing cell loss for non-real-time traffic. To improve performance A structure for this is presented.

1 is a block diagram of a conventional quasi-shared buffer type N × M ATM switch element.

2 is a conceptual diagram of an input process of a conventional switch element.

3 is a conceptual diagram illustrating an output process of a conventional switch device.

4 is a block diagram of a quasi-shared buffer N × M ATM switch element supporting two classes of the present invention.

5 is a conceptual diagram of the output process and the control register configuration in the switch element of the present invention.

6 is an explanatory diagram of the arbiter operation in the switch element of the present invention.

<Description of the symbols for the main parts of the drawings>

31-a, 31-b: distributor

32-a, 41-a, 51-a: buffer for real-time traffic

32-b, 41-b, 51-b: buffer for non-real-time traffic

33, 43: control register

34, 44: Arbitrator

35, 45, 56: output switch

Hereinafter will be described in detail with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention.

4 is a configuration diagram of an N × M switch element according to the embodiment of the present invention.

In the switch element proposed in the embodiment of the present invention, the number of input ports is N, the number of output groups is M, and r output ports are configured per output group.

The present invention provides N selectors 36 for classifying input cells into real-time traffic and non-real-time traffic according to class, and a divider 31-a for real-time traffic that evenly distributes the cells from the selectors to buffers in each buffer group. Distributor 31-b for non-real-time traffic, LR real-time traffic buffers 32-a and 32-b for non-real-time traffic where input cells are stored, and output order of cells stored in the buffer L (L = LR + LN) control registers 33 for storing control information and control signals for controlling an output switch, an arbiter 34 for generating a control signal using the control information, and for non-real-time traffic. It is characterized in that it consists of a counter 37 for generating a threshold signal by counting the occupied cells of the buffers to the arbiter 34 and an output switch 35 for sending the cells stored in the buffer to the corresponding output group. The size BN of the non-real time traffic buffers 32-b is larger than the size BR of the real time traffic buffers 32-a.

The operation of each part in the switch element of the present invention is as follows.

The input cells are divided into real-time traffic cells and non-real-time traffic cells by the selector 36, so that the real-time traffic cells are sent to the real-time traffic distributor 31-a, and the non-real-time traffic cells are distributed to the non-real-time traffic distributor 31-. b) is sent. The two distributors 31-a and 31-b perform the same operation as the distributor 1 in the existing switch material for the corresponding class cells which are classified and input through the selector 36. That is, the input cells sent to the splitter 31-a for real-time traffic are in round robin format. Cells stored in two buffers 32-a and sent to the divider 31-b for non-real-time traffic are in round robin format. Are stored in two buffers 32-b. At this time, the cells are distributed to the buffers 32-a and 32-b one by one from the cell of the upper input port of each group. Cells sent to buffers 32-a and 32-b are stored in buffers 32-a and 32-b until output. Control information of the HOL cells of the buffer is sent to and stored in the control register 33. In addition, the counter 37 checks whether the number of occupied cells of the non-real-time traffic buffer exceeds a predetermined threshold, generates a threshold signal, and sends the threshold signal to the control register 33. The control information of the control register 33 is sent to the arbiter 34, which uses the information to generate a control signal to control the output switch 35 and send it back to the control register. Finally, the output switch 35 is controlled using the control signal of the control register 33 to switch each cell to the corresponding output port of the destination output group.

5 is for explaining the output algorithm of the cell in detail.

5A illustrates a case where the number of output groups is M and the number of output ports r per output group is two.

The signals sent from the control register 43 to the arbiter 44 to produce an output control signal for controlling the output switch 45 are as follows. the threshold signal generated by the counter 47 for the i th buffer , Class signal read from HOL cells of each buffer (41-a, 41-b) , Timestamp information And output group bitmap information to be. 5B shows the configuration of the control register, four types of control information , , , It is configured to be stored in order.

The arbiter 44 determines the output priority of the cell by using the first three pieces of information (threshold signal, class signal, and time stamp information), and output group bitmap information according to the determined priority. Create an output control signal using. The output group bitmap information is represented by a binary number of M bits. A bit corresponding to a group to be output among M output groups is indicated by 1, and a LSB (least significant bit) means output group # 0. For example, when the output group bitmap information is (0, 1, ..., 1, 0, 1), the destination output group is # 0, # 2, # M-2. This destination output group information is generated before the cell is input to the switch element, so it is only used within the switch element.

An algorithm for determining the priority of the HOL cells stored in the buffer by using the “threshold signal, class signal, and time stamp” information is as follows. The buffer HOL cells may be classified into three groups according to the threshold signal and the class signal as follows.

Iii) HOL cell of the buffer for non-real-time traffic whose threshold signal value is "0" above threshold H

Ii) HOL cell of buffer for real-time traffic

Iii) HOL cell of buffer for non-real-time traffic with threshold value "1" not exceeding threshold H

Among the three groups, the highest priority is given to the HOL cell of the non-real time traffic buffer exceeding the threshold, and the next highest priority is given to the HOL cell of the real time traffic buffer. In other words, if the real-time traffic is given a higher priority to satisfy the latency requirements of the real-time traffic, but there are too many cells stored in the non-real-time traffic buffer, there is a risk of cell loss. HOL cells in the corresponding non-real-time buffers are given higher priority than real-time traffic to prevent cell loss. Among the cells belonging to the same priority group, a cell having a small time stamp value, that is, an old cell input to the switch system has a high priority.

Hereinafter, the operation of the counter, the control register and the arbiter will be described in detail with reference to the example of FIG. 5.

In the embodiment of FIG. 5A, the counters 47 assigned to the non-real-time traffic buffers 41-b one by one count the threshold number of cells in the buffer. Create The counter 47 keeps a threshold signal until the length of the buffer exceeds a predetermined threshold H. Is set to "1" and sent to the control register 43, the buffer length being the threshold value. Threshold signal is set to "0" only if it is greater than 0, sent to control register 43, and the threshold number of cells in this buffer is set. When it comes down to below, the threshold signal is returned. Set to "1". In the case of a buffer for real-time traffic, there is no counter, and the threshold signal is always sent to the control register 43, which is set to "1".

Class signal From the HOL cell of each buffer Also read from the corresponding HOL cell and stored in the control register 43. It is read and sent to the control register 43. In the embodiment of FIG. 5A, the real-time traffic class has a class signal of "0" and the non-real-time traffic is set to "1". Since all cells stored in the real-time traffic buffer are real-time traffic, it can be seen that the class signals of the HOL cells of the real-time traffic buffer are all "0". Similarly, it can be seen that the class signals are all "1" in the case of HOL cells of the non-real-time traffic buffer. Time stamp Also read from the corresponding HOL cell and stored in the control register 43.

Threshold signal in the control register as shown in b of FIG. Class signal , Timestamp information In the order of, the smaller the value of the (threshold signal, class signal, time stamp) information, the higher the priority, and the higher the value, the lower the priority. Therefore, it is possible to determine the priority of all HOL cells only by comparing the magnitude of "(threshold signal, class signal, time stamp) information".

In the embodiment of FIG. 5A in which signal values are assigned in the above manner, buffer # HOL cell Output group information with the highest priority Is 00 ... 101, so the cell Assign output groups # 0 and # 2 first. Next highest priority cell Since the destination output group information of is 01 ... 001, Assign output groups # 0 and # M-2 to the. Cell In the case of, the destination output group information is 10 ... 001, but cells can only be output to output group # M-1, and cells cannot be output to output group # 0. The reason is that all output ports of output group # 0 are higher priority cells. Wow It is already occupied by. Cell Output to output group # 0 will be tried at the next cell time.

6 illustrates an example of an arbitrator implementation and illustrates the cell output process.

The switch output section is composed of a control information register (CIR) 52, a control signal register (CSR) 53, a distributed arbiter and an output switch 56. The distributed arbiter includes a priority selection part (PSP) 54 and an output port selection part (OSP) 55 that align cells using priority information.

The operation of the switch output is as follows.

The control information "(threshold signal, class signal, time stamp) information" and destination output group information are read from the HOL cells of each of the buffers 51-a and 51-b into the control information register 52. The " (threshold signal, class signal, time stamp) information " is used to determine the priority, and the destination output group information indicates the destination of each cell.

The control information is first sent to the priority determining unit 54 of the distributed arbiter. The control information passing through the two cross-point elements is sent to the latch of the output port determination section 55, in which "(threshold signal, class signal, time stamp) information" is arranged in descending order. The output port determination unit 55 generates a control signal by allocating output ports according to priorities using destination output group information stored in each latch. Up to r different cells can be output to one output group, and each cell must be output to a different output port. That is, in the example of figure, two cells can be output to output group # 0. At this time, one cell should be output to the first output port of output group # 0 and the other one to the second output port. The destination output group information is a bitmap information signal of M bits, which means that each bit corresponds to one output group, and when a bit value is "1", a cell should be output to the corresponding output group. The control signal is a bitmap control signal of Mr bits, which means that each bit corresponds to one output port, and when the bit value is "1", the control signal is output to the corresponding output port. The cross point elements of the priority determining unit 54 determine the priority using only "(threshold signal, class signal, time stamp) information" in the control information. Each cross-point element has "(critical signal, class signal, time stamp) information" of the upper port, In the left port "(Critical signal, Class signal, Time stamp)" When larger, it is in a cross state, and the left control information having a small (high priority) information (threshold signal, class signal, time stamp) information is sent to the right. Contrary end If it is smaller than or equal to the bar state, the higher priority control information is sent to the right. Each cross point device maintains the determined state until it receives a control signal from the output port determining section.

In the embodiment of Fig. 5A, since r = 2, there are two output ports per one output group. Control signal When a specific HOL cell is output to the jth output port of the kth output group, the bit Is set to "1". The generated control signal is sent back to the priority determining section 54 and sent to the control signal register (CSR) 53 via the cross points. At this time, since each of the cross point elements of the priority determining unit 54 maintains the state, it is possible to send a control signal to the corresponding control signal register 53 without further processing. The output switch 56 is controlled by using the information of the control signal register 53, and the HOL cells of the buffers 51-a and 51-b are loaded on the data bus and switched to the output port. A simple structure that sends cells to the output port only for an output port with a control signal of 1, and the cross point of the output switch can be made simply by a logic gate.

During the switching, the control signal stored in the control signal register 53 Output group occupancy information using Create If output group occupancy information ( , ..., , ), The control signal The calculation method of output group occupancy information from is as follows.

From the stomach Means a Boolean OR operation. Then, the destination output group information stored in the control information register 52 Output group occupancy information from Subtracts the destination output group information of the next cell time of each buffer (51-a, 51-b) HOL cell. Calculate That is, 'remaining destination output group information' that HOL cell should transmit at the next cell time. Is = - Obtain it in the same way. After switching If 0 means that all the HOL cells are output to the desired output group, the HOL cells are replaced and the control information of the new HOL cell is read into the control information register 52. If is not 0, there is still an output group to output HOL cell. Only the new data is written to the destination output group information portion of the control information register 52.

Referring to the above-described output switch operation by way of example, when the control information of the HOL cells of Figure 6 is shown in Table 1, the HOL cell of the i-th buffer 6 is arranged in the order of the smallest time stamp values through the priority determiner 54 and stored in the latch of the output port determiner as shown in FIG. 6. The first latch of the output port determination section 55 has the highest priority. Cell Output Group Information sign Is stored.

Cell ( ) ( , , ) ： (1, 0, 13): (1, 0, 15) 01 ... 001 ： 00 ... 010 0001 ... 000010 ： 0000 ... 000100 01 ... 001 ： 00 ... 010 ： (1, 1, 8): (0, 1, 7) 10 ... 001 ： 00 ... 101 0100 ... 000000 ： 0000 ... 010001 10 ... 000 ： 00 ... 101

Since the first latch is assigned the output port first, it is possible to output to the first port of all destination groups, and as a result, the control signal. Is Becomes The second latch has the next priority As cell output group information sign Is stored, so the control signal Is Becomes That is, a signal is generated to output to the second output port of output group # 0 and the first output port of output group # M-2. Cell In this case, the destination output group information. Is, and output group # 0 is already a cell Wow Preempted by and can only output to output group # M-1 Is Becomes In this way, the output ports are selected for all L latches and a control signal is generated.

The control signal produced by the output port determiner is sent to the control signal register 53 via the reverse path of the priority determiner. In the case of FIFO # 0, the control signal Therefore, the HOL cell of FIFO # 0 on the second output port of output group # 0 and the first output port of output group # M-2. Outputs In this case, end Becomes therefore, Is newly stored in the destination output group information field of the CIR.

As described above, the present invention improves the performance of the switch by classifying input cells into real-time traffic and non-real-time traffic, thereby reducing latency for real-time traffic and reducing cell loss for non-real-time traffic. can do. By separating buffers into two groups to separate and process real-time traffic and non-real-time traffic, there is an effect that can support desired QoS by minimizing interaction of two traffics.

In addition, by using a high-speed arbitrator and control logic that prioritizes real-time traffic and non-real-time traffic, there is an effect of ensuring the fairness between real-time and non-real-time traffic while operating at high speed.

Claims (4)

A switch element comprising a first buffer group storing a cell belonging to a real time traffic class and a second buffer group storing a cell belonging to a non-real time traffic class; Selection means for discriminating whether a cell input into the switch element is real-time traffic or non-real-time traffic; A real time traffic distributor for distributing cells input from the selection means to respective buffers in the first buffer group and a non-real time traffic distributor for distributing the buffers in the second buffer group; A counter for counting the number of cells occupied by each of the buffers in the second buffer group and generating a threshold signal; A control register for storing control information from cells and a counter stored in the buffers and for storing a control signal of an output switch; A priority information determiner (PSP) for arranging control information of HOL cells stored in the buffers of the first buffer group by using the control information register and the threshold signal, class signal, and time stamp information provided by the control information register. An output port selection part (OSP) for determining a corresponding output port of a destination output group by using a priority selection part and control information arranged by the priority determining part to generate a control signal; It is composed of a control signal register for storing the control signal generated by the output port determination unit, by using the control information of the control register to determine the priority of the cells of the buffer to create a control signal, and send it back to the control register With the arbitrator, An output switch for switching cells of the buffer to a destination output group using a control signal of the control register; Quasi-shared buffered multicast ATM switch element architecture supporting two QoS classes, including: delete delete delete