KR20030074866A - Device for Controlling a Line Defect of a Switching for Automatic Power Distribution - Google Patents

Abstract

PURPOSE: An apparatus for controlling a line fault of a switch for automatic power distribution is provided to improve the reliability of data transmission by connecting a fault decision DSP(Digital Signal Processor) unit to a main DSP unit by means of a DMA(Direct Memory Access) method. CONSTITUTION: An apparatus includes a voltage/current input portion(21), a fault decision DSP unit(22), a CPU(Central Processing Unit)(24), a main DSP unit(23), a communication unit(25), and a display unit(26). The voltage/current input portion(21) converts a voltage/current signal of a load terminal to a constant voltage. The fault decision DSP unit(22) decides a fault from an output signal of the voltage/current input portion(21) and calculates power elements. The CPU(24) is used for performing a function of an address decoder. The main DSP unit(23) is connected to the fault decision DSP unit(22) by means of a DMA method. The communication unit(25) performs a data communication process between the main DSP unit(23) and an upper system. The display unit(26) displays output data of the CPU(24).

Description

Device for Controlling a Line Defect of a Switching for Automatic Power Distribution}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal device of an automated switchgear of a distribution system, and more particularly, to distribution automation for improving reliability and speed in communication between digital signal processors for measuring, calculating, and displaying voltage and current of a distribution system. It relates to a line failure control device of the switchgear.

In general, the terminal device of the automatic switchgear of the distribution system detects the voltage and current of the load stage, determines the fault point (FI: Fault Indicator) by calculating the fault current in real time, and transmits it to the upper system. When the execution command by the automation algorithm (Algorithm) is transmitted to the terminal device, the terminal device performs a role of separating / returning the failure section by its own communication and failure determination algorithm. At this time, accurate and reliable data (data) due to disturbances (noise and surge components) between the processor (Processor) that collects and operates measurement data and the processor that processes the data and delivers them to the upper level. Exchange is the most important and high speed data transmission is required.

1 is a block diagram showing a track failure control apparatus according to the prior art.

As shown in FIG. 1, the conventional line failure control apparatus includes a voltage / current input unit 11, a failure point determination CPU unit 12, a main CPU unit 13, and a dual port RAM. The unit 14, the communication unit 15, and the display unit 16 are configured.

The voltage / current input unit 11 is composed of a CT / PT (Current Transformer / Power Transformer) circuit, receives the voltage / current signal of the load stage, filters the second small signal, and converts the signal into a constant voltage. The failure point determination CPU unit 12 receives the voltage from the voltage / current input unit 11 and transmits measurement data Data for determining the failure point to the main CPU unit 13.

Since the measurement data is a current and the failure point is determined by the magnitude of the current, the measurement data of the current must be correctly transmitted to the main CPU unit 13, and serial communication in the bit transmission unit is required for the transmission of the measurement data. (Using the Tx and Rx signals). In other words, the failure point determination CPU section 12 and the main CPU section 13 exchange data using serial communication.

The communication unit 15 transmits the collected data to the main CUP unit 13 to a higher system. At this time, the transmission medium between the communication unit 15 and the main CPU unit 13 is the dual port RAM unit 14.

The dual port RAM unit 14 includes a command and data (Data) in a promised area so that the main CPU unit 13 and the communication unit 15 exchange addresses A0 to A10 and data D0 to D7. After writing), it causes interrupts (INTa, INTb) to the other side so that the other side can recognize the interrupt and read data. In this case, the address and data are transmitted through an address bus and a data bus, respectively.

That is, when the communication unit 15 receives the data at the upper level and generates an interrupt INTa, the main CPU unit 13 reads the command and data from the designated area of the dual port RAM unit 14 to analyze and process the data.

Similarly, when the communication unit 15 recognizes the interrupt INTb of the main CPU unit 13, it analyzes and processes the transmitted command and data.

Therefore, even if data exists in the dual port RAM unit 14, if the other party's interrupts are not recognized by each other, the other party cannot take the data and can read / write the data of the dual port RAM unit 14 only when the other party needs it. have.

Therefore, the line failure control apparatus of the switchgear for distribution automation according to the prior art as described above has the following problems.

First, since data transfer between the main CPU unit and the communication unit is performed through a data bus that operates unconditionally against external factors, external factors (surge or noise, etc.) are not caused by normal processor operation. ), Interruption may cause a malfunction in which data is transmitted in a direction not required by each other, thereby reducing reliability.

Second, it sends and receives each other's data only by interrupt, and transmits data through serial communication of bit transmission method, so the operation speed is slow.

The present invention has been made in order to solve the above problems, and an object thereof is to provide a line failure control apparatus for an automatic switchgear for distribution automation for improving the reliability of data transmission and realizing high-speed data transmission.

1 is a block diagram showing a track failure control apparatus according to the prior art

Figure 2 is a block diagram showing a track failure control apparatus according to an embodiment of the present invention

3 is a conceptual diagram of direct memory access (DMA) communication data transmission between a digital signal processor (DSP) unit and a main DSP unit in the present invention.

Explanation of symbols for the main parts of drawings

21: voltage / current input unit 22: failure point determination DSP unit

23: main DSP unit 24: CPU unit

25: communication unit 26: display unit

The line fault control apparatus of the distribution automation switchgear according to the present invention for achieving the above object is a voltage / current input unit for receiving a voltage / current signal from the load end to convert a constant voltage and outputs, and the voltage / current input unit Fault point determination which receives the output signal and determines the fault current and calculates and transmits the fault current in real time by various power elements, a central processing unit which functions as an address decoder, and receives the command to determine the fault point. A main digital signal processing unit communicating with a digital signal processing unit by a direct memory access (DMA) method, a communication unit for performing data communication between the main digital signal processing unit and an upper system by an enable signal from the central processing unit, and the central processing unit Various calculation result value, signal input status and output data And a display unit for receiving and displaying data.

In more detail, a dedicated data bus may be provided between the failure point determination digital signal processor and the main digital signal processor separately from the central processor.

In more detail, the failure point determination further comprises a communication driver between the digital signal processor and the main digital signal processor.

Hereinafter, with reference to the accompanying drawings illustrating a line failure control device of the switchgear automation switch according to the present invention.

2 is a block diagram showing a track failure control apparatus according to an embodiment of the present invention.

As shown in FIG. 2, the line failure control apparatus of an automatic switchgear for distribution automation according to the present invention receives a voltage / current signal from a load end and converts the voltage / current into a constant voltage and outputs the voltage / current input unit 21. The fault point determination DSP unit 22, which is a dedicated digital signal processor (DSP) that receives the output signal of the current / current input unit 21 and determines the fault current, and calculates and transmits the current in real time with various power elements. CPU unit 24 serving as a decoder and a main DSP unit 23 for exchanging data through the DMA (Direct Memory Access) communication with the failure point determination DSP unit 22 by receiving a command from the CPU unit 24. ), A communication unit 25 for communicating with the host system, and a display unit 26 for receiving and displaying various calculation result values, signal input states, and output data from the CPU unit 24 via a data bus.

The DMA communication between the failure point determination DSP unit 22 and the main DSP unit 23 reads data from the memory area of the failure point determination DSP unit 22 and writes the data to the data area of the main DSP unit 23. Since it is performed via a dedicated address bus and data bus independently of the CPU unit 24, parallel processing is possible without degrading the operation of the CPU unit 24 without adding a separate circuit.

The communication speed between the failure point determination DSP unit 22 and the main DSP unit 23 is about 5 Mbps, and communication is performed by six signals. The basic processing is as follows.

In general, the start address and the arrival address are automatically increased or decreased each time a word transmission is performed in the DMA communication, and data transmission is performed synchronously using internal and external interrupts. After the DMA channel register is initialized, the DMA operation is initiated and the word is transmitted.

The first step is to initialize the DMA channel register.

That is, the start address and destination address registers of the DMA channel are initialized with the arrival address value and the transfer address value, respectively. The number of words to transfer the transfer counter register (TCR) of the DMA channel is suitable for taking a read and write operation by interrupting the channel control register (CCR). Initialize each to a mode.

Subsequently, the channel control register CCR determines the start bit for starting the DMA operation and starts the DMA operation.

The DMA channel then reads one word from the address indicated by the start address register and stores it in a temporary register inside the DMA channel.

At this time, the start address register value does not increase, decrease or change according to the contents stored in the increment bit (INCSRC bit) of the start address of the channel control register (CCR) or the decrease bit (DECSRC bit) of the arrival address.

Then, if one word stored in the temporary register is written to the address indicated by the destination address register, the value of the counter register (CR) is decreased, and the value of the destination address is the start address of the channel control register. It does not increase, decrease or change depending on the increase bit of or the decrease bit of the arrival address.

If the block transfer is completed and the count register CR is zero, the DMA channel sets the transfer counter interrupt flag of the counter control register CCR to one.

When the DMA block transfer is completed, the transfer counter (TC) of the DMA controller has a value of 1 or 0 so that the transfer counter (TC) is initialized to one of a transmission stop mode or an operation execution mode or an interrupt mode with a transmission counter interrupt (TCINT) of 1. Will be.

The function of the communication unit 25 is performed only by the input / output read / write R / W by the unit signal UNIT of the CPU unit 24 and not by the address or the data bus method.

Therefore, when receiving or transmitting data from the upper level, the communication unit 25 receives the chip select signal (C / S) between the CPU unit 24 and the main DSP 23 unit to perform an operation and allows transmission and reception. If so, the function starts only according to the operation sequence of the DMA communication described above. When the corresponding data of the departure address is finished, the flag value of the DMA controller becomes one of three modes (TC = 1, 0, TCINT = 1). There cannot be an error.

Since the communication speed is transmitted in word block unit rather than the existing serial communication bit transmission method, many data can be transmitted and received at several Mbps.

3 is a conceptual diagram of direct memory access (DMA) communication data transmission between the fault point determination DSP (Digital Signal Processor) unit 22 and the main DSP unit 23 according to the present invention. When the data D is sent to the DSP unit 23, the clock CLK is generated, and the flag signal FS is in one cycle of the clock CLK, while the data D is in the clock CLK. It is made for 2 cycles.

According to another embodiment of the present invention, the fault point determination DSP unit 22 and the main DSP unit 23 are easily connected to an analog / digital converter, a serial port, and the like. It is also possible to add a communication driver in between.

The line fault control apparatus of the automatic switching device for wiring automation according to the present invention has the following effects.

First, since a disturbance error can be prevented by communicating with a direct memory access (DMA) method between the failure point determination DSP unit and the main DSP unit, the reliability of data transmission can be improved.

Second, since the communication between the failure point determination DSP unit and the main DSP unit is performed through a dedicated address bus and data bus separately from the CPU unit, parallel processing with the CPU unit is possible without degrading the operation function of the CPU unit. It is possible to improve the data transfer rate without adding circuits.

Third, the data transmission speed can be improved because the failure point determination DSP unit and the main DSP unit do not transmit bit by bit, but block by bit.

Fourth, since a communication driver is added between the failure point determination DSP unit and the main DSP unit, long distance communication is possible.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (3)

A voltage / current input unit which receives a voltage / current signal from a load end and converts the voltage / current signal into a constant voltage; A failure point determination digital signal processing unit which receives an output signal of the voltage / current input unit to determine a fault current and calculates and transmits the fault current in real time with various power elements; A central processing unit serving as an address decoder, A main digital signal processing unit which receives a command of the central processing unit and communicates with the failure point determination digital signal processing unit by direct memory access (DMA); A communication unit for performing data communication between the main digital signal processing unit and an upper system by an enable signal from the central processing unit; And a display unit configured to receive and display various operation result values, signal input states, and output data from the central processing unit. The apparatus of claim 1, wherein a dedicated data bus is provided between the fault determination digital signal processor and the main digital signal processor separately from the central processor. The apparatus of claim 1, further comprising a communication driver between the failure point determination digital signal processor and the main digital signal processor.