CN116827714A - Communication anti-interference method, device, system and storage medium - Google Patents
Communication anti-interference method, device, system and storage medium Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40019—Details regarding a bus master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Abstract
The invention discloses a communication anti-interference method, a device, a system and a storage medium. The method comprises the following steps: the communication host sends a communication preparation signal to the communication slave; resetting a preset register after the communication slave detects a communication preparation signal, and controlling a level signal on a preset communication state signal line to be a reset completion signal after the reset is completed, wherein the preset register is a register associated with communication between the communication master and the communication slave; after detecting the reset completion signal, the communication host sends a control instruction to the communication slave. According to the technical scheme provided by the embodiment of the invention, after the communication host sends the communication preparation signal to the communication slave, the communication slave can reset the preset register in time, so that interference data generated by electromagnetic interference in the preset register is deleted in time, and the communication host is informed of the completion of the reset through the preset communication state signal line, so that the problem of communication abnormality caused by electromagnetic interference on a communication line is solved, and the communication reliability is improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a system, and a storage medium for anti-interference communications.
Background
With the increasing scale of integrated circuits, the functionality of ICs (Integrated Circuit, integrated circuits) is increasing. The ICs are tested before they are shipped from the factory, and the core chips used in the test equipment typically include field programmable gate array (Field Programmable Gate Array, FPGA) chips and micro control unit (Microcontroller Unit, MCU) chips.
Currently, communication between FPGA and MCU in the prior art uses standard serial peripheral interface (Serial Peripheral Interface, SPI) communication, which is a high-speed, synchronous communication bus with full duplex and half duplex characteristics.
However, due to the complex electromagnetic environment in the IC test field and the longer service life of the test instrument, the generated electromagnetic interference seriously affects the communication quality of the SPI communication signal line, which often results in abnormal communication and affects the performance and the working efficiency of the test instrument.
Disclosure of Invention
The invention provides a communication anti-interference method, a device, a system and a storage medium, which are used for solving the problem that electromagnetic interference seriously affects communication.
In a first aspect, the present invention provides a communication anti-interference method, including:
the communication host sends a communication preparation signal to the communication slave;
resetting a preset register after the communication slave detects the communication preparation signal, and controlling a level signal on a preset communication state signal line to be a reset completion signal after the reset is completed, wherein the preset register is a register associated with communication between the communication master and the communication slave;
and after the communication host detects the reset completion signal, a control instruction is sent to the communication slave.
Further, according to the anti-interference method for communication provided by the present invention, after the communication slave detects the communication preparation signal, resetting the preset register, and after the resetting is completed, controlling the level signal on the preset communication state signal line to be a reset completion signal, including:
after the communication slave detects the communication preparation signal, the communication slave sends a high-level signal to a preset communication state signal line and resets a preset register;
and after the communication slave determines that the reset of the preset register is completed, switching the high-level signal on the preset communication state signal line into the low-level signal, wherein the low-level signal on the preset communication state signal line belongs to a reset completion signal.
Further, according to the communication anti-interference method provided by the invention, after the communication host sends a control instruction to the communication slave, the communication anti-interference method further comprises the following steps:
after the communication slave machine finishes executing the control instruction and the received cyclic redundancy check code passes the check, the communication slave machine sends a response pulse signal to the communication host machine through the preset communication state signal line, wherein the response pulse signal is used for informing the communication host machine that the control instruction is processed.
Further, according to the communication anti-interference method provided by the present invention, after the communication slave sends a high level signal to a preset communication state signal line and resets a preset register, the method further includes:
if the communication host does not detect the first accumulated time used by the reset completion signal and exceeds a first preset duration, determining that the communication slave fails to reset the preset register, wherein the starting time of the first accumulated time is the time when the communication host detects a high-level signal sent by the communication slave to a preset communication state signal line.
Further, according to the communication anti-interference method provided by the present invention, after the communication slave sends a response pulse signal to the communication master through the preset communication state signal line, the method further includes:
if the communication host does not detect the second accumulated time used by the response pulse signal and exceeds a second preset duration, determining that communication abnormality occurs between the communication host and the communication slave, wherein the timing starting time of the second accumulated time is the time when the communication host sends a control instruction corresponding to the response pulse signal to the communication slave.
Further, according to the communication anti-interference method provided by the invention, the preset register at least comprises a shift register.
Further, according to the communication anti-interference method provided by the invention, the number of the communication slaves which are communicated with the communication master is multiple, and the communication slaves are mutually independent.
In a second aspect, the present invention provides a communication anti-interference device, including a signal sending module and an instruction sending module disposed at a communication host, and a signal control module disposed at a communication slave, where:
the signal sending module is used for sending a communication preparation signal to the communication slave;
the signal control module is used for resetting a preset register after detecting the communication preparation signal, and controlling a level signal on a preset communication state signal line to be a reset completion signal after the reset is completed, wherein the preset register is a register associated with communication between the communication host and the communication slave;
the instruction sending module is used for sending a control instruction to the communication slave machine after detecting the reset completion signal.
In a third aspect, the present invention provides a communication anti-interference system, the system comprising:
a communication host side and a plurality of communication slave sides;
at least one processor; and a memory communicatively coupled to the at least one processor;
wherein the memory stores a computer program executable by the at least one processor to enable the at least one processor to instruct the communication host side to perform content executed by the communication host in the communication antijamming method as set forth in any one of the preceding claims, and to instruct the communication slave side to perform content executed by the communication slave in the communication antijamming method as set forth in any one of the preceding claims.
In a fourth aspect, the present invention provides a computer readable storage medium storing computer instructions for causing a processor to perform the communication anti-interference method of the first aspect.
According to the communication anti-interference scheme provided by the invention, a communication host transmits a communication preparation signal to a communication slave, after the communication slave detects the communication preparation signal, a preset register is reset, and after the reset is completed, a level signal on a preset communication state signal line is controlled to be a reset completion signal, wherein the preset register is a register associated with communication between the communication host and the communication slave, and after the communication host detects the reset completion signal, a control instruction is transmitted to the communication slave. Through adopting above-mentioned technical scheme, after communication host computer is through sending the communication preparation signal to communication slave machine, communication slave machine can in time reset and predetermine the register to in time deleted the interference data that produces because of electromagnetic interference in predetermineeing the register, avoid influencing normal data's receipt, and after the completion of resetting, utilize predetermineeing communication state signal line in time to inform communication host machine, so as to inform communication host machine can send control command to communication slave machine, it has solved the unusual problem of communication that receives electromagnetic interference to bring on the communication line, improve communication reliability.
It should be understood that the description in this section is not intended to identify key or critical features of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a communication anti-interference method according to a first embodiment of the present invention;
fig. 2 is a flowchart of a communication anti-interference method according to a second embodiment of the present invention;
FIG. 3 is a flow chart of anti-interference control for communication between an FPGA and an MCU according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a communication anti-interference device according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of a communication anti-interference system according to a fourth embodiment of the present invention;
fig. 6 is a diagram showing an exemplary configuration of a communication master communicating with a plurality of communication slaves according to a fourth embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. In the description of the present invention, unless otherwise indicated, "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a flowchart of a communication anti-interference method provided in an embodiment of the present invention, where the embodiment is applicable to a communication anti-interference situation, for example, a communication anti-interference situation between an FPGA chip and an MCU chip in an integrated circuit tester, where the method may be performed by a communication anti-interference device, where the communication anti-interference device may be implemented in a form of hardware and/or software, where the communication anti-interference device may be configured in a communication anti-interference system, where the communication anti-interference system includes a communication master side and a plurality of communication slave sides, where the communication master side may execute content executed by a communication master in the communication anti-interference method, and where the communication slave side may execute content executed by a communication slave in the communication anti-interference method.
As shown in fig. 1, the method for anti-interference communication provided in the first embodiment of the present invention specifically includes the following steps:
s101, the communication host transmits a communication preparation signal to the communication slave.
In this embodiment, the communication modes between the communication host (such as FPGA chip) and the communication slave (such as MCU chip) may be multiple communication modes such as SPI communication, bidirectional two-wire synchronous serial bus communication, and CAN communication. Taking SPI communication as an example, a communication signal line between a communication master and a communication slave includes: MISO (Master Iutput Slave Onput), MOSI (Master Output Slave Input), SCK (CMOS clock), CS (Chip Select) and Chip Select) signal lines. The communication preparation signal may be sent to the communication slave via a preset communication signal line, which in this embodiment may be a CS signal line, and the communication preparation signal may be a low level signal, for example, a low level signal may be sent to the CS signal line, which indicates that the communication master is ready to communicate with the communication slave.
S102, after the communication slave detects the communication preparation signal, resetting a preset register, and after the resetting is completed, controlling a level signal on a preset communication state signal line to be a reset completion signal, wherein the preset register is a register associated with communication between the communication master and the communication slave.
In this embodiment, the communication slave, upon detecting the communication ready signal, triggers a high priority interrupt of the communication slave and resets a preset register, such as a register associated with SPI communication. After the reset is completed, the communication slave can control the level signal on the newly-added preset communication state signal line to be a reset completion signal. The preset communication state signal line is a newly added signal line, and the signal line can be used for transmitting state signals of the communication slave machine, such as transmitting reset completion signals and the like, wherein the reset completion signals are used for reminding the communication host machine that the preset register is reset, and the reset completion signals can be low-level signals and the like.
S103, after the communication host detects the reset completion signal, a control instruction is sent to the communication slave.
In this embodiment, after detecting the reset completion signal, the communication master may send a control instruction, data, etc. to the slave via the signal line, for example, send data to the slave via the MOSI signal line. The control instruction comprises a read instruction, a write instruction and the like, the structure of a write instruction frame is shown in a write instruction frame structure table in table 1, the structure of a read instruction frame is shown in a read instruction frame structure table in table 2, and the structure of a read data frame is shown in a read data frame structure table in table 3. Wherein, CRC represents cyclic redundancy check, which is called Cyclic Redundancy Check.
Table 1 write instruction structure table
Table 2 read command frame structure table
Table 3 read data frame Structure table
| 1 st to 4 th byte | Byte 5 |
| Data frame (D) | Data frame (CRC) |
| DATA | CRC |
According to the communication anti-interference method provided by the embodiment of the invention, a communication host sends a communication preparation signal to a communication slave, after the communication slave detects the communication preparation signal, a preset register is reset, and after the reset is completed, a level signal on a preset communication state signal line is controlled to be a reset completion signal, wherein the preset register is a register associated with communication between the communication host and the communication slave, and after the communication host detects the reset completion signal, a control instruction is sent to the communication slave. According to the technical scheme, after the communication host sends the communication preparation signal to the communication slave, the communication slave can reset the preset register in time, the interference data generated by electromagnetic interference in the preset register is deleted in time, normal data receiving is avoided, and after the reset is completed, the communication host is informed in time by using the preset communication state signal line to inform the communication host that the communication host can send the control instruction to the communication slave, so that the problem of communication abnormality caused by electromagnetic interference on a communication line is solved, and the communication reliability is improved.
Example two
Fig. 2 is a flowchart of a communication anti-interference method provided by the second embodiment of the present invention, and the technical solution of the embodiment of the present invention is further optimized based on the above-mentioned alternative technical solutions, and a specific manner of communication anti-interference is provided.
Optionally, after the communication slave detects the communication preparation signal, resetting a preset register, and after the resetting is completed, controlling a level signal on a preset communication state signal line to be a reset completion signal, including: after the communication slave detects the communication preparation signal, the communication slave sends a high-level signal to a preset communication state signal line and resets a preset register; and after the communication slave determines that the reset of the preset register is completed, switching the high-level signal on the preset communication state signal line into the low-level signal, wherein the low-level signal on the preset communication state signal line belongs to a reset completion signal. The setting has the advantages that the communication host can timely determine the state of the preset register by changing the level signal on the preset communication state signal line before and after resetting the preset register, and the accuracy and the integrity of data transmission are ensured.
Optionally, after the communication host sends a control instruction to the communication slave, the method further includes: and after the control instruction is executed by the communication slave machine and the received cyclic redundancy check code passes the check, sending a response pulse signal to the communication host machine through the preset communication state signal line, wherein the response pulse signal is used for informing the communication host machine that the control instruction is processed. The communication slave machine sends a response pulse signal to the communication host machine through the preset communication state signal line, so that the communication host machine can inform that the instruction of the communication host machine is processed, the communication host machine can send the next instruction, and the order of communication is ensured.
Optionally, after the communication slave sends a high level signal to a preset communication state signal line and resets a preset register, the method further includes: if the communication host does not detect the first accumulated time used by the reset completion signal and exceeds a first preset duration, determining that the communication slave fails to reset the preset register, wherein the starting time of the first accumulated time is the time when the communication host detects a high-level signal sent by the communication slave to a preset communication state signal line. The advantage of this arrangement is that by determining the first cumulative timing, the communication master can be enabled to accurately determine whether the reset of the preset register is normal or not and whether the communication slave has a reset failure or not.
As shown in fig. 2, the anti-interference method for communication provided in the second embodiment of the present invention specifically includes the following steps:
s201, the communication host transmits a communication preparation signal to the communication slave.
For example, if the communication host is an FPGA chip, hereinafter referred to as FPGA, the communication slave is an MCU chip, hereinafter referred to as MCU, and the communication mode is SPI communication. Fig. 3 is a flow chart of anti-interference control of communication between an FPGA and an MCU. As shown in fig. 3, if the low level signal is a communication preparation signal, the FPGA may first send a low level signal, i.e., a "CS pull-down level", to the CS (signal line).
S202, after the communication slave detects the communication preparation signal, a high-level signal is sent to a preset communication state signal line, and a preset register is reset.
For example, if the preset communication state signal line is a BUSY signal line, as shown in fig. 3, the MCU triggers an interrupt response after detecting a low level signal (communication ready signal) on the CS signal line, and sends a high level signal to the BUSY signal line, and resets the preset register.
Optionally, the preset register at least includes a shift register.
Specifically, the preset register may be a shift register related to communication.
And S203, if the communication host does not detect the first accumulated time used by the reset completion signal and exceeds the first preset time length, determining that the communication slave fails to reset the preset register.
The timing starting time of the first accumulated timing is the time when the communication host detects a high-level signal sent by the communication slave to a preset communication state signal line.
For example, the FPGA starts timing from the moment when the MCU detects the high level signal sent by the MCU to the preset communication state signal line, and stops timing when the low level signal (the reset completion signal) is received, as shown in fig. 3, if the first cumulative timing exceeds a first preset duration, such as 2 microseconds, it may determine that the wait time is overtime or the MCU fails to reset the SPI peripheral (i.e. the preset register), where the first preset duration may be set according to the actual needs, such as 3 microseconds, etc., and is not limited herein.
S204, after the communication slave machine determines that the reset of the preset register is completed, the high-level signal on the signal line of the preset communication state is switched to the low-level signal.
Wherein, the low level signal on the preset communication state signal line belongs to the reset completion signal.
For example, as shown in fig. 3, after the MCU determines that the reset of the SPI-related preset register (SPI peripheral) is completed, the MCU switches the high level signal on the BUSY signal line to the low level signal, and it should be noted that, in fig. 3, the SPI peripheral refers to the preset register, which may be a shift register or the like.
S205, after detecting the reset completion signal, the communication host sends a control instruction to the communication slave.
For example, as shown in fig. 3, after detecting the low level signal on the BUSY signal line, the FPGA outputs a rising edge, i.e., an effective signal, on the SCK signal line, and outputs a control word (i.e., a control command) and a data frame address, if the control command is a write command, the FPGA will send a data frame and a CRC check frame to the MCU, and after the sending is completed, send a high level signal to the SCK signal line and the CS signal line, and if the control command is a read command, the FPGA will keep outputting a high level signal on the SCK signal line, send a CRC check frame, and after the sending is completed, send a high level signal to the SCK signal line and the CS signal line.
S206, after the communication slave machine executes the control instruction and the received cyclic redundancy check code passes the check, the communication slave machine sends a response pulse signal to the communication host machine through a preset communication state signal line.
The response pulse signal is used for informing the communication host that the control instruction is processed.
For example, as shown in fig. 3, after the MCU executes the control command and the received crc passes the check, the MCU sends a response pulse signal to the FPGA through the BUSY signal line.
Optionally, after the communication slave sends a response pulse signal to the communication host through the preset communication state signal line, the method further includes: if the communication host does not detect the second accumulated time used by the response pulse signal and exceeds a second preset duration, determining that communication abnormality occurs between the communication host and the communication slave, wherein the timing starting time of the second accumulated time is the time when the communication host sends a control instruction corresponding to the response pulse signal to the communication slave. The advantage of this is that by determining the second cumulative timing, the communication master can be guaranteed to discover the communication failure of the communication slave in time.
For example, as shown in fig. 3, the second preset duration is preset to be 30 microseconds, the FPGA sends a control instruction to the MCU to start timing, and the FPGA receives the response pulse signal to stop timing, and if the second cumulative timing exceeds the second preset duration, that is, is greater than 30 microseconds, it may be determined that the waiting time is overtime or the CRC check fails, that is, the communication abnormality occurs.
Optionally, as shown in fig. 3, if the control instruction sent by the FPGA is a read instruction, after the MCU sends a response pulse signal to the FPGA through the BUSY signal line, the FPGA continues to send a high-level signal to the SCK signal line and sends a low-level signal to the CS signal line, receives a read-back data frame and a read-back CRC check frame sent by the MCU, and after receiving, sends a high-level signal to the CS signal line and keeps sending a high-level signal to the SCK signal line. If the received cyclic redundancy check code passes the check, the FPGA can end the exit.
Optionally, the number of communication slaves that communicate with the communication master is plural, and communications between the communication master and the communication slaves are independent from each other. This has the advantage of improving the efficiency of communication between the communication master and the plurality of communication slaves.
According to the communication anti-interference method provided by the embodiment of the invention, the level signals on the preset communication state signal line are changed before and after resetting the preset register, so that the communication host can timely determine the state of the preset register, the accuracy and the integrity of data transmission are ensured, the communication slave sends a response pulse signal to the communication host through the preset communication state signal line, the communication host can be informed that an instruction is processed, the communication host can send the next instruction, the order of communication is ensured, and the communication host can accurately determine whether the reset of the preset register is normal or not and whether the communication slave has reset faults or not by determining the first accumulated time.
Example III
Fig. 4 is a schematic structural diagram of a communication anti-interference device according to a third embodiment of the present invention. As shown in fig. 4, the apparatus includes a signal transmission module 401 and an instruction transmission module 403 disposed at a communication master, and a signal control module 402 disposed at a communication slave, wherein:
the signal sending module is used for sending a communication preparation signal to the communication slave;
the signal control module is used for resetting a preset register after detecting the communication preparation signal, and controlling a level signal on a preset communication state signal line to be a reset completion signal after the reset is completed, wherein the preset register is a register associated with communication between the communication host and the communication slave;
the instruction sending module is used for sending a control instruction to the communication slave machine after detecting the reset completion signal.
According to the communication anti-interference device provided by the embodiment of the invention, after the communication host sends the communication preparation signal to the communication slave, the communication slave can reset the preset register in time, delete interference data generated by electromagnetic interference in the preset register in time, influence normal data reception, and inform the communication host in time by using the preset communication state signal line after the reset is completed, so that the communication host can be informed to send the control instruction to the communication slave, the problem of communication abnormal condition caused by electromagnetic interference on a communication line is solved, and the communication reliability is improved.
Optionally, the signal control module includes:
a reset unit, configured to send a high-level signal to a preset communication state signal line after detecting the communication preparation signal, and reset a preset register;
and the signal switching unit is used for switching the high-level signal on the preset communication state signal line into the low-level signal after the completion of the reset of the preset register is determined, wherein the low-level signal on the preset communication state signal line belongs to the reset completion signal.
Optionally, the apparatus further comprises:
the pulse signal transmitting module belongs to a communication slave machine and is used for transmitting a response pulse signal to the communication host machine through the preset communication state signal line after the communication host machine transmits a control instruction to the communication slave machine and the received cyclic redundancy check code passes through the control instruction, wherein the response pulse signal is used for notifying the communication host machine that the control instruction is processed.
Optionally, the signal control module includes:
and the reset judging unit is used for determining that the communication slave machine fails to reset the preset register if the first accumulated time used for resetting the completion signal is not detected and exceeds a first preset duration after the communication slave machine sends a high-level signal to the preset communication state signal line and resets the preset register, wherein the timing starting time of the first accumulated time is the time when the communication host machine detects the high-level signal sent by the communication slave machine to the preset communication state signal line.
Optionally, the apparatus further comprises:
and the communication abnormality determining module belongs to a communication host and is used for determining that communication abnormality occurs between the communication host and the communication slave if a second accumulated time used by the response pulse signal is not detected after the communication slave sends the response pulse signal to the communication host through the preset communication state signal line and exceeds a second preset time length, wherein the timing starting time of the second accumulated time is the time when the communication host sends a control instruction corresponding to the response pulse signal to the communication slave.
Optionally, the preset register at least includes a shift register.
Optionally, the number of communication slaves that communicate with the communication master is plural, and communications between the communication master and the communication slaves are independent from each other.
The communication anti-interference device provided by the embodiment of the invention can execute the communication anti-interference method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example IV
Fig. 5 illustrates a schematic diagram of a communication tamper resistant system 50 that may be used to implement an embodiment of the present invention. The communication anti-interference system comprises: a communication master 51, a plurality of communication slaves 52, a processor 53 and a memory 54. The memory stores a computer program executable by the processor, which when executed by the processor, can enable the processor to instruct the communication host side to execute content executed by the communication host in the communication anti-interference method and instruct the communication slave side to execute content executed by the communication slave in the communication anti-interference method. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein. Fig. 6 is a schematic diagram of a communication structure of a communication host and a plurality of communication slaves, if the communication host is an FPGA chip, the communication slaves are MCU chips, and the communication mode is SPI communication, as shown in fig. 6, the communication host and the communication slaves may be different chips in the same electronic device, and a processor and a memory in the system may be built in the same host, and the host may be used for controlling, and the communication host and the communication slaves may implement a communication anti-interference method.
The memory in the communication tamper resistant system may be a Read Only Memory (ROM), a Random Access Memory (RAM), or the like, wherein the memory stores a computer program executable by at least one processor, and the processor may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) or the computer program loaded from a storage unit into the Random Access Memory (RAM). The processor, ROM and RAM are connected to each other by a bus. An input/output (I/O) interface is also connected to the bus.
A plurality of components in a communication tamper resistant system are connected to an I/O interface, comprising: an input unit such as a keyboard, a mouse, etc.; an output unit such as various types of displays, speakers, and the like; a storage unit 48 such as a magnetic disk, an optical disk, or the like; and communication units such as network cards, modems, wireless communication transceivers, and the like. The communication unit allows the communication tamper resistant system to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The processor may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of processors include, but are not limited to, central Processing Units (CPUs), graphics Processing Units (GPUs), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processors, controllers, microcontrollers, and the like. The processor performs the various methods and processes described above, such as the communication immunity method.
In some embodiments, the communication tamper-resistant method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and/or installed into the communication tamper resistant system via the ROM and/or the communication unit. One or more of the steps of the communication immunity method described above may be performed when the computer program is loaded into RAM and executed by a processor. Alternatively, in other embodiments, the processor may be configured to perform the communication immunity method in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
The computer equipment provided by the above can be used for executing the communication anti-interference method provided by any embodiment, and has corresponding functions and beneficial effects.
Example five
In the context of the present invention, a computer-readable storage medium may be a tangible medium, which when executed by a computer processor, is configured to perform a communication immunity method, the method comprising:
the communication host sends a communication preparation signal to the communication slave;
resetting a preset register after the communication slave detects the communication preparation signal, and controlling a level signal on a preset communication state signal line to be a reset completion signal after the reset is completed, wherein the preset register is a register associated with communication between the communication master and the communication slave;
and after the communication host detects the reset completion signal, a control instruction is sent to the communication slave.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer equipment provided by the above can be used for executing the communication anti-interference method provided by any embodiment, and has corresponding functions and beneficial effects.
It should be noted that, in the embodiment of the communication anti-interference device, each unit and module included are only divided according to the functional logic, but not limited to the above division, so long as the corresponding functions can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A method of communication immunity, comprising:
the communication host sends a communication preparation signal to the communication slave;
resetting a preset register after the communication slave detects the communication preparation signal, and controlling a level signal on a preset communication state signal line to be a reset completion signal after the reset is completed, wherein the preset register is a register associated with communication between the communication master and the communication slave;
and after the communication host detects the reset completion signal, a control instruction is sent to the communication slave.
2. The method according to claim 1, wherein resetting the preset register after the communication slave detects the communication preparation signal, and controlling the level signal on the preset communication state signal line to be a reset completion signal after the reset is completed, comprises:
after the communication slave detects the communication preparation signal, the communication slave sends a high-level signal to a preset communication state signal line and resets a preset register;
and after the communication slave determines that the reset of the preset register is completed, switching the high-level signal on the preset communication state signal line into the low-level signal, wherein the low-level signal on the preset communication state signal line belongs to a reset completion signal.
3. The method of claim 1, further comprising, after the communication master sends a control instruction to the communication slave:
after the communication slave machine finishes executing the control instruction and the received cyclic redundancy check code passes the check, the communication slave machine sends a response pulse signal to the communication host machine through the preset communication state signal line, wherein the response pulse signal is used for informing the communication host machine that the control instruction is processed.
4. The method of claim 2, further comprising, after the communication slave sends a high signal on a preset communication state signal line and resets a preset register:
if the communication host does not detect the first accumulated time used by the reset completion signal and exceeds a first preset duration, determining that the communication slave fails to reset the preset register, wherein the starting time of the first accumulated time is the time when the communication host detects a high-level signal sent by the communication slave to a preset communication state signal line.
5. A method according to claim 3, further comprising, after the communication slave transmits a response pulse signal to the communication master through the preset communication state signal line:
if the communication host does not detect the second accumulated time used by the response pulse signal and exceeds a second preset duration, determining that communication abnormality occurs between the communication host and the communication slave, wherein the timing starting time of the second accumulated time is the time when the communication host sends a control instruction corresponding to the response pulse signal to the communication slave.
6. The method of claim 1, wherein the pre-set registers comprise at least shift registers.
7. The method of claim 1, wherein the number of communication slaves communicating with the communication master is a plurality, and wherein the communication between the communication master and the communication slaves are independent of each other.
8. The communication anti-interference device is characterized by comprising a signal sending module and an instruction sending module which are arranged on a communication host machine, and a signal control module which is arranged on a communication slave machine, wherein:
the signal sending module is used for sending a communication preparation signal to the communication slave;
the signal control module is used for resetting a preset register after detecting the communication preparation signal, and controlling a level signal on a preset communication state signal line to be a reset completion signal after the reset is completed, wherein the preset register is a register associated with communication between the communication host and the communication slave;
the instruction sending module is used for sending a control instruction to the communication slave machine after detecting the reset completion signal.
9. A communication tamper resistant system, the system comprising:
a communication host side and a plurality of communication slave sides;
at least one processor; and a memory communicatively coupled to the at least one processor;
wherein the memory stores a computer program executable by the at least one processor to enable the at least one processor to instruct the communication master to perform the content of the communication antijamming method of any of claims 1-7, and instruct the communication slave to perform the content of the communication antijamming method of any of claims 1-7.
10. A computer readable storage medium storing computer instructions for causing a processor to implement the communication tamper resistant method of any one of claims 1-7 when executed.
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