CN115203092A - Single-master multi-slave single-wire communication method, device and equipment - Google Patents
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Abstract
The invention discloses a single-master multi-slave single-wire communication method, a single-master multi-slave single-wire communication device and single-master multi-slave single-wire communication equipment, relates to the field of communication, and is used for solving the problems of longer communication flow and larger communication power consumption in the prior art. The method, the device and the equipment are applied to a single-wire communication system, and the single-wire communication system comprises the following steps: the device comprises an upper computer, slave equipment and a single wire, wherein the single wire is provided with a plurality of slave equipment. Starting signal pulse through an upper computer; the reset pulse and the enable pulse in the pulse signal are used for controlling the slave equipment to enter a working state; a single-wire arbitration mechanism is adopted to carry out dynamic address allocation on all slave devices on the single wire; determining a data transmission sequence of all slave devices based on the dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence; the upper computer acquires the data sent by the slave equipment, single-line communication is completed, and communication efficiency is effectively improved.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a single-master multi-slave single-wire communication method, apparatus, and device.
Background
With the continuous development of technology, communication becomes an indispensable function between different devices or modules. The main communication means currently existing are wired communication and wireless communication. In fact, the wireless communication physical layer can evolve into single-wire communication, and finally, signals can also be converted into wired communication through the wireless transmitting and receiving module. The traditional wired communication modes mainly include serial communication and parallel communication. The serial communication has two communication modes of serial asynchronous communication and serial synchronous communication, wherein a transmitting and receiving end of the serial asynchronous communication needs to be connected with a transmission line and a ground wire.
single-Wire communication, which is one of serial asynchronous communication, is currently the most commonly used single-Wire communication method, which is the 1-Wire protocol defined by dallas corporation in DS18B20 temperature sensors, and has the greatest advantage of saving pin and wiring resources compared to conventional two-Wire (I2C), three-Wire (SPI) and other communication methods. The method has the disadvantages of longer communication flow and larger communication power consumption, and is generally unacceptable for application scenes such as the Internet of things and the like with sensitive power consumption and limited operation resources.
Therefore, it is desirable to provide a single master multiple slave single-wire communication scheme to solve the disadvantages of the existing single-wire communication.
Disclosure of Invention
The invention aims to provide a single-master multi-slave single-wire communication method, a single-master multi-slave single-wire communication device and single-master multi-slave single-wire communication equipment, which are used for solving the problems of longer communication flow and higher communication power consumption in the prior art.
In order to achieve the above purpose, the invention provides the following technical scheme:
in a first aspect, the present invention provides a single-master multi-slave single-wire communication method, which is applied to a single-wire communication system, and the single-wire communication system includes: host computer, slave unit and single line, have a plurality of slave units on the single line, the method includes:
the upper computer starts signal pulses; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
performing dynamic address allocation for all the slave devices on a single line;
determining a data transmission order of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
In a second aspect, the present invention provides a single-master multi-slave single-wire communication device, which is applied to a single-wire communication system, the single-wire communication system comprising: host computer, slave unit and single line, have a plurality of slave units on the single line, the device includes:
the signal pulse starting module is used for starting signal pulses by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
the dynamic address allocation module is used for performing dynamic address allocation on all the slave devices on the single line;
a data transmission sequence determining module, configured to determine a data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the data acquisition module is used for acquiring the data sent by the slave equipment by the upper computer to complete single-wire communication.
In a third aspect, the present invention provides a single-master multiple-slave single-wire communication apparatus, which is applied to a single-wire communication system, the single-wire communication system including: host computer, slave unit and single line, have a plurality of slave units on the single line, equipment includes:
the communication unit/communication interface is used for starting signal pulse by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
a processing unit/processor for dynamic address allocation for all said slave devices on a single line;
determining a data transmission order of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
In a fourth aspect, the present invention may also provide a computer storage medium having stored therein instructions that, when executed, implement the single master-multiple slave single wire communication method described above.
Compared with the prior art, the single-master multi-slave single-wire communication scheme provided by the invention is provided. The scheme is applied to a single-wire communication system, and the single-wire communication system comprises: the device comprises an upper computer, slave equipment and a single wire, wherein the single wire is provided with a plurality of slave equipment. The scheme starts signal pulse through an upper computer; the reset pulse and the enable pulse in the pulse signal are used for controlling the slave equipment to enter a working state; a single-wire arbitration mechanism is adopted to carry out dynamic address allocation on all slave devices on the single wire; determining a data transmission sequence of all slave devices based on the dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence; and the upper computer acquires the data sent by the slave equipment to complete single-wire communication. According to the scheme, the slave devices are controlled to enter the working state based on the pulse, dynamic address allocation is carried out on all the slave devices on the single line based on the single line arbitration mechanism, and the data sending sequence of the plurality of slave devices on the single line is determined based on the dynamic addresses, so that conflict-free simultaneous access to the plurality of slave devices on the single line is realized, the waste of the upper computer operation resources and the communication power consumption of the slave devices in the prior art is solved, and the communication efficiency is effectively improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic system structure diagram of a single-wire communication system applied to a single-master multiple-slave single-wire communication method provided by the invention;
FIG. 2 is a flow chart of a single-master multi-slave single-wire communication method provided by the present invention;
FIG. 3 is a schematic diagram of a single-line pulse signal provided by the present invention;
FIG. 4 is a schematic diagram illustrating a dynamic address allocation process in a single-master multi-slave single-wire communication method according to the present invention;
fig. 5 is a schematic diagram illustrating a data transmission flow of a slave device in a single-master multi-slave single-wire communication method according to the present invention;
FIG. 6 is a schematic structural diagram of a single-master multi-slave single-wire communication device according to the present invention;
fig. 7 is a schematic structural diagram of a single-master multi-slave single-wire communication device provided by the invention.
Detailed Description
In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.
Next, the scheme provided by the embodiments of the present specification will be described with reference to the accompanying drawings:
single-wire communication is one type of serial asynchronous communication, the protocol of which is defined between a master device and a slave device, both sharing a single-wire connection to transfer data to each other in a simultaneous bidirectional manner. In most cases, in the direction of data transmission from the transmitting data device to the receiving data device, the transmitting data device modulates the duty cycle of the periodic signal in accordance with the signal to be transmitted (logic level 0 or logic level 1), and the receiving data device recovers the data transmitted by the transmitting device by measuring the duty cycle. Both sides TTL signal carries out the communication through a signal line, a power cord and a ground wire, before beginning the communication: the master computer is in a sending state, and the slave computer is in a receiving state. The host CPU sends a low pulse signal of 20ms to inform the host to prepare to receive the host command, and the host sends the command to the slave according to the F2F code. If the slave responds, the slave responds according to the F2F code 2ms after the master sends the reading command.
Compared with communication methods such as a two-wire system (I2C) communication method and a three-wire System (SPI) communication method, although single-wire communication in the prior art can save pin and wiring resources, the existing single-wire communication process is complex, a first-level selection command needs to be sent first, and then a first-level task command needs to be sent to determine a specific executed task, the two-level command format increases software compiling difficulty, a large number of pulses need to be sent, and upper computer operation resources are wasted; in addition, only a single device can be accessed in one-time communication, a longer communication flow and larger communication power consumption are needed in a multipoint measurement system, and the requirements cannot be met in application scenarios such as the internet of things and the like with sensitive power consumption and limited computing resources.
Based on the above defects, the present solution provides a single-master multiple-slave single-wire communication scheme, and please refer to the following embodiments:
fig. 1 is a schematic system structure diagram of a single-wire communication system to which the single-master multi-slave single-wire communication method provided by the present invention is applied. As shown in fig. 1, the single-wire communication system includes: the system comprises an upper computer (or called a host), a slave device (or called a slave) and a single wire (or called a DIO). The upper computer is connected with all the slave devices through a single line. A plurality of slaves can be connected to a single wire, the single wire is connected to a power supply VDD through a pull-up resistor Rpu to form an open drain circuit, and the open drain circuit has the wired and characteristic; i.e., either slave device outputs 0 (pulls down single line), this results in a single line output of 0; all slave devices output 1 (release single wire) resulting in a single wire output 1. In practical applications, the pull-up resistor may be replaced by an external resistor, or may be built in the slave device, which may be specifically limited according to practical situations, and this specification does not specifically limit this.
Based on the single-wire communication system in fig. 1, the present invention provides a single-master multi-slave single-wire communication method applied to the single-wire communication system in fig. 1, as shown in fig. 2, fig. 2 is a flow chart of the single-master multi-slave single-wire communication method provided by the present invention. From the program perspective, the execution subject of the flow may be an upper computer.
As shown in fig. 2, the process may include the following steps:
step 210: the upper computer starts signal pulses; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter an operating state.
In the field of communications, SET: set instruction, RST: and resetting the instruction. The SET and RST commands are a pair of commands and are mainly used for holding and resetting the output relay, the state machine and the auxiliary relay. PLS denotes a rising edge differential output command, and PLF denotes a falling edge trigger command. Wherein, SET SET pulse, the function is action hold. RST reset pulse, function is clear action hold, zero clearing of the register. The enable pulse is like a trigger signal, mainly a switching signal to ensure the normal operation of the circuit or device. I.e. a function in the circuit can be switched on or off by this signal. The data pulse may include a data 1 pulse and a data 0 pulse.
In the present invention, four signal types are defined, which may include:
reset pulse: the upper computer pulls down the single wire, releasing the single wire after tRST continues.
Enabling the pulse: and the upper computer pulls down the single wire, and releases the single wire after the tACT is continued.
Data 0 pulse: the upper computer pulls down the single wire, and releases the single wire after the tRL is continued; after the slave device detects the falling edge of the single wire, the single wire starts to be pulled down, and after the tRDV is continued, the single wire is released.
Wherein, tRST (Reset Time) is used to indicate Reset Time, tRDV (Read Data Valid Time) is used to indicate Read Data Valid Time, tACT (active Time) is used to indicate activation Time, and tRL (Read Low) is used to indicate Read pulse pull-down Time.
The pulse signal defined in the present scheme can be explained with reference to fig. 3. Fig. 3 is a schematic diagram of a single-line pulse signal provided by the present invention. As shown in fig. 3, the timing parameters satisfy: tRL < tRDV < tACT < tRST. Adjacent signal pulses require a spacing tREC.
All signal pulses are started by the upper computer: the reset pulse and the enable pulse are used for controlling the slave equipment to enter the corresponding working state; the data pulse is used to read the 1-bit data output from the device. The data pulse is divided into a data 0 pulse and a data 1 pulse according to the difference of actions of the slave devices after detecting the falling edge of the single line. The upper computer and the slave equipment can sample the single line within the time range of tRL < t < tRDV, and when the single line is sampled to be at a logic high level, the single line is indicated to be a data 0 pulse and carries 1-bit data 0; when the single line is sampled to be in a logic low level, the single line is described as a data 1 pulse and carries 1-bit data 1.
Step 220: dynamic address allocation is performed for all of the slave devices on a single line.
A plurality of slave devices are hung on a single line, and a dynamic address needs to be allocated to each slave device, so that the slave devices can send data in sequence, and data collision does not occur.
Step 230: determining a data transmission order of all the slave devices based on the allocated dynamic addresses; and the slave equipment entering the working state transmits data according to the data transmission sequence.
The dynamic address of each slave device may correspond to a data transmission order, determine its own data transmission order according to its own assigned dynamic address, and then transmit data according to the transmission order.
Step 240: and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
The method of fig. 2, initiating a signal pulse by the host computer; the reset pulse and the enable pulse in the pulse signal are used for controlling the slave equipment to enter a working state; a single-wire arbitration mechanism is adopted to carry out dynamic address allocation on all slave devices on the single wire; determining a data transmission sequence of all slave devices based on the dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence; and the upper computer acquires the data sent by the slave equipment to complete single-wire communication. According to the scheme, the slave devices are controlled to enter the working state based on the pulse, dynamic address allocation is carried out on all the slave devices on the single line based on the single line arbitration mechanism, and the data sending sequence of the plurality of slave devices on the single line is determined based on the dynamic addresses, so that conflict-free simultaneous access to the plurality of slave devices on the single line is realized, the waste of the upper computer operation resources and the communication power consumption of the slave devices in the prior art is solved, and the communication efficiency is effectively improved.
Based on the method of fig. 2, the embodiments of the present specification also provide some specific implementations of the method, which are described below.
Optionally, the performing dynamic address allocation on all the slave devices on the single line may specifically include:
when the outputs of the slave devices are different, determining that the single lines have data collision, and the upper computer sends a reset pulse to control all the slave devices on the single lines to enter an address allocation state;
the upper computer starts a data pulse and reads a response bit;
if the data of the response bit is 0, determining that the slave equipment responds, starting a first number of data pulses by the upper computer, and reading the priority level of the corresponding slave equipment; the priority levels corresponding to all slave devices are numerical values which are stored in binary number format by using a nonvolatile memory by each slave device;
a single-wire arbitration mechanism is utilized to ensure that no data conflict exists in each round of reading, and the read result is the priority level with the minimum value participating in the current round of allocation, so that single-round address allocation is completed; the data pulse comprises a data 1 pulse and a data 0 pulse;
if the data of the response bit is 1, determining that no slave device responds, and ending address allocation.
In the scheme, when address allocation is carried out, allocation can be carried out on the basis of a single-wire arbitration mechanism, and the slave equipment which outputs 0 is judged to win single-wire arbitration by utilizing the 'wire AND' characteristic, so that the slave equipment is allowed to continuously output the rest bits; and the slave equipment of the output 1 loses the control right on the single wire, and the distribution of the current round must be quitted, and the single wire is released, so that the subsequent single wire communication state is not interfered, and the next round of distribution is waited again. The single-wire arbitration mechanism may be that the slave device samples a single wire while outputting its own data, so as to obtain a single-wire arbitration result:
the slave device samples a single line while outputting self data, and if the output self data and the sampling single line are both 1, it is determined that no data collision occurs at the bit;
if the output self data and the sampling single line are both 0, determining that no data conflict occurs in the bit or that data conflict occurs and winning arbitration by self;
if the output self data is 1 and the sampling single line is 0, determining that data collision occurs at the bit and that the self does not win arbitration;
and if the output self data is 0 and the sampling single line is 1, determining that the circuit connection fails.
The arbitration mechanism of the invention has the advantages that the smaller the priority value is, the higher the arbitration priority is.
In practical application, when single-wire communication is carried out, address allocation is required to be carried out firstly, then data are transmitted according to the allocated address sequence, communication is achieved, and when address allocation is carried out, the slave device compares the priority level of the slave device with the priority levels of other slave devices on a single wire, and the data transmission sequence of the slave device is determined. For example: only slave 1, slave 2 and slave 3 are present on a single line, and the three may have priority levels of 3, 1, 6, respectively. After address assignment, the slave device 1, the slave device 2, and the slave device 3 determine data transmission orders to be 2 nd, 1 st, and 3 rd, respectively.
After the addresses are distributed, the slave device measures and converts the environment quantity, and then sequentially outputs the environment quantity to a single line according to the data transmission sequence of the slave device and is acquired by the upper computer. In the above example, the host computer will continuously read three rounds of data, which are the outputs of the slave 2, the slave 1, and the slave 3, respectively.
It should be noted that the method provided in this embodiment is mainly directed to a single-wire communication method when multiple slave devices are mounted on a single wire. In practical application, if only one slave device is mounted on a single line, dynamic address allocation is not needed, and the slave device can directly send data.
When determining the data transmission order of the slave devices, the following method can be used:
each slave device uses a non-volatile memory such as Fuse, OTP, EPROM, EEPROM to hold a value in binary format as its own priority.
The slave devices having smaller priority values have the earlier data transmission order.
All slave devices mounted on the same single line must have different respective priority levels.
As one embodiment, a flow of performing dynamic address allocation in this scheme may be described with reference to fig. 3, fig. 4 is a schematic diagram of a flow of dynamic address allocation in a single-master multiple-slave single-wire communication method provided by the present invention, and as shown in fig. 4, the flow may include:
step 1: the upper computer sends a reset pulse to control all slave devices on the single line to enter an address allocation state.
And 2, step: and the upper computer starts a data pulse and reads the response bit. If the data is 0, the slave device responds, and the step 3 can be continued; if the data is 1, the slave device does not respond, and the address allocation is finished.
And 3, step 3: the upper computer starts n data pulses and reads the priority P [ n:1]. The arbitration mechanism ensures that there is no data collision for each read round, and the read result is the priority level with the minimum value for participating in the round of allocation.
And 4, step 4: one round of allocation is completed and the slave device with priority level P n:1 has its address allocated as the round number a.
And repeating the steps 2, 3 and 4 until the end.
After the address is allocated, the flow of data transmission by the slave device may be described with reference to fig. 5, where fig. 5 is a schematic diagram of a data transmission flow of the slave device in the single-master-multiple-slave single-wire communication method provided by the present invention, and the flow may include:
step 1: the upper computer sends an enabling pulse to control all the slave devices on the single line to start measuring the environmental quantity.
And 2, step: the upper computer polls the single wire. If the query result is 0, the slave equipment does not complete the measurement; if the query result is 1, which indicates that all the slave devices have completed measurement, step 3 may be started.
And step 3: the upper computer starts m data pulses and reads the measured data Dm: 1. After address assignment, all slaves have acknowledged their own transmission order, so no data collision occurs at this stage.
And 4, step 4: one round of acquisition is completed. And if the slave device searched in the address allocation phase is not completely traversed, returning to the step 3, otherwise, ending the data acquisition phase.
The scheme in the above embodiment controls the slave devices to enter the working state based on the pulse, performs dynamic address allocation for all the slave devices on the single line based on the single-line arbitration mechanism, and determines the data transmission sequence of the plurality of slave devices on the single line based on the dynamic address, thereby implementing collision-free simultaneous access to the plurality of slave devices on the single line, defining a new pulse, and starting the action with only the two pulses (the reset pulse and the enable pulse). A set of address assignment procedures is defined. After all slaves are assigned addresses, all slaves are allowed to issue in sequence.
The prior art is memory fixed memory addresses. The addresses are fixed, in the scheme, the addresses are dynamically allocated, the address allocation determines a transmission sequence, the slave machines complete data transmission according to the transmission sequence, single-wire data transmission based on pulses, slave equipment addresses are dynamically allocated based on a single-wire arbitration mechanism, conflict-free simultaneous access to a plurality of slave equipment is realized based on the dynamic addresses, and the plurality of slave equipment can be simultaneously accessed without conflict without any command format, so that the waste of upper computer operation resources and slave equipment communication power consumption in the prior art is solved, and the communication efficiency is effectively improved.
Based on the same idea, the embodiment of the present specification further provides a single-master multi-slave single-wire communication device. Fig. 6 is a schematic structural diagram of a single-master multi-slave single-wire communication device according to the present invention. The device is applied to a single-wire communication system, and the single-wire communication system comprises: host computer, slave unit and single line, have a plurality of slave units on the single line, as shown in fig. 6, can include:
a signal pulse starting module 610, configured to start a signal pulse by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
a dynamic address allocation module 620, configured to perform dynamic address allocation for all the slave devices on a single line;
a data transmission order determination module 630, configured to determine a data transmission order of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the data acquisition module 640 is used for acquiring the data sent by the slave equipment by the upper computer to complete single-wire communication.
Based on the apparatus in fig. 6, there are some implementation modules, which are described below:
optionally, the dynamic address allocating module 620 may specifically include:
the reset pulse sending unit is used for determining that the single line has data conflict when the outputs of the slave devices are different, and the upper computer sends reset pulses to control all the slave devices on the single line to enter an address allocation state;
the data pulse starting unit is used for starting a data pulse by the upper computer and reading a response bit;
the priority reading unit is used for determining that slave equipment responds if the data of the response bit is 0, starting a first number of data pulses by the upper computer and reading the priority of the corresponding slave equipment; the priority levels corresponding to all slave devices are numerical values which are stored in binary number format by using a nonvolatile memory by each slave device;
the single-round address allocation unit is used for ensuring that no data conflict exists in each round of reading by utilizing a single-wire arbitration mechanism, and finishing single-round address allocation if the read result is the priority level with the minimum value participating in the current round of allocation; the data pulse comprises a data 1 pulse and a data 0 pulse;
if the data of the response bit is 1, determining that no slave device responds, and ending address allocation.
Optionally, the single wire may be connected to a power supply through a pull-up resistor to form an open-drain circuit; the open drain circuit has a line and a characteristic; the line and characteristic indicates that if any one of the slave devices outputs 0, then the single line outputs 0; if all the slave devices output 1, outputting 1 by a single line;
the dynamic address allocation module 620 may be specifically configured to:
and determining the slave equipment outputting 0 to output the residual bit based on the line and the characteristic, the slave equipment outputting 1 loses the control right on the single line, quits the distribution of the current round, releases the single line and waits for the next round of distribution again.
Optionally, the apparatus may further include:
the data output module is used for sampling a single line while the slave device outputs own data;
the judging module is used for determining that data collision does not occur at the bit if the output self data and the sampling single line are both 1;
if the output self data and the sampling single line are both 0, determining that no data conflict occurs in the bit or that data conflict occurs and winning arbitration by self;
if the output self data is 1 and the sampling single line is 0, determining that data collision occurs at the bit and that the self does not win arbitration;
and if the output self data is 0 and the sampling single line is 1, determining that the circuit connection fails.
Optionally, the apparatus may further include:
the priority output module is used for outputting the self priority to the single line by all the slave devices on the single line at the same time in the address allocation stage; slave devices mounted on the same single line have different priority levels;
the priority comparison module is used for comparing the priority of all the slave equipment outputs, and the smaller the priority value is, the higher the corresponding single-line arbitration priority is;
and the dynamic address allocation module is used for performing dynamic address allocation on the slave equipment based on the priority level.
Based on the same idea, the embodiment of the present specification further provides a single-master multi-slave single-wire communication device. Fig. 7 is a schematic structural diagram of a single-master multi-slave single-wire communication device provided by the invention. The apparatus is applied to a single-wire communication system, which includes: host computer, slave unit and single line, have a plurality of slave units on the single line, equipment can include:
the communication unit/communication interface is used for starting signal pulse by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
a processing unit/processor for dynamic address allocation for all said slave devices on a single line;
determining a data transmission order of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
As shown in fig. 7, the terminal device may further include a communication line. The communication link may include a path for transmitting information between the aforementioned components.
Optionally, as shown in fig. 7, the terminal device may further include a memory. The memory is used for storing computer-executable instructions for implementing the inventive arrangements and is controlled by the processor for execution. The processor is used for executing computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.
As shown in fig. 7, the memory may be a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to. The memory may be self-contained and coupled to the processor via a communication link. The memory may also be integral to the processor.
Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.
In one implementation, as shown in FIG. 7, a processor may include one or more CPUs, such as CPU0 and CPU1 of FIG. 7, for example.
In one implementation, as shown in fig. 7, a terminal device may include a plurality of processors, such as the processor in fig. 7, for example. Each of these processors may be a single-core processor or a multi-core processor.
Based on the same idea, embodiments of the present specification further provide a computer storage medium corresponding to the foregoing embodiments, where the computer storage medium stores instructions, and when the instructions are executed, the single-master multiple-slave single-wire communication method in the foregoing embodiments is implemented.
The above description mainly introduces the scheme provided by the embodiment of the present invention from the perspective of interaction between the modules. It is understood that each module contains hardware structure and/or software unit for executing each function in order to realize the above functions. Those of skill in the art will readily appreciate that the invention is capable of being implemented as hardware or a combination of hardware and computer software in connection with the exemplary elements and algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed in hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The functional modules may be divided according to the above method examples, for example, the functional modules may be divided corresponding to the functions, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, the division of the modules in the embodiment of the present invention is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
The processor in this specification may also have the function of a memory. The memory is used for storing computer-executable instructions for implementing the inventive arrangements and is controlled by the processor for execution. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.
The memory may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disk read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disk, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be separate and coupled to the processor via a communication link. The memory may also be integral to the processor.
Optionally, the computer execution instruction in the embodiment of the present invention may also be referred to as an application program code, which is not specifically limited in the embodiment of the present invention.
The method disclosed by the embodiment of the invention can be applied to a processor or realized by the processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in ram, flash, rom, prom, or eprom, registers, etc. as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and combines hardware thereof to complete the steps of the method.
In one possible implementation, a computer-readable storage medium is provided, in which instructions are stored, and when executed, are used to implement the method in the foregoing embodiments.
In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).
While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely illustrative of the invention as defined by the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A single master multiple slave single wire communication method, applied to a single wire communication system, the single wire communication system comprising: host computer, slave unit and single line, have a plurality of slave units on the single line, the method includes:
the upper computer starts signal pulses; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
performing dynamic address allocation for all the slave devices on a single line;
determining a data transmission order of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
2. The method according to claim 1, wherein the performing dynamic address allocation for all the slave devices on a single line comprises:
when the outputs of the slave devices are different, determining that the single lines have data collision, and the upper computer sends a reset pulse to control all the slave devices on the single lines to enter an address allocation state;
the upper computer starts a data pulse and reads a response bit;
if the data of the response bit is 0, determining that the slave equipment responds, starting a first number of data pulses by the upper computer, and reading the priority level of the corresponding slave equipment; the priority levels corresponding to all slave devices are numerical values which are stored in binary number format by using a nonvolatile memory by each slave device;
a single-wire arbitration mechanism is utilized to ensure that no data conflict exists in each round of reading, and the read result is the priority level with the minimum value participating in the current round of allocation, so that single-round address allocation is completed; the data pulse comprises a data 1 pulse and a data 0 pulse;
if the data of the response bit is 1, determining that no slave device responds, and ending address allocation.
3. The method according to claim 1, wherein the single wire is connected to a power supply through a pull-up resistor to constitute an open-drain circuit; the open drain circuit has a line and a characteristic; the line and characteristic indicates that if any one of the slave devices outputs 0, then a single line outputs 0; if all the slave devices output 1, outputting 1 by a single line;
the dynamic address allocation for all the slave devices on the single line specifically includes:
and determining the output residual bit of the slave equipment with the output 0 based on the line and the characteristic, losing the control right of the slave equipment with the output 1 to the single line, exiting the distribution of the current round, releasing the single line, and waiting for the next round of distribution again.
4. The method of claim 3, further comprising:
the slave device samples the single line while outputting the self data, and if the output self data and the sampling single line are both 1, it is determined that no data collision occurs in the corresponding bit;
if the output self data and the sampling single line are both 0, determining that no data conflict occurs in the corresponding bit or data conflict occurs and winning arbitration by self;
if the output data per se is 1 and the sampling single line is 0, determining that data collision occurs to the corresponding bit and that the corresponding bit does not win arbitration;
and if the output self data is 0 and the sampling single line is 1, determining that the circuit connection fails.
5. The method of claim 2, wherein prior to dynamically assigning addresses to all of the slave devices on a single line, further comprising:
all slave devices on the single line output own priority levels to the single line simultaneously; slave devices mounted on the same single line have different priority levels;
comparing the priority levels output by all slave devices, wherein the smaller the numerical value of the priority level is, the higher the corresponding single-line arbitration priority level is;
and performing dynamic address allocation for the slave device based on the priority level.
6. The method according to claim 2, wherein the upper computer acquires the data sent by the slave device to complete single-wire communication, and specifically comprises:
the upper computer sends the enabling pulse to control all slave devices on the single line to start measuring the environmental quantity;
the upper computer polls the single line, and if the single line is queried to be 0, it is determined that the slave equipment is not measured;
if the single line query result is 1, determining that all the slave devices have completed measurement;
and when the slave devices complete measurement, the upper computer starts a second number of data pulses, reads the measured data and completes one round of data acquisition.
7. The method according to claim 6, wherein the slave device entering the working state performs data transmission according to the data transmission sequence, and specifically includes:
after the slave device measures and converts the environment quantity, the environment quantity is sequentially output to a single line according to the data sending sequence of the slave device and is acquired by the upper computer.
8. A single master multiple slave single wire communication apparatus for use in a single wire communication system, the single wire communication system comprising: host computer, slave unit and single line, have a plurality of slave units on the single line, the device includes:
the signal pulse starting module is used for starting signal pulses by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
the dynamic address allocation module is used for performing dynamic address allocation on all the slave devices on the single line;
a data transmission sequence determining module, configured to determine a data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the data acquisition module is used for acquiring the data sent by the slave equipment by the upper computer to complete single-wire communication.
9. A single master multiple slave single wire communication apparatus for use in a single wire communication system, said single wire communication system comprising: host computer, slave unit and single line, have a plurality of slave units on the single line, equipment includes:
the communication unit/communication interface is used for starting signal pulse by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave equipment to enter a working state;
a processing unit/processor for dynamic address allocation for all said slave devices on a single line;
determining a data transmission order of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state transmits data according to the data transmission sequence;
and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
10. A computer storage medium having stored thereon instructions that, when executed, implement a single master multiple slave single wire communication method according to any one of claims 1 to 7.
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