CN115203092B - Single-master multi-slave single-wire communication method, device and equipment - Google Patents
Single-master multi-slave single-wire communication method, device and equipment Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a single-master multi-slave single-wire communication method, device and equipment, relates to the field of communication, and aims to solve the problems of longer communication flow and larger communication power consumption in the prior art. Methods, apparatus and devices are applied to a single-wire communication system comprising: the system comprises an upper computer, slave devices and a single wire, wherein the single wire is provided with a plurality of slave devices. Starting signal pulse through the upper computer; wherein the reset pulse and the enable pulse in the pulse signal are used for controlling the slave device to enter the working state; adopting a single-wire arbitration mechanism to carry out dynamic address allocation for all slave devices on a single wire; determining the data transmission sequence of all slave devices based on the dynamic address; the slave equipment entering the working state transmits data according to the data transmission sequence; and the upper computer acquires the data sent by the slave equipment to complete single-wire communication, so that the communication efficiency is effectively improved.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a single-master multi-slave single-wire communication method, apparatus, and device.
Background
With the continuous development of technology, communication becomes an indispensable function between different devices or modules. The main communication modes existing at present are wired communication and wireless communication. In fact, the wireless communication physical layer may evolve into single-wire communication, and finally, the signal is converted into wired communication through the wireless transmitting and receiving module. The traditional wired communication mode mainly comprises serial communication and parallel communication. Serial communication has two communication modes of serial asynchronous communication and serial synchronous communication, wherein a transmitting and receiving end of the serial asynchronous communication needs to be connected with a transmission line and a ground line.
single-Wire communication is one of serial and asynchronous communication, and the most commonly used single-Wire communication method at present is a 1-Wire protocol defined by Dallas corporation in a DS18B20 temperature sensor, and compared with the traditional two-Wire system (I2C), three-Wire System (SPI) and other communication methods, the single-Wire communication method has the greatest advantage of saving pin and wiring resources. The method has the defects of longer communication flow and larger communication power consumption, and is generally unacceptable for application scenes such as power consumption sensitivity of the Internet of things and the like and limited operation resources.
Accordingly, there is a need to provide a single-master multi-slave single-wire communication scheme to solve the drawbacks of the existing single-wire communication.
Disclosure of Invention
The invention aims to provide a single-master multi-slave single-wire communication method, device and equipment, which are used for solving the problems of longer communication flow and larger communication power consumption in the prior art.
In order to achieve the above object, the present invention provides the following technical solutions:
in a first aspect, the present invention provides a single-master multi-slave single-wire communication method, which is applied to a single-wire communication system, the single-wire communication system comprising: the method comprises the steps of enabling the host computer to perform data transmission, enabling the slave devices to perform data transmission, and enabling the slave devices to perform data transmission, wherein the single line is provided with a plurality of slave devices, and the method comprises the following steps:
the upper computer starts signal pulses; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
dynamic address allocation is carried out for all slave devices on a single line;
determining the data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
In a second aspect, the present invention provides a single-master multi-slave single-wire communication device, the device being applied to a single-wire communication system, the single-wire communication system comprising: the host computer, slave device and single line, have a plurality of slave devices on the single line, the device includes:
The signal pulse starting module is used for starting signal pulses by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
the dynamic address allocation module is used for carrying out dynamic address allocation on all the slave devices on a single line;
a data transmission sequence determining module, configured to determine a data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
and the data acquisition module is used for acquiring the data sent by the slave equipment by the upper computer and completing single-wire communication.
In a third aspect, the present invention provides a single-master multi-slave single-wire communication device, the device being applied to a single-wire communication system, the single-wire communication system comprising: the host computer, slave device and single line, have a plurality of slave devices on the single line, the equipment includes:
the communication unit/communication interface is used for starting signal pulses by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
A processing unit/processor for dynamically allocating addresses to all the slave devices on a single line;
determining the data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
In a fourth aspect, the present invention may also provide a computer storage medium having instructions stored therein, which when executed, implement the single-master multi-slave single-wire communication method described above.
Compared with the prior art, the single-master multi-slave single-wire communication scheme provided by the invention is characterized in that the single-master multi-slave single-wire communication scheme is adopted. The scheme is applied to a single-wire communication system, which comprises: the system comprises an upper computer, slave devices and a single wire, wherein the single wire is provided with a plurality of slave devices. The scheme starts signal pulse through the upper computer; wherein the reset pulse and the enable pulse in the pulse signal are used for controlling the slave device to enter the working state; adopting a single-wire arbitration mechanism to carry out dynamic address allocation for all slave devices on a single wire; determining the data transmission sequence of all slave devices based on the dynamic address; the slave equipment entering the working state transmits data according to the data transmission sequence; and the upper computer acquires the data sent by the slave equipment to complete single-wire communication. In the scheme, the slave devices are controlled to enter the working state based on the pulse, dynamic address allocation is carried out on all the slave devices on a single line based on a single line arbitration mechanism, and the data transmission sequence of the plurality of slave devices on the single line is determined based on the dynamic address, so that the conflict-free simultaneous access of the plurality of slave devices on the single line is realized, the waste of the operation resource of an upper computer and the communication power consumption of the slave devices in the prior art is solved, and the communication efficiency is effectively improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a schematic diagram of a system structure of a single-wire communication system to which a single-master multi-slave single-wire communication method provided by the invention is applied;
FIG. 2 is a schematic flow chart of a single-master multi-slave single-wire communication method provided by the invention;
FIG. 3 is a schematic diagram of a single-line pulse signal provided by the present invention;
FIG. 4 is a schematic diagram of a dynamic address allocation flow in a single-master multi-slave single-wire communication method provided by the invention;
fig. 5 is a schematic diagram of a slave device data transmission flow in the single-master multi-slave single-wire communication method provided by the invention;
fig. 6 is a schematic structural diagram of a single-master multi-slave single-wire communication device according to the present invention;
fig. 7 is a schematic structural diagram of a single-master multi-slave single-wire communication device provided by the invention.
Detailed Description
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
Next, the scheme provided by the embodiments of the present specification will be described with reference to the accompanying drawings:
single wire communication is one type of serial asynchronous communication, the protocol of which is defined between a master device and a slave device, which share a single wire connection in order to transfer data to each other in a simultaneous bi-directional manner. In most cases, in the direction in which the transmitting data device transmits data to the receiving data device, the transmitting data device modulates the duty cycle of the periodic signal according to the signal to be transmitted (logic level 0 or logic level 1), and the receiving data device restores the data transmitted by the transmitting device by measuring the duty cycle. The TTL signals of both parties are communicated through a signal wire, a power wire and a ground wire, and before communication is started: the host computer is in a transmitting state, and the slave computer is in a receiving state. The host CPU initiates, gives a low pulse signal of 20ms, informs the host to prepare to receive the host command, and the host sends the command to the slave according to the F2F code. If the slave is to respond, the slave responds by encoding the response in F2 ms after the host sends the read command.
Compared with communication methods such as two-wire system (I2C), three-wire System (SPI) and the like, the single-wire communication in the prior art can save pin and wiring resources, but the existing single-wire communication flow is complex, a first-stage selection command needs to be sent firstly, then a first-stage task command determines a specific execution task, the two-stage command format increases the software programming difficulty, a large number of pulses need to be sent, and the operation resource of an upper computer is wasted; in addition, only a single device can be accessed in one communication, longer communication flow and larger communication power consumption are needed in the multipoint measurement system, and the requirements cannot be met for application scenes with sensitive power consumption, such as the Internet of things and limited operation resources.
Based on the defects, the scheme provides a single-master multi-slave single-wire communication scheme, and the specific implementation scheme is as follows:
fig. 1 is a schematic diagram of a system structure of a single-wire communication system to which the single-master multi-slave single-wire communication method provided by the invention is applied. As shown in fig. 1, the single-wire communication system includes: host computer (or called host computer), slave device (or called slave computer) and single line (or called DIO). The upper computer is connected with all slave devices through a single wire. A plurality of slaves can be connected to a single wire, and the single wire is connected to a power supply VDD through a pull-up resistor Rpu to form an open drain circuit, and the open drain circuit has the characteristics of wires and; that is, any slave device outputs 0 (pulls down the single line), resulting in a single line output of 0; all slaves output a 1 (release single line) which would result in a single line output of 1. In practical application, the pull-up resistor may be replaced by an external resistor, or may be built in the slave device, and the pull-up resistor may be specifically limited according to practical situations, which is not specifically limited in this specification.
Based on the single-wire communication system in fig. 1, the present invention provides a single-master multi-slave single-wire communication method applied to the single-wire communication system in fig. 1, as shown in fig. 2, fig. 2 is a schematic flow chart of the single-master multi-slave single-wire communication method provided by the present invention. From the program perspective, the execution subject of the flow may be an upper computer.
As shown in fig. 2, the process may include the steps of:
step 210: the upper computer starts signal pulses; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state.
In the communication field, SET: set instruction, RST: a reset instruction. The SET instruction and the RST instruction are a pair of instructions and are mainly used for maintaining and resetting the output relay, the state machine and the auxiliary relay. PLS represents a rising edge differential output command, and PLF represents a falling edge trigger command. The SET pulse is SET, and the function is action retention. RST reset pulse, function is clear action hold, zero clearing of register. The enable pulse is similar to a trigger signal, and is mainly a switching signal for ensuring the normal operation of a circuit or a device. That is, a certain function in the circuit can be turned on or off by this signal. The data pulses may include data 1 pulses and data 0 pulses.
In the present invention, four signal types are defined, which may include:
reset pulse: the upper computer pulls down the single line and releases the single line after the tST is continued.
An enable pulse: the upper computer pulls down the single line and releases the single line after the tACT is continued.
Data 0 pulse: the upper computer pulls down the single wire, and releases the single wire after tRL; after the slave detects the falling edge of the single line, the single line starts to be pulled down, and the single line is released after the slave continuously reaches the tDV.
Data 1 pulse: the upper computer pulls down the single wire, and releases the single wire after tRL; and after the slave device detects the falling edge of the single wire, the single wire is directly released.
tRST (Reset Time), tRDV (Read Data Valid Time), tACT (Activate Time), and tRL (Read Low) are respectively used for representing reset time, read data valid time and Read pulse pull-down time, respectively.
The pulse signal defined in this scheme can be explained in connection with fig. 3. Fig. 3 is a schematic diagram of a single-line pulse signal provided by the present invention. As shown in fig. 3, each timing parameter satisfies: tRL < tDV < tACT < tST. Adjacent signal pulses require a spacing tREC.
All signal pulses are started by the upper computer: the reset pulse and the enable pulse are used for controlling the slave device to enter a corresponding working state; the data pulse is used to read 1-bit data output from the device. The data pulses are divided into data 0 pulses and data 1 pulses according to the difference in actions of the slave device after detecting a single line falling edge. The upper computer and the slave equipment can sample a single line in the time range of tRL < t < tDV, and when the single line is sampled to be at a logic high level, the single line is indicated to be a data 0 pulse and carries 1-bit data 0; when the single line is sampled to be at a logic low level, the data is illustrated as a data 1 pulse, carrying 1-bit data 1.
Step 220: dynamic address allocation is performed for all the slave devices on a single line.
A plurality of slave devices are mounted on a single line, and dynamic addresses are required to be allocated to each slave device, so that the slave devices can send data sequentially, and data collision is avoided.
Step 230: determining the data transmission sequence of all the slave devices based on the allocated dynamic addresses; and the slave equipment entering the working state performs data transmission according to the data transmission sequence.
The dynamic address of each slave device may correspond to a data transmission order, determine its own data transmission order according to its own allocated dynamic address, and then transmit data according to the transmission order.
Step 240: and the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
In the method in FIG. 2, the signal pulse is started by the upper computer; wherein the reset pulse and the enable pulse in the pulse signal are used for controlling the slave device to enter the working state; adopting a single-wire arbitration mechanism to carry out dynamic address allocation for all slave devices on a single wire; determining the data transmission sequence of all slave devices based on the dynamic address; the slave equipment entering the working state transmits data according to the data transmission sequence; and the upper computer acquires the data sent by the slave equipment to complete single-wire communication. In the scheme, the slave devices are controlled to enter the working state based on the pulse, dynamic address allocation is carried out on all the slave devices on a single line based on a single line arbitration mechanism, and the data transmission sequence of the plurality of slave devices on the single line is determined based on the dynamic address, so that the conflict-free simultaneous access of the plurality of slave devices on the single line is realized, the waste of the operation resource of an upper computer and the communication power consumption of the slave devices in the prior art is solved, and the communication efficiency is effectively improved.
Based on the method of fig. 2, the present description examples also provide some specific implementations of the method, as described below.
Optionally, the dynamically allocating addresses to all the slave devices on the single line may specifically include:
when the output of the slave devices is different, determining that the single line has data conflict, and sending a reset pulse by the upper computer to control all the slave devices on the single line to enter an address allocation state;
the upper computer starts a data pulse and reads a response bit;
if the data of the response bit is 0, determining that the slave device responds, starting a first number of data pulses by the upper computer, and reading the priority level of the corresponding slave device; the priority level corresponding to all the slave devices is a numerical value stored in a binary number format by using a nonvolatile memory by each slave device;
the single-wire arbitration mechanism is utilized to ensure that no data conflict exists in each round of reading, and the reading result is the priority level with the minimum numerical value participating in the round of allocation, so that the single round of address allocation is completed; the data pulses include data 1 pulses and data 0 pulses;
if the data of the response bit is 1, determining that the slave device does not respond, and ending address allocation.
In the scheme, when address allocation is performed, the allocation can be performed based on a single-wire arbitration mechanism, and the slave device outputting 0 is judged to win single-wire arbitration by utilizing the characteristics of 'line AND', so that the slave device is allowed to continuously output the residual bit; the slave device of output 1 loses control over the single line, must exit the round of allocation, release the single line, so as not to interfere with the subsequent single line communication state, and wait for the next round of allocation again. The single-wire arbitration mechanism can be that the slave device can sample a single wire while outputting own data, so that a single-wire arbitration result is obtained:
The slave device samples a single line while outputting self data, and if the self data and the sampling single line which are output are both 1, the slave device determines that no data collision occurs in the bit;
if the self data and the sampling single line which are output are both 0, determining that no data conflict occurs in the bit or the data conflict occurs, and winning arbitration by the self;
if the self data output is 1 and the sampling single line is 0, determining that data conflict occurs in the bit and self does not win arbitration;
and if the self data output is 0 and the sampling single line is 1, determining that the circuit is connected with faults.
The arbitration mechanism of the present invention has a higher arbitration priority as the priority value is smaller.
In practical application, when single-wire communication is performed, address allocation is required, then data is transmitted according to the allocated address sequence, communication is realized, and when address allocation is performed, the slave device compares the priority level of the slave device with the priority levels of other slave devices on the single wire, and determines the data transmission sequence of the slave device. For example: only slave 1, slave 2 and slave 3 are present on a single line, and the three may have priority levels of 3, 1, 6, respectively. After address assignment, the slave 1, the slave 2, and the slave 3 determine the data transmission order of the 2 nd, 1 st, and 3 rd, respectively.
After the addresses are allocated, the slave device measures and converts the environment quantity, and then sequentially outputs the environment quantity to a single line according to the data transmission sequence of the slave device, and the single line is acquired by an upper computer. In the foregoing example, the host computer will continuously read three rounds of data, namely the outputs of slave 2, slave 1 and slave 3.
It should be noted that, the method provided in the present solution is mainly aimed at a single-wire communication method corresponding to a single-wire when a plurality of slave devices are mounted on a single wire. In practical application, if only one slave device is mounted on a single line, dynamic address allocation is not needed, and the slave device directly transmits data.
In determining the data transmission order of the slave device, it may be implemented based on the following manner:
each slave device uses a nonvolatile memory such as Fuse, OTP, EPROM, EEPROM to store a value in binary format as its own priority level.
The slave device having the smaller value of the priority class has the earlier data transmission order.
All slaves mounted on the same single line must have respective different priority levels.
As an implementation manner, the flow of dynamic address allocation in this embodiment may be described with reference to fig. 3, and fig. 4 is a schematic diagram of the flow of dynamic address allocation in the single-master multi-slave single-wire communication method provided by the present invention, as shown in fig. 4, where the flow may include:
Step 1: the upper computer sends a reset pulse to control all slave devices on the single line to enter an address allocation state.
Step 2: the upper computer starts the data pulse and reads the response bit. If the data is 0, indicating that the slave device responds, and continuing the step 3; if the data is 1, it indicates that there is no slave device response and the address allocation is ended.
Step 3: the upper computer starts n data pulses and reads the priority level Pn.1. The arbitration mechanism ensures that there is no data collision for each round of reading and reads out the lowest priority level of the values that are assigned to participate in the round.
Step 4: a round of allocation is completed, and the slave device with the priority level of Pn:1 is allocated with the address of round number a.
Repeating the steps 2, 3 and 4 until the process is finished.
After the address allocation is finished, the flow of data transmission by the slave device may be described with reference to fig. 5, and fig. 5 is a schematic diagram of the flow of data transmission by the slave device in the single-master multi-slave single-wire communication method provided by the present invention, which may include:
step 1: the upper computer sends an enabling pulse to control all slave devices on the single line to start measuring the environmental quantity.
Step 2: the upper computer polls the single line. If the query result is 0, indicating that the slave device does not finish measurement; if the query result is 1, which indicates that all slave devices have completed measurement, step 3 may be started.
Step 3: the upper computer starts m data pulses and reads the measurement data Dm 1. After address assignment, all slave devices have confirmed their own transmission order, so no data collision occurs at this stage.
Step 4: one round of acquisition is completed. If the slave device searched in the address allocation stage has not been completely traversed, the process returns to step 3, otherwise the data acquisition stage is ended.
According to the scheme in the embodiment, the slave devices are controlled to enter the working state based on the pulse, dynamic address allocation is carried out for all the slave devices on a single line based on a single line arbitration mechanism, and the data transmission sequence of the plurality of slave devices on the single line is determined based on the dynamic address, so that conflict-free simultaneous access to the plurality of slave devices on the single line is realized, new pulses are defined, and only the two pulses (reset pulses and enable pulses) are used for starting action. A set of address assignment flows is defined. After the addresses are allocated to all the slave devices, all the slave devices are sequentially sent out.
The prior art is a memory fixed storage address. The addresses are fixed, the addresses are dynamically allocated in the scheme, the address allocation determines the sending sequence, the slave machine finishes data sending according to the sending sequence, single-wire data transmission is based on pulses, the slave device addresses are dynamically allocated based on a single-wire arbitration mechanism, conflict-free simultaneous access to a plurality of slave devices is realized based on the dynamic addresses, the plurality of slave devices can be accessed simultaneously without any command format, the waste of the operation resources of the upper computer and the communication power consumption of the slave devices in the prior art is solved, and the communication efficiency is effectively improved.
Based on the same thought, the embodiment of the specification also provides a single-master multi-slave single-wire communication device. Fig. 6 is a schematic structural diagram of a single-master multi-slave single-wire communication device according to the present invention. The device is applied to a single-wire communication system, and the single-wire communication system comprises: the host computer, slave device and single line, have a plurality of slave devices on the single line, as shown in fig. 6, can include:
a signal pulse starting module 610, configured to start a signal pulse by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
a dynamic address allocation module 620, configured to perform dynamic address allocation for all the slave devices on a single line;
a data transmission order determining module 630, configured to determine the data transmission order of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
and the data acquisition module 640 is configured to acquire the data sent by the slave device by using the upper computer, so as to complete single-wire communication.
Based on the apparatus in fig. 6, some specific implementation modules are described below:
Optionally, the dynamic address allocation module 620 may specifically include:
the upper computer sends a reset pulse to control all slave devices on the single line to enter an address allocation state;
the data pulse starting unit is used for starting data pulses by the upper computer and reading response bits;
the priority reading unit is used for determining that the slave equipment responds if the data of the response bit is 0, starting a first number of data pulses by the upper computer, and reading the priority of the corresponding slave equipment; the priority level corresponding to all the slave devices is a numerical value stored in a binary number format by using a nonvolatile memory by each slave device;
the single round address allocation unit is used for ensuring that no data conflict exists in each round of reading by utilizing a single line arbitration mechanism, and reading out the priority level with the smallest numerical value participating in the round allocation to finish the single round address allocation; the data pulses include data 1 pulses and data 0 pulses;
if the data of the response bit is 1, determining that the slave device does not respond, and ending address allocation.
Optionally, the single wire can be connected to a power supply through a pull-up resistor to form a drain electrode open circuit; the open drain circuit has a line and a characteristic; the line and characteristic indicates that if any one of the slave devices outputs 0, a single line outputs 0; if all slave devices output 1, outputting 1 by a single line;
The dynamic address allocation module 620 may specifically be configured to:
and determining the slave device outputting the residual bit of the output 0 based on the line and the characteristics, wherein the slave device outputting the output 1 loses control over the single line, exits the current round of allocation, releases the single line and waits for the next round of allocation again.
Optionally, the apparatus may further include:
the data output module is used for the slave equipment to sample a single line while outputting own data;
the judging module is used for determining that no data conflict occurs in the bit if the output self data and the sampling single line are both 1;
if the self data and the sampling single line which are output are both 0, determining that no data conflict occurs in the bit or the data conflict occurs, and winning arbitration by the self;
if the self data output is 1 and the sampling single line is 0, determining that data conflict occurs in the bit and self does not win arbitration;
and if the self data output is 0 and the sampling single line is 1, determining that the circuit is connected with faults.
Optionally, the apparatus may further include:
the priority level output module is used for outputting the priority level of the slave equipment on the single wire to the single wire at the same time in the address allocation stage; slave devices mounted on the same single line have different priority levels respectively;
The priority level comparison module is used for comparing all the priority levels output by the slave equipment, and the smaller the priority level value is, the higher the corresponding single-wire arbitration priority is;
and the dynamic address allocation module is used for carrying out dynamic address allocation on the slave equipment based on the priority level.
Based on the same thought, the embodiment of the specification also provides single-master multi-slave single-wire communication equipment. Fig. 7 is a schematic structural diagram of a single-master multi-slave single-wire communication device provided by the invention. The apparatus is applied to a single-wire communication system including: the host computer, slave device and single line, have a plurality of slave devices on the single line, the equipment can include:
the communication unit/communication interface is used for starting signal pulses by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
a processing unit/processor for dynamically allocating addresses to all the slave devices on a single line;
determining the data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
And the upper computer acquires the data sent by the slave equipment to complete single-wire communication.
As shown in fig. 7, the terminal device may further include a communication line. The communication line may include a pathway to communicate information between the aforementioned components.
Optionally, as shown in fig. 7, the terminal device may further include a memory. The memory is used for storing computer-executable instructions for executing the scheme of the invention, and the processor is used for controlling the execution. The processor is configured to execute computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the invention.
As shown in fig. 7, the memory may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), a compact disc read-only memory (compact disc read-only memory) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, without limitation. The memory may be stand alone and be coupled to the processor via a communication line. The memory may also be integrated with the processor.
Alternatively, the computer-executable instructions in the embodiments of the present invention may be referred to as application program codes, which are not particularly limited in the embodiments of the present invention.
In a specific implementation, as one embodiment, as shown in FIG. 7, the processor may include one or more CPUs, such as CPU0 and CPU1 in FIG. 7.
In a specific implementation, as an embodiment, as shown in fig. 7, the terminal device may include a plurality of processors, such as the processor in fig. 7. Each of these processors may be a single-core processor or a multi-core processor.
Based on the same thought, the embodiment of the present disclosure further provides a computer storage medium corresponding to the above embodiment, where instructions are stored, and when the instructions are executed, the single-master multi-slave single-wire communication method in the above embodiment is implemented.
The above description has been presented mainly in terms of interaction between the modules, and the solution provided by the embodiment of the present invention is described. It is understood that each module, in order to implement the above-mentioned functions, includes a corresponding hardware structure and/or software unit for performing each function. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The embodiment of the invention can divide the functional modules according to the method example, for example, each functional module can be divided corresponding to each function, or two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present invention, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.
The processor in this specification may also have a function of a memory. The memory is used for storing computer-executable instructions for executing the scheme of the invention, and the processor is used for controlling the execution. The processor is configured to execute computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the invention.
The memory may be, but is not limited to, read-only memory (ROM) or other type of static storage device that can store static information and instructions, random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, but may also be electrically erasable programmable read-only memory (EEPROM), compact disc-read only memory (compact disc read-only memory) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be stand alone and be coupled to the processor via a communication line. The memory may also be integrated with the processor.
Alternatively, the computer-executable instructions in the embodiments of the present invention may be referred to as application program codes, which are not particularly limited in the embodiments of the present invention.
The method disclosed by the embodiment of the invention can be applied to a processor or realized by the processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The processor may be a general purpose processor, a digital signal processor (digital signal processing, DSP), an ASIC, an off-the-shelf programmable gate array (field-programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.
In a possible implementation manner, a computer readable storage medium is provided, where instructions are stored, and when the instructions are executed, the computer readable storage medium is used to implement the method in the above embodiment.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user equipment, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, e.g., floppy disk, hard disk, tape; optical media, such as digital video discs (digital video disc, DVD); but also semiconductor media such as solid state disks (solid state drive, SSD).
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. A single-master multi-slave single-wire communication method, characterized in that the method is applied to a single-wire communication system, the single-wire communication system comprising: the method comprises the steps of enabling the host computer to perform data transmission, enabling the slave devices to perform data transmission, and enabling the slave devices to perform data transmission, wherein the single line is provided with a plurality of slave devices, and the method comprises the following steps:
the upper computer starts signal pulses; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
dynamic address allocation is carried out for all slave devices on a single line;
determining the data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
the upper computer acquires the data sent by the slave equipment to complete single-wire communication;
the dynamic address allocation for all the slave devices on the single line specifically comprises the following steps:
when the output of the slave devices is different, determining that the single line has data conflict, and sending a reset pulse by the upper computer to control all the slave devices on the single line to enter an address allocation state;
the upper computer starts a data pulse and reads a response bit;
If the data of the response bit is 0, determining that the slave device responds, starting a first number of data pulses by the upper computer, and reading the priority level of the corresponding slave device; the priority level corresponding to all the slave devices is a numerical value stored in a binary number format by using a nonvolatile memory by each slave device;
the single-wire arbitration mechanism is utilized to ensure that no data conflict exists in each round of reading, and the reading result is the priority level with the minimum numerical value participating in the round of allocation, so that the single round of address allocation is completed; the data pulses include data 1 pulses and data 0 pulses;
if the data of the response bit is 1, determining that the slave device does not respond, and ending address allocation.
2. The method of claim 1, wherein the single wire is connected to a power supply through a pull-up resistor to form a drain open circuit; the open drain circuit has a line and a characteristic; the line and characteristic indicates that if any one of the slave devices outputs 0, a single line outputs 0; if all slave devices output 1, outputting 1 by a single line;
the dynamic address allocation for all the slave devices on the single line specifically comprises the following steps:
and determining the slave device outputting the residual bit of the output 0 based on the line and the characteristics, wherein the slave device outputting the output 1 loses control over the single line, exits the current round of allocation, releases the single line and waits for the next round of allocation again.
3. The method according to claim 2, wherein the method further comprises:
the slave device samples a single line while outputting self data, and if the self data and the sampling single line which are output are both 1, the slave device determines that the corresponding bit has no data collision;
if the self data and the sampling single line which are output are both 0, determining that the corresponding bit has no data conflict or the data conflict occurs, and winning arbitration by the self;
if the self data output is 1 and the sampling single line is 0, determining that the corresponding bit has data conflict and does not win arbitration;
and if the self data output is 0 and the sampling single line is 1, determining that the circuit is connected with faults.
4. The method of claim 1, wherein said dynamically assigning addresses to all of said slave devices on a single line is preceded by:
all slave devices on the single line simultaneously output own priority level to the single line; slave devices mounted on the same single line have different priority levels respectively;
comparing all priority levels output by the slave devices, wherein the smaller the numerical value of the priority level is, the higher the corresponding single-wire arbitration priority level is;
And carrying out dynamic address allocation for the slave equipment based on the priority level.
5. The method of claim 1, wherein the host computer obtains the data sent by the slave device to complete single-wire communication, and specifically comprises:
the upper computer sends the enabling pulse and controls all slave devices on the single line to start measuring the environmental quantity;
the upper computer polls the single wire, and if the query result of the single wire is 0, the slave device is determined to have not completed measurement;
if the single-line query result is 1, determining that all slave devices have finished measuring;
and when the slave devices all finish measurement, the upper computer starts a second number of data pulses, reads measurement data and finishes one round of data acquisition.
6. The method according to claim 5, wherein the slave device entering the working state performs data transmission according to the data transmission sequence, specifically including:
and after the slave equipment measures and converts the environment quantity, the environment quantity is sequentially output to a single line according to the data transmission sequence of the slave equipment and is acquired by the upper computer.
7. A single-master multi-slave single-wire communication device, the device being applied to a single-wire communication system comprising: the host computer, slave device and single line, have a plurality of slave devices on the single line, the device includes:
The signal pulse starting module is used for starting signal pulses by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
the dynamic address allocation module is used for carrying out dynamic address allocation on all the slave devices on a single line;
a data transmission sequence determining module, configured to determine a data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
the data acquisition module is used for acquiring the data sent by the slave equipment by the upper computer and completing single-wire communication;
the dynamic address allocation module specifically comprises:
the upper computer sends a reset pulse to control all slave devices on the single line to enter an address allocation state;
the data pulse starting unit is used for starting data pulses by the upper computer and reading response bits;
the priority reading unit is used for determining that the slave equipment responds if the data of the response bit is 0, starting a first number of data pulses by the upper computer, and reading the priority of the corresponding slave equipment; the priority level corresponding to all the slave devices is a numerical value stored in a binary number format by using a nonvolatile memory by each slave device;
The single round address allocation unit is used for ensuring that no data conflict exists in each round of reading by utilizing a single line arbitration mechanism, and reading out the priority level with the smallest numerical value participating in the round allocation to finish the single round address allocation; the data pulses include data 1 pulses and data 0 pulses;
if the data of the response bit is 1, determining that the slave device does not respond, and ending address allocation.
8. A single-master multi-slave single-wire communication device, the device being for use in a single-wire communication system, the single-wire communication system comprising: the host computer, slave device and single line, have a plurality of slave devices on the single line, the equipment includes:
the communication unit/communication interface is used for starting signal pulses by the upper computer; the signal pulse comprises a reset pulse, an enable pulse and a data pulse; the reset pulse and the enable pulse are used for controlling the slave device to enter a working state;
a processing unit/processor for dynamically allocating addresses to all the slave devices on a single line;
determining the data transmission sequence of all the slave devices based on the allocated dynamic addresses; the slave equipment entering the working state performs data transmission according to the data transmission sequence;
The upper computer acquires the data sent by the slave equipment to complete single-wire communication;
the dynamic address allocation for all the slave devices on the single line specifically comprises the following steps:
when the output of the slave devices is different, determining that the single line has data conflict, and sending a reset pulse by the upper computer to control all the slave devices on the single line to enter an address allocation state;
the upper computer starts a data pulse and reads a response bit;
if the data of the response bit is 0, determining that the slave device responds, starting a first number of data pulses by the upper computer, and reading the priority level of the corresponding slave device; the priority level corresponding to all the slave devices is a numerical value stored in a binary number format by using a nonvolatile memory by each slave device;
the single-wire arbitration mechanism is utilized to ensure that no data conflict exists in each round of reading, and the reading result is the priority level with the minimum numerical value participating in the round of allocation, so that the single round of address allocation is completed; the data pulses include data 1 pulses and data 0 pulses;
if the data of the response bit is 1, determining that the slave device does not respond, and ending address allocation.
9. A computer storage medium having instructions stored therein which, when executed, implement the single master multi-slave single wire communication method of any one of claims 1 to 6.
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| US20030023777A1 (en) * | 2001-07-27 | 2003-01-30 | Ken Fields | Dynamic address assignment for one-wire interface |
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| US7606955B1 (en) * | 2003-09-15 | 2009-10-20 | National Semiconductor Corporation | Single wire bus for connecting devices and methods of operating the same |
| CN207266039U (en) * | 2017-10-25 | 2018-04-20 | 福州思飞信息技术有限公司 | A kind of single line anti-collision competitive mode bus network |
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